By Dr. Phil Garrou, Contributing Editor
G450 – 450mm wafer status report
For most of us, whether we work in the FEOL or in packaging, what we want to know about the attempted move to 450mm wafers is (1) if it will really happen and if so (2) when will it happen. Unfortunately, those answers are not yet clear. The recent G450C update at SEMICON Europa shared some new information, but we really cannot expect such a highly politicked program to ever come out and say “This just isn’t going to work.”
G450C is a collaborative consortium being run at the Albany nano tech center. Members are Intel, TSMC, GlobalFoundries Samsung and IBM. IBM, recall has sold off all production capability to GF, so this program, to them, is really a window on what can be done, not something they will commercialize.
The consortium goal is to have a “full flow 14/10nm process capability on line by 2016.” Of interest was their tool installation status report as shown below.
In terms f process readiness, they reported the following:
- Process Capability demonstrated on 98% 14nm process steps
- Productivity: 80% of process tools can achieve 300mm equivalent or better (WPH)
- Performance: Process tools at or near 300mm process targets
- Suppliers can deliver HVM tools in 18-24 months after signals
- Potential die cost savings of >30% achievable
Panasonic – Plasma Dicing
Panasonic reports that plasma based dicing is both damage free and results in more die per wafer due to the narrower dicing streets. Panasonic reports etch rates of 20m/min with their APX300 HVM tool.
In addition, the fracture strength of the silicon is greatly increased.
Front side and backside process flows are shown below.
Fraunhoffer EMFT – Ultra-thin devices in flexible packages
Christof Landesberger of Fraunhoffer EMFT discussed their program to develop a processing scheme for embedding and interconnection of ultra-thin IC devices in flexible chip foil packages.
Target applications include:
- Smart phones – Reduce package thickness
- Healthcare and Wearables
- Large area electronics; e. g. bendable displays and photovoltaic modules
- Sensors on curved surfaces; to be adapted or integrated to machines, buildings, robots, housings
- IoT applications
The key question to be answered is: “Will there be increased mechanical robustness of ultra-thin silicon die after embedding them in films?”
They report a strong increase in breaking force for ultra thin silicon after embedding as shown in the following weibull plot.
Their process flow is sown below.
In their micro controller demonstrator, 25um thick die are inserted in the cavities on the flexible substrate. The chips are covered by 10um of thin film dielectric and patterned and connected. The final packages showed no cracking or delamination after bending.
Their initial conclusions are hat rigid packages will be used for 50-150um thick die and such flexible packages will be used for ultra thin, 10-30um die.
Osram – review of chip interconnection in LED packages
Standard LED packages remain lead frame based. They are:
– easy to assemble by standard SMT reflow
– show the lowest manufacturing cost
– integral solder pad with excellent heat sinking
– single WB interconnect with proven reliability
A multitude of packaging configurations are available and are being used.
Die attach methods include conductive epoxies, non conductive silicones, sinterable materials and eutectic metal solders which all provide different thermal performance and cost and ae better compatible to different packages.
Amongst other things, they conclude:
– When comparing acrylate based silver filled die attach to their epoxy counterparts Osram finds that the acrylates show less stable interconnection after solder heat treatment.
– Corrosive gasses like moisture, NO2 and SO2 diffuse through clear silicone encapsulant. Attack on copper is even worse. Hybrid silicones should be used as well as Ni diffusion barriers for copper gold plated surfaces.
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