Author Archives: sdavis

IFTLE 383 Global Foundries “Adv Packaging Trends in the Foundry Space”

By Dr. Phil Garrou, Contributing Editor

At the recent IMAPS Device Packaging Conference outside Phoenix Hamid Eslampour, CMOS BU Product Management, of GlobalFoundries (GF) discussed Advanced Packaging in the Foundry Space.

Eslampour indicated that todays networking, machine learning, and other high-end computing applications have created the need for architectures that allow for processing of massive amount of data located in nearby memory through communication with the CPU/ GPU with low latency, parallel processing, and high data rate.

To enable these solutions, advanced Si nodes with High-Speed-SERDES (HSS), enhanced HBM-PHY, and highly integrated package technologies are required. The packaging solutions they see providing the level of integration required include MCM, 2.5D, and 3D.

The challenge for foundries such as GF is to enable these solutions through co-design with the customer within a business model that provides the package design, technology integration, and OSAT manufacturing processes required.

High bandwidth and high performance computing technologies for silicon and packaging are shown below. Such high performance devices will require < 40um pitch copper pillar bumping and fine line interconnect (< 10/10 L/S).

fig 1-2

14nm designs are in customer development with 7nm and beyond designs in pathfinding.

fig 2-2

Current GF interposer capabilities are shown below and include 10um TSV on 40um pitch, up to 3 metal layers of 0.8um L/S interconnect:



GF has the following supply chain in place:

fig 3

Higher bandwidth trends drive higher number of HBM stacks, larger silicon interposers and larger power dissipation issues.

For all the latest on Advanced packaging, stay linked to IFTLE…

IFTLE 382 Semiconductor Activity in China – Betting on AI

By Dr. Phil Garrou, Contributing Editor

China is by far the largest consumer of semiconductors reportedly accounting for 45 percent of the worldwide demand for chips, used both in China and for exports. More than 90 percent of its consumption relies on imported ICs.

At the end of 2016 IC Insights reported that China was responsible for ~ 11% of the worlds wafer capacity.

fig 1

China has been working to reduce its dependence on technology imports, including computer chips for several years. In March, it was reported that state-backed China Integrated Circuit Industry Investment Fund Co. is in talks with government agencies to raise at least $24B to build up China’s domestic semiconductor industry. Recently, the Wall Street Journal reported that China is poised to announce a new fund of ~ $47B for development of its semiconductor industry and close the technology gap with the U.S. and other rivals.[link]

While the existence of such a fund has been rumored for months, the size of the fund has been hard to pin down. A few weeks ago, Reuters reported that the fund would be $19B, while Bloomberg reported $31.5B two months ago. The exact number appears to be under consideration among the Chinese leadership, and tied to the increasingly tense trade negotiations with the United States. If $47B is indeed the correct number, it would be identical in size to the $47 billion fund that was financed by Tsinghua University, to spur the development of an indigenous semiconductor industry back in 2015.

While China is playing catchup in many semiconductor areas, it has also been placing its bets on new areas like 5G wireless and AI (artificial intelligence) chips. [link].

China releases its first cloud AI chip

Beijing artificial intelligence (AI) chip maker Cambricon Technologies Corp Ltd has just announced two new products, a cloud-based smart chip Cambricon MLU100 and a new version of its AI processor, Cambricon 1M, in Shanghai on May 3rd.

The cloud chip MLU100, developed by China’s Cambricon Technology, is China’s first cloud artificial intelligence (AI) chip developed to have big data processing ability, for image and voice searching [link].

fig 2

Cambricon 1M is the company’s third generation AI chip (gen 1 was in 2015) for “edge devices.” An edge device is a device which provides an entry point into enterprise or service provider networks such as routers, routing switches, integrated access devices (IADs), multiplexers, and WAN (wide area network) access devices. Using TSMC 7nm technology, the AI chip can be used in smartphones, smart speakers, cameras, and smart driving.

Cambricon MLU100 supports cloud-based machine learning, including vision, audio and natural language processing. It can process under complex scenarios, such as “…with huge amounts of data, multi-tasks, multi-modality and low latency.” This processor reportedly can provide 166 TFLOPS in high-performance mode with energy consumption of no more than 110 watts at peak. The MLU100 is built with TSMC 16nm technology.

Lenovo has announced that their ThinkSystem SR650 server is based on the MLU100. Products built around MLU100 were also announced by Sugon and iFlytek who also announced collaboration with Cambricon [link]

For all the latest on Advanced Packaging, stay linked to IFTLE…


By Dr. Phil Garrou, Contributing Editor

TSMC Introduces WoW Technology

At the TSMC Technology Symposium in Santa Clara, the company discussed their new Wafer-on-Wafer (WOW) silicon wafer stacking technology for the 7 and 5nm nodes. The “new” technology connects chips on two silicon wafers reportedly using 10um TSV. Those of us who have been following 3DIC for over a decade recognize this as W2W 3DIC. Even the name isn’t new, since Fujitsu introduced their version of WoW technology in 2010 which we discussed way back in in IFTLE 181.

TSMC first teased us with this potential technology back in 2014 at the IEEE IEDM.


The TSMC technology stacks and interconnects die while still part of the full silicon wafers vs their previous 2.5D technology CoWoS that uses silicon interposers. The advantage is obviously that this tech connects all die on two wafers in one process step. In terms of performance, direct 3D stacking has always been known as the highest performance lowest latency solution.
As we have known for a decade at least, there are several issues with W2W technology: (1) yield – bad die on wafer 1 will be connected to good die on wafer 2 resulting in a bad stack. This precludes this technology from being a viable solution for silicon that doesn’t already offer high wafer yields. Ideally, TSMC reports that chip yields should be 90% or higher to use TSMC’s Wafer-on-Wafer technology. (2) quite obviously this technology is most relevant for low-power silicon, where heat is less of an issue and (3) Also importantly, readers of IFTLE know that this solution works best for chips that are identical like memory stacking, but not for ships of different sizes and different I/O configurations which would require redistribution (RDL) before alignment and stacking is possible, thus increasing cost.

So far, TSMC has reportedly achieved “2-layer stacks, in which two silicon layers that are mirror images of each other (for perfect alignment), sandwich bonding layers, through which pins for the upper layer pass through.”

Since TSMC currently manufactures graphics cards for both AMD and Nvidia and there are some predicting that we will see stacked GPUs from the WoW technology. “There won’t be latency problems between the connected GPUs as the wafer has the ability to let the GPUs communicate quickly, meaning we could see dual-GPU graphics cards based on current GPUs like the Polaris and Pascal GPUs from AMD and NVIDIA, respectively.” [link]

Certainly they wouldn’t be hyping the technology if there weren’t real customers urging them to move forward with it. It will be interesting to see if they give a more complete description of WoW at the IEEE ECTC in a few weeks. If so be sure that IFTLE will get you the details.

What about designing these complicated structures ??

Cadence Teams with TSMC for full WoW Design Flow

Cadence has announced that its full suite of Cadence digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology. [link]

Cadence announced a new WoW reference flow to complement their other TSMC integration solutions ( InFO and CoWoS). They described the following design flows, tools and methodologies that will enable TSMC customers to manage the top-level connectivity and verification of their chip integration solutions as part of the overall design process as follows:

  • Innovus™ Implementation System: Supports single database top-die including front/back-side routing and backside-through-silicon-via (BTSV) support, creating connections between multiple dice
  • Quantus™ Extraction Solution: Supports back-side routing layers, sub-circuit replacement for BTSV and die-to-die interface coupling capacitance extraction, enabling electrical analysis between the dice
  • Voltus™ IC Power Integrity Solution: Provides die-level power map generation, enabling concurrent power analysis of multiple dice
  • Tempus™ Timing Signoff Solution: Provides multi-die static timing analysis (STA) support, enabling a checking of timing paths that cross multiple dice
  • Physical Verification System (PVS): Offers design rule checking (DRC) and layout vs. schematic (LVS) for die with BTSV, interface alignment and connectivity checks, ensuring that the two dice connect properly
  • Virtuoso® Platform: Includes features for bump placement and alignment on top of the existing PDK via the Virtuoso Incremental Technology Database (ITDB), creating connections between multiple dice
  • OrbitIO™ interconnect designer: Provides interface connectivity,  device flattening, port connectivity and configurable module definitions to manage top-level connectivity, enabling unified planning of die interconnect and alignment
  • Sigrity™ PowerSI® 3D-EM Extraction Option: Offers electrical modeling of the combined die and interposer, validating that the power and ground distribution is sufficient for multiple dice
  • Sigrity PowerDC™ technology: Thermal analysis solution with interposer and die analysis capabilities that allow co-simulation with Voltus IC Power Integrity Solution, enabling inclusion of temperature into concurrent electromigration analysis of multiple dice
  • Sigrity XcitePI™ Extraction:  Provides accurate interposer-level interconnect model extraction, enabling validation of high-speed signal propagation in the time and frequency domains
  • Sigrity SystemSI™ technology: Automatic construction of complete model-based interconnect topologies used to drive simultaneous switching noise (SSN/SSO) analysis for concise eye-diagram validation

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFLE 380 IMAPS Device Packaging Conf Part 3: Yole Updates FO-WLP

By Dr. Phil Garrou, Contributing Editor

This week, let’s take a look at the latest Yole update on Fan out Packaging by Jerome Azemar that was presented at the IMAPS 2018 Device Packaging Conference.

As we have discussed before, fan out packaging can be embedded in laminate or embedded in mold cmpd (EMC) . Chips can be placed face up or down with various options for interconnections.

yole 1-2

Their look inside a smartphone gives an interesting perspective on where fan out packages are being used and where they can be used.

yole 2-2

Yole sees automotive radars as an interesting market for fan out solutions

– fan out used in Rf and radar applications

– since 2015 Infineon has shipped > 10MM Radar IC in eWLB packages

Yole reports that technical challenges still exist for fan out as shown below:

yole 3-2


They see high density fan out (like TSMCs InFO) fan out being in competition in the future for HPC (high performance computing) and AI (artificial intelligence) applications with silicon 2.5D solutions.

While panel production would certainly reduce costs (more units per operation) such technology is not ready and will have large capital equipment costs. They see production being mainly on wafer through 2022.

fowlp iftle 380


CMOS Image Sensor Market

IC Insights Optoelectronic, Sensor, and Discrete report concludes that the CMOS Image sensor market is not approx. the same size and growth rate as the LED business [link]. An interesting comparison…

CIS market

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 379 IMAPS DPC 2018: Chip to Wafer Hybrid Bonding

By Dr. Phil Garrou, Contributing Editor

IFTLE has extensively discussed the applicability of the Ziptonix technologies (acquired and now owned by Xperi): ZiBond (oxide-oxide bonding) and DBI (copper-oxide to copper-oxide “hybrid bonding”) [for example see IFTLE 303, “Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7” and refs therein]

These technologies have now been commercialized in areas such as COS image sensors, Rf and MEMS. These are all wafer to wafer bonding applications. As of yet, a die-to-wafer process has not been developed for manufacturing, imposing W2W limitations such as the requirement that die sizes match and yields are high.

experi 2-2

At the recent IMAPS Device Pkging Conf in March, Wang of Xperi discussed the “Design, characterization and testing of large area and high density 3D direct bond interconnect which discussed development of such a die to wafer technology.

DBI’s key attribute is the formation of electrical interconnects at low temperatures and pressures as shown below:

experi 3-2

The technology requires highly polished (CMP’ed) surfaces (less than 1nm deviation across wafer surface topology is typical) .

The Xperi goal was expressed as developing a process for HBM memory stacks by stacking 4 double sided DBI memory die with the following attributes:

– throughput – 3000uph                       – no underfill

– no solder                                             – stack consecutively then batch anneal

For die to wafer bonding they followed he following process sequence:

experi 4

The design that was evaluated for a HBM stack contained 10um pads on 40um pitch.

D2W vs W2W electrical test for their test vehicle is shown below:

experi 5

Die to wafer reliability for a 31K daisy chain are shown below:

experi 6

It will be interesting to see whether this data will extrapolate to the fabrication of real HBM die stack in the future.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 378 IBM/DARPA ICECool Program Summary; Apple to Inc use of Apple Chips

By Dr. Phil Garrou, Contributing Editor

The March Issue of Electronic Cooling magazine contains a great summary article on the IBM effort in the DARPA ICECool Program [link]. I recommend reading the full article which I will summarize here.

When today’s standard cooling technology, air cooling with fans, does not meet the required needs, advanced water cooling approaches are examined. Traditional water cooling approaches replace the heat sink with a cold plate that provides more efficient heat transfer. But, because of its electrical conductivity, water cooling requires isolation measures to protect the chip, and requires large channels to cool large high-power die at reasonable pressure drops.

As part of the DARPA ICECool program, seeking to develop appropriate cooling technologies for 3D chip stacks, IBM developed a new chip-embedded cooling approach, utilizing a nonconductive fluid, doing away with the need for a barrier between the chip electrical signals and the fluid. This chip-embedded cooling technology pumps a heat-extracting dielectric fluid into ~100μm cooling channels, between the chips at any level of the stack. The coolant removes the heat from the chip by boiling from liquid-phase to vapor-phase. It then re-condenses, dumping the heat to the ambient environment. Since this system doesn’t need a compressor, it can operate at much lower power compared to typical refrigeration systems.


The dielectric coolant is fed in at the center of the die, moves through radially expanding channels, and exits at the edges of the die. This approach (shown below) provides better energy efficiency and maximum critical heat flux with the resulting reduced flow path.

To modify an IBM microprocessor module for embedded cooling the package lid was removed to expose the processor die, a deep reactive ion etch (DRIE) of the processor die was performed to generate the 120 µm deep cooling channels structures in the backside the processor and a glass die was bonded to the etched processor die to create the top wall of the micro-channels and a brass manifold lid, which provides for coolant supply and return, was bonded to the glass manifold die and the organic substrate using an adhesive. The coolant enters the module and passes through 24 inlet orifices to distribute the flow among the corresponding 24 radial expanding channels as shown below.


The figure below compares the performance of the standard air cooled module with the new embedded liquid cooled module. The cores temperature were measured with coolant inlet temperature in both cases at 25 ºC; a dielectric coolant mass flow rate of 9 kg/hr at a pressure drop of ~11 psi. The temp of the air-cooled processor levels off at around 70 ºC as the system fans speed up (~65%) to prevent overheating whereas the liquid cooled system is running at 40 – 45 ºC. At the highest power operation (4.3 GHz) the reduced operating temperature results in over a 10 watt decrease in the power consumed by the microprocessor along with a significant reduction in fan power (15+W) .


Apple to Replace Intel chips in Macintosh Computers

Bloomberg is reporting that Apple, which has used Intel processor chips in its computers since 1995, is planning to use its own chips in Mac computers beginning as early as 2020 (code-named Kalamata), replacing processors from Intel (link).

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 377 μ-Transfer Printing going mainstream?; Heterogeneous Int at IMAPS DPC

By Dr. Phil Garrou, Contributing Editor

OSRAM licenses m-transfer printing from X-Celeprint

IFTLE has discussed m-transfer printing for several years, first with Semprius [ see IFTLE 203 “Apple Acquires LuxVue µ-assembly Technology” ] and then at licensee X-Celeprint [see IFTLE 354 “The Case for µLED Displays”]

We have seen Teledyne using the technology in several DARPA programs and have heard rumors of the technology being used to develop mLED displays.

It now appears that a major player in word wide LED component marketplace has significant interest in the technology because OSRAM now reports that they have entered into a technology and patent licensing agreement with X-Celeprint for their m-transfer printing technology (link)

Exactly how will OSRAM use this technology in their LED products?? We’ll be keeping an eye out and report back to our readers…

Xceleprint 1

μ-transfer printing basics [link]

Heterogeneous Integration Roadmap Update at IMAPS DPC

Starting this week we will begin going over some of the presentations at the IMAPS Device Packaging Conf held every year outside Phoenix, AZ. At one of the keynote presentations Raja Swaminathan of Intel discussed his work on the Bill Chen Heterogeneous Integration Roadmap.

If you read this blog regularly you have probably picked up on the fact that IFTLE has little tolerance for bad nomenclature and/or redundant nomenclature. So, let’s consider the term “heterogeneous Integration” what this means is basically combining (i.e integrating) things that are not the same (i.e. heterogeneous)…i.e. a DRAM memory module is not heterogeneous integration (but would be homogeneous integration) . So is this something new ?? In the 1990s we called them multichip modules. Today that is also called a SiP. Too many terms meaning nearly the same thing for my liking.

But…given that the community has appeared to latch onto this catch phrase lets look at what the roadmap committee is doing about the naming.

Swaminathan makes the point that on package integration is more compact, low power and higher band width than off package connections (see below).

Intel 1-2

In order to improve on the meaningless terms 2.5D, 2.1D etc they are proposing that we consider these as 2D enhanced architectures as side by side active silicon interconnected at high densities using either organic or silicon based interposers.

intel 2-2

So, TSMC’s CoWoS would be 2DS with TSV, ASEs FoCoS would be 2DO chips last and Intel’s EMIB would be 2DS without TSV.

Intel 3

Technologies are compared I terms of density below:

Intel 4

Swaminathan concludes with a slide showing on of the main themes of IFTLE for the past decade “Packaging technologies will become more wafer-fab like.”

Intel 5


For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 376 ASE / TDK launch ASE Embedded; The AI Ecosystem Develops

By Dr. Phil Garrou, Contributing Editor

ASE, TDK Embedded Chip Joint Venture begins

Taiwan’s ASE has initiated a joint venture with Japan’s TDK Corp to produce embedded packaging solutions in Kaohsiung Taiwan. ASE has 51% ownership in the venture which currently employs 150 people.

With initial capital of $51MM , ASE Embedded Electronics Inc has started operations manufacturing embedded substrates using TDK’s (SESUB) technology (see IFTLE 238 “ASE & the Apple watch, ASE / TDK JV…” and IFTLE 347: “ASE Embedded Packaging Solutions” )

ASE 1-4

AI vs IoT

AI and IoT both buzz words that are predicted to drive the electronics industry over the next decade. ITLE is bullish on AI, not so much on IoT. As I have explained before my opinion is formed from a packaging perspective and while I think AI will need all the latest high end packaging solutions, I still perceive that most IoT will require the absolute lowest cost, stripped down packaging available. AI platforms are an intimate combination of hardware and software but certainly will be requiring the latest that we have to offer in high end packaging solutions.

AI processing will go into home control devices, autos, surveillance systems, airplanes, wearables and things we have yet to think of. AI processing is unique in that traditional customers Amazon, Google and Apple, have begun to design their own AI chips, in hopes of differentiating their products from those of rivals. This has major ramifications for companies like Intel and Nvidia, which will now be competing with their customers.

While I certainly am not an AI expert, we all must quickly up our knowledge in this area which I see leading advanced packaging into the next decade. A list of current participants has recently been compiled (shown in the table below) (link)


Recently on “Graphics Speaks” Kathleen Maher has looked at how some of these cloud companies, IP companies, and the traditional semiconductor companies all have conflicting ambitions in the AI market place . I recommend reading the full article.[link]

While cloud companies like Google appear to be favoring custom chips to augment CPUs and GPUs, Semiconductor and IP companies are designing chips to enable efficient hardware and neural net systems and Intel is proposing an open platform ecosystem based on Xeon, FPGAs, and specialized processors like Nervana and Saffron.


Google’s Tensor Processing Unit (TPU), was introduced last year. Their initial beta customer Lyft, is using AI to recognize surroundings, locations, street signs etc. The cloud-based TPU features 180 teraflops of floating-point performance through four ASICS with 64 GB of high bandwidth memory. These modules can be used alone or connected together via a dedicated network to form multi-petaflop ML supercomputers that they call TPU pods.


The best known mobile AI processor is included in the Apple iPhone X. Apple’s A11 is a 64-bit ARM 6 core CPU with two high performance 2.39 GHz cores called Monsoon, and four energy efficient cores, call Mistral. The A11’s performance controller gives the chip access to all six cores simultaneously. The A11 has three-core GPU by Apple, the M11 motion coprocessor, an image processor supporting computational photography, and the new Neural Engine that comes into play for Face ID and other machine learning tasks.


Amazon is reportedly developing a chip designed for artificial intelligence to work with the Echo and other hardware powered by Amazon’s Alexa virtual assistant (link). The chip should allow Alexa-powered devices to respond more quickly to commands, by allowing more data processing to be handled on the device vs the cloud.


Nvidia has announced its new Volta GPU with 640 tensor cores, which delivers over 100 Teraflops. It has been adopted by leading cloud suppliers including Amazon, Microsoft, Google, Oracle , and others. On the OEM side, Dell EMC, HP, Huawei, IBM and Lenovo have all announced Volta-based offerings for their customers.

Microsoft and Intel’s “Brainwave”

Microsoft has teamed with Intel and is offering their Stratix 10 FPGAS for AI processing on Microsoft Azure (see below) codename “Brainwave” (link) . Intel is proposing FPGAs  + processors for AI work. Intel is reportedly focusing on the Stratix X FPGA as a AI companion to Intel’s Xeon processors.



Intel’s 14 nm Stratix 10 FPGAs accelerate Microsoft’s Azure deep learning platform using FPGAs with “soft” Deep Neural Network (DNN) units synthesized onto the FPGAs instead of hardwired Processing Units (DPUs). Brainwave is designed for live data streams including video, sensor feeds, and search queries.


Intel is making a major play in AI. Intel has multiple processor options for AI, including Xeon, FPGAs, Nervana, Movidius, and Saffron (link).

Saffron Technology was acquired by Intel in 2015. It develops “..cognitive computing systems that use incremental learning to understand and unify by entity (person, place or thing) the connections between an entity and other “things” in data, along with the context of their connections and their raw frequency counts…. Saffron learns from all sources of data including structured and unstructured data to support knowledge-based decision making.” It is being used extensively in the financial services industry.

In 2016, Inte­­­l announced acquired Nervana, a startup developing AI software and hardware for machine learning. In 2017, Intel revealed the Nervana Neural Network Processor (NNP) designed expressly for AI and deep learning.

Intel acquired Movidius in 2016 to get VPU (visual processor unit) technology for machine learning and AI. Intel’s Movidius devices include dedicated imaging, computer vision processing, and an integrated neural compute engine. Applications for VPUs include automobile license readers at bridges and toll roads, airport security screening, drone surveillance and the many applications of facial recognition.

ARM – Trillium Platform

The Arm Trillium Platform includes Machine Learning (ML) and Object Detection (OD) processors with Arm software, and the existing Arm compute library and CMSIS-NN Neural Network kernels.


It will be interesting to see hope the packaging community develops solutions that will be compatible with these advanced high speed HPC applications.

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 375 EVG / IBM Laser Debonding; Samsung Increases Focus on CMOS Image Sensor Mkt

By Dr. Phil Garrou, Contributing Editor

EVG Licenses IBM Laser deBonding Tech

IBM’s Hybrid Laser Release Process has been licensed by EV Group for inclusion in their low-temperature laser debonding equipment (link).

The IBM technology will reportedly help EVG address the industry’s requirements for temporary bonding and debonding, including high throughput, low wafer stress for high yield, and low cost of ownership of the laser equipment, processing and consumables. The EVG offering will encompasses techniques to help protect chips from heat and laser damage, as well as chemical clean technologies for device and carrier wafers.

The IBM technology was first described at the 2010 IEEE ECTC Conf (link)

Post debond cleaning is a topic that is rarely discussed but very significant from a manufacturing standpoint. Following debonding, residual polymer materials are left on the substrate. The residue level is dependent on the ablation condition. Laser fluence and total accumulated number of laser pulses need to be optimized for a given polymer adhesive. After debonding, any residue or remaining polymer adhesive needs to be cleaned prior further processing. The cleaning may be accomplished by several approaches including dry etching or chemical wet etching.



Designed for integration in the company’s benchmark EVG-850DB automated debonding system, EVG’s laser debonding modules incorporate a solid-state laser and optics designed to enable force-free debonding. Featuring both low-temperature debonding and high-temperature-processing stability, EVG’s laser debonding solution is available for a variety of applications including FO-WLP (below), memory stacking, die-partitioning, heterogeneous integration etc.

EVG debonding

Samsung to Challenge Sony on CMOS Image Sensors

Fresh from their overtaking of Intel as the worlds #1 IC Chip producer, ETNews (Korea) reports that Samsung has reportedly now set its sights on Sony and CMOS Image sensors. (link)

Samsung Electronics is reportedly planning to increase its production capacity of image sensors and it has set a goal to become #1 in the image sensor market.

Since 2017, Samsung has reportedly been working to convert its line 11 in Hwasung that was used to produce DRAMs into a line (S4 line) that would be used to produce CMOS image sensors (CIS). Conversion to the S4 line is expected to be completed by end of this year. According to ETNews Korea , when this process is done, Samsung Electronics is going to immediately start the conversion process of its 300mm line 13 in Hwasung, that is used to produce DRAMs, into another line that will be used to produce image sensors. Line 13 line can produce about 100,000 units of DRAMs per month, but because image sensors ae a more complex deposition process, it is expected that production capacity for CIS will be reduced by about 50% after conversion. They further report that Samsung Electronics will have a total production capacity of 120,000 units / mo of CIS after these conversion processes are over.

SONY and Samsung are both commercializing 3D stacked image sensors (sensor + logic + DRAM) that can process 960 frames per second (slo-mo). Samsung Electronics has launched the new ISOCELL Fast 2L3 image sensor for super slow-motion recording (link).

The Samsung ISOCELL Fast 2L3 is a high speed 3 layer 3D stacked CMOS image sensor designed with a 2 Gb LPDDR4 DRAM attached below the analog logic layer. With the integration, the image sensor can temporarily store a larger number of frames taken in high speed quickly onto the sensor’s DRAM layer before sending frames out to the mobile processor and then to the device’s DRAM. This allows the sensor to capture a full-frame snapshot at 1/120 of a second and also to record super-slow motion video at up to 960 frames per second ( 32 times the typical filming speed of 30 fps).


The design is similar to that of Sony who was the first to report integration of DRAM into the 3D CIS stack (see IFTLE 272 “2015 3D ASIP Part 1: Pioneer Awards; Sony 3D stacked CIS; Latest on SPIL Acquisition”)

ETNews reports that the number of customers purchasing Samsung image sensors is currently over 10 as Samsung Electronics is increasing points interactions with major mobile devices and automotive customers.

For all the latest on advanced packaging, stay linked to IFTLE…


IFTLE 374 IMAPS Device Pkging Conf part 1: 3DIncites Award Winners

By Dr. Phil Garrou, Contributing Editor

The 14th Int Conf on Device Pkging was held at its normal site, Ft. McDowell, AZ, last week. I normally show a picture of the general chair of the meeting and I will this time also (below), but I thought it was about time we gave due credit to the IMAPS staff that makes the meeting possible.   Below we see (L to R) Dir of Program Dev, Brian Schieman; Membership Admin, Shelby Moirano and Exec Dir Michael O’Donoghue. Events Mgr Brianne Lamm was back in NC holding down the fort, so to speak.



On Tuesday night, we were all entertained by a local Indian tribe that showed us their various ceremonial dances. Below Chairman Ramm poses with the tribes dancers.

Ramm & the Indians


The most entertaining event of the conference was certainly the 3DInsights awards gala on Wednesday night which included, in addition to the awards ceremony, a barbecue dinner, an awards ceremony quiz and a dress up photo booth.

There were 40 nominees from 26 companies and four research institutes competing for awards in 9 categories. An amazing 40,619 votes were cast online. Winners were:

Device Manufacturer of the Year: Amkor Technology for its acquisition of NANIUM.

Device of the Year: (tie) M-Series ™ Deca Technologies, and OmniVision Technologies. Deca was nominated for their adaptive processing technology combined with planar front side molding. OmniVision was nominated for their Nyxel technology which allows their image sensor to see better and farther under low- and no-light conditions than previous generations.

EDA Supplier of the Year: Mentor, A Siemens Business was nominated in recognition of the efforts of Juan Rey, VP of Engineering, at a number of 3D-IC focused conferences in 2017.

Engineer of the Year: Gill Fountain, Xperi (Ziptronix) was nominated for expanding the chemical mechanical polishing process window for Cu damascene image sensor processing.

Equipment Supplier of the Year: FRT GmbH was nominated in recognition of its third gen surface metrology tools that combine multi-sensor technology and hybrid metrology in one measuring system.

Material Supplier of the Year: Semblant for their MobileShield technology, a nano-coating that protects mobile phones from water damage and corrosion.

Process of the Year: F.A.S.T., KOBUS  was nominated for combining the CVD and ALD deposition.

Research Institute of the Year: Fraunhoffer IZM  was nominated for launching a consortium to bring research and industry together on all questions of implementing panel level packaging (PLP)

The dress up photo booth was certainly lots of fun. Below we see General Chair Peter Ramm, 3DIncites Francoise von Trapp and a group shot of the nights award winners.


Proceeds from the event went to two charities: the IMAPS Microelectronics Foundation, which exists to support student activities related to the study of microelectronic packaging, interconnect and assembly; and Phoenix Children’s Hospital pediatric oncology programs which exists to save children with cancer.

Next week we will start to look at some of the key presentations.

For all the latest in Advanced Packaging, stay linked to IFTLE…