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IFTLE 255: Consolidation continues; ASE acquires SPIL stock; Semicon Taiwan part 2: MediaTek Antenna on Package

By Dr. Phil Garrou, Contributing Editor


One may say that IFTLE has been obsessed with consolidation for the last few years. The reasons for this become obvious when one looks at the increase in recent activity. There are typically ~25 or so acquisitions a year. In 2015, there will 2X that number and the deals, in general are ~10X larger than in the past.

IC Insights has recently pulled together the major M&A activity over the last year.

IFTLE255 Table

In addition, several large M&A agreements announced last year have closed in 2015 including:

  • RF Micro Devices and TriQuint Semiconductor officially completed their Qorvo merger
  • Qualcomm completed its acquisition of CSR in August 2015
  • Cypress completed its acquisition and merger with Spansion in March 015
  • Infineon completed its acquisition of International Rectifier in January 2015
  • IBM completed the sale of its Microelectronics business to GlobalFoundries in July 2015

IC Insights notes that the unprecedented M&A activity is indicative of IC suppliers experiencing slower sales in their existing market segments and the need to broaden their businesses to stay in favor with investors. IFTLE favors the explanation that we have published previously, i.e. many of the segments of our industry are entering late stage 3 and stage 4 where consolidation is the norm. (See IFTLE 241, “Simply Obeying the Laws of Economics”.)

ASE Buys 25 percent of SPIL Stock

Following up on our story about ASE attempting to purchase 25 percent of SPIL (see IFTLE 252, “ASE makes bid for SPIL shares…”), ASE announced on September 22 it has purchased 25 percent shares of SPIL shares, achieving its acquisition goal.

SPIL reiterated that a SPIL-ASE tie-up would not create much synergy, since 85 percent of its customers overlap with ASE’s. “… the acquisition will cause order losses as customers will allocate some orders to a third supplier rather than put all their eggs in one basket,” SPIL stated.

ASE noted that now being a major shareholder of SPIL, the company will be exploring avenues of cooperation with SPIL but otherwise, “ ASE will not intervene in SPIL’s operations and therefore, cannot affect the rights and interests of SPILs current employees.” [Link]

Embedded and Wafer Level Package Technology Forum at Semicon Taiwan

IFTLE255 fig 1Continuing our look at Semicon Taiwan 2015, let’s begin our look at the Embedded and Wafer Level Package Technology Forum led by Mr. Albert Lan (left), Senior Director, SPIL. The theme of the forum was System Integration & Package Solutions for Portable/Wearable/IoT Devices. Mediatek discussed “Packaging Breakthroughs in Wearable Devices”. Unimicron gave a great review of “Innovative Substrate Technology …”;  J Devices discussed their panel level processing efforts and Fraunhoffer IZM discussed results of their fan out panel level processing.



Overall Mediatek sees IoT wearables as requiring:

  • miniaturization which can be achieved with embedding;
  • being substrate less for low cost which is achieved by fan out packaging; and
  • being manufactured on a panel process to minimize cost.

IFTLE255 fig 2Mediatek discussed Aster (MT2502A) a monolithic low-power CMOS chip integrating power management unit, analog baseband and radio circuitry. Based on an ARM RISC processor, it provides a platform for class 12 MODEM and leading-edge multimedia applications.

It also features a Bluetooth transceiver and an FM receiver supporting both audio broadcast de-modulation and RDS/RBDS data decoding. The MT2502A device is offered in a 5.4mm×6.2mm, 143-ball, 0.4mm pitch, TFBGA package. MT2502A provides always-on mode to optimize the low power performance for wearable device. [Link]

IFTLE255 fig 3

Another interesting development is their antenna on package (AoP) technology which they claim offers smaller form factor, better performance and faster time to market, although one must be careful about a properly designed keep-out-zone and proper design to minimize EM interference.

IFTLE 255 fig 4

We’ll finish up with Semicon Taiwan 2015 next week.

For all the latest in 3DIC and other advanced packaging stay linked to IFTLE.

IFTLE 254 Semicon Taiwan Part 1; GaTech Interposer Workshop

By Dr. Phil Garrou, Contributing Editor

System Integration by 3D SiP

cp hungThe forum chairman was CP Hung, who is currently the VP of Corporate R&D for ASE Group, responsible for next generation products development. The System Integration by 3D SiP forum invited global experts to discuss the development of 3DIC and 2.5DIC packaging and alternative solutions. Presentations were made by Cisco, AMD, SK Hynix, ASE, Altera, Amkor, Teledyne and Cadence.



Bryan Black detailed the commercialization of the AMD “Fiji” GPU which has been in development for 8.5 years. It “required the collaboration of 20+ companies and government research organizations”. The four that were key included Amkor, ASE, SK Hynix and UMC.

IFTLE254_Fiji 1

Some of the obstacles that they ran up against are listed below:

IFTLE254_fuji 2

SK Hynix is in production with HBM memory in support of “Fiji”. HBM benefits include:

  • 4096-bit memory interface with four stacks creating 512GB/s of bandwidth
  • 60% higher memory bandwidth6 for 60% less power7 than GDDR5
  • 4X bandwidth per watt improvement from Radeon (TM) R9 290X

SK Hynix

Hongshin Jun of SK Hynix detailed their high bandwidth memory development. Each application has different memory requirements, but most common are high bandwidth (HBM) and low power consumption.

Mass production of their HBMPower consumption and bandwidth are compared for DDR and HBM below:


HBM 2 will show the following properties:


The stacked memory features 25um bumps on 55um pitch.


Min Yoo of Amkor presented their SLIM and SWIFT package architectures. Basically, these are interconnected first technologies with no TSV. SLIM uses back-end foundry technology for <2um L/S, whereas SWIFT uses 2-10um OSAT RDL technology.

IFTLE_amkor 1

GaTech Global Interposer Workshop coming in November

The fifth annual GaTech Interposer workshop is coming Nov 4-6. With 2.5 and 3D being buzzwords, many conferences have interposer presentations. But the GaTech conference does the best job of bringing together practitioners from silicon, laminate and glass segments of this leading edge technology. This year’s conference is led by Rao Tummala (the Godfather of packaging) and Matt Nowak of Qualcomm, and Subu Iyer, who recently retired from IBM to teach at UCLA.

Highlight presentations include:

  • Bob Sankman (Intel) – EMIB packaging
  • Dave McCann (Global Foundries) – ASIC and RF with 2.5D technology
  • Doug Yu (TSMC) – InFO
  • Suresh Ramalingam (Xilinx) – SLIT (a TSV-less interconnect technology)
  • Ron Huemoeller(Amkor) – Advance fan out: SWIFT and SLIM
  • Bryan Black (AMD) – The road to AMD’s Fuji dGPU Chip
  • DC Hu (Unimicron) – Glass manufacturing readiness
  • Tomoyuki Yamada (Kyocera) – Organic interposers

Hope to see you all in Atlanta!

For all the latest on 2.5/3D and other advanced packaging stay linked to IFTLE.

IFTLE 253 China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix; Tezzaron 8 layer 3DIC

By Dr. Phil Garrou, Contributing Editor

China targets GlobalFoundries

In IFTLE 238, we noted that China was the “wild card” when it came to global microelectronics consolidation – with plenty of cash and the government behind them. [link]

China’s National IC Investment Fund, Hua Capital Management, has reportedly approached GlobalFoundries, through an investment bank. Such an acquisition would allow China to secure 14nm FinFET foundry process technology [link 1]. GlobalFoundries’ 14nm process is licensed from Samsung [link 2].

Acquisition of GlobalFoundries would enable SMIC to enter volume production of 14nm FinFET products much earlier than originally planned. SMIC began volume production of 28nm chips in cooperation with Qualcomm and has signed an agreement with Qualcomm, IMEC and Huawei to develop 14nm process with volume production slated for 2020.

Abu Dhabi’s Advanced Technology Investment (ATIC), a major shareholder of GlobalFoundries, is reported to be willing to sell its interest in GF.

In July, China’s Tsinghua Unigroup put a bid in to acquire Micron. On the packaging front, in the last year, Chinese companies have purchased bumping house FCI in Phoenix and the #4 global assembly house STATSChipPAC.

Tessera to Acquire Ziptronix

Tessera Technologies announced the acquisition of Ziptronix for $39 MM [link].

Founded in 2000 as a venture-backed spinoff of RTI International, Ziptronix is a pioneer in the development of low-temperature direct bonding technology for 3D integration.

Ziptronix’s patented ZiBond direct bonding and DBI hybrid bonding technologies. Ziptronix has commercially licensed their ZiBond and/or DBI technologies to Sony Corporation for volume production of CMOS image sensors, to Raytheon and to Tezzaron / Novati.

In 2013, Ziptronix announced an agreement with Tezzaron and Novati Technologies, a wholly owned subsidiary of Tezzaron, selling its 3D IC development lab in Morrisville NC to Tezzaron, to be operated by Novati [link].

Tezzaron Announce 8 Layer 3DIC

At the IEEE 3DIC conference in Japan, Tezzaron and their manufacturing subsidiary, Novati announce the world’s first eight-layer 3D IC wafer stack containing active logic. Claiming “…the transistor and interconnect densities per cubic mm are far higher than achievable with 2D 14nm silicon fabrication.”

Each wafer has 10 layers of copper interconnect supporting high performance CMOS logic – a total of 80 layers of interconnect and 8 layers of transistors in a finished stack as thin as a single conventional die. Tezzaron’s 8-wafer stack contains active CMOS circuitry and tungsten vertical interconnect. Wafers are 20µm thick; SuperContacts are 1.2µm diameter, 6µm deep, and can be deployed at a pitch of 2.4µm. There are no wire bonds, copper pillars, bumps, or underfill between the layers. The wafers were bonded with DBI technology, invented by Ziptronix and now available from Tessera. (see discussion above)


For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 252 ASE Makes Bid for Siliconware Shares; TSMC/Huawei 2.5D Networking Processor; TSMC Closes Solar Business

By Dr. Phil Garrou, Contributing Editor

ASE seeking ~ 25% stake in SPIL

By now, you have seen the news that ASE has made an offer to buy up to 25% of the shares of competitor SPIL at a 34% premium. [link]

For those of you following IFTLE, this attempt at further industry consolidation should not come s a surprise [see IFTLE 163, 195, 231, 241], although some would have predicted that offers for the big 4 OSATS would come from foundries or China Inc, not fellow OSATS.

Although ASE is making statements like “…this is not a hostile takeover” , “…ASE is seeking cooperation rather than competition”, and that this “…is purely a financial investment, and ASE will not intervene in SPIL’s operations” this is the kind of move that clearly precedes a takeover attempt.

ASE and SPIL currently have 19.1% and 10.1% shares, respectively, in the global IC packaging and testing market. The planned ASE-SPIL integration will widen the market gap against rival companies, including Amkor Technology, which has a 12% share and China-based JCET with a 10% share [link]. JCET’s acquisition of STATS ChipPAC was the first major consolidation move amongst the top assembly houses. After acquiring STATS ChipPAC in 2015, JCET now has a production capacity almost equal to SPIL. If this ASE / SPIL goes through, the pressure will on Amkor to make a move beyond J-devices.

OSAT sales

Click to view full screen.

TSMC offered “ no comment ” on the ASE bid offer [link]. ~ 90% of the backend packaging for TSMC’s fabless clients is decided by their customers. Although TSMC works with both ASE and SPIL, many customers report that TSMC appears to have a closer relationship to ASE who they use, for instance, to backup to their internal bumping capacity.

With their recent major move into packaging, TSMC is becoming a competitor to both ASE and SPIL and rumors have circulated that TSMC could acquire one of the OSAT assembly houses.

By the end of the week Hon Hai Precision Industry (which some of us remember as Foxcon the board stuffer) and SPIL announced a strategic alliance via a share swap to reject this ASE hostile takeover of SPIL [link].

TSMC and Huawei develop 2.5D 16nm Networking Processor Module

Despite earlier delays [see IFTLE 228, “Samsung Goings On”] TSMC, during its Q2 earnings call, announced that the chipmaker has begun volume shipment of chips based on its 16-nm FinFET manufacturing process.

One of their first 16nm development projects has been with HiSilicon, the chip design division of China’s telecommunications company Huawei. They have produced an ARM-based 32-core, 64-bit networking processor using TSMC 16nm FinFET manufacturing process. [link].

TSMC has stated that HiSilicon’s processor is the first fully functional networking processor implemented on its 16nm FinFET manufacturing process. As well as using the 16nm FF process HiSilicon used TSMCs CoWoS silicon interposer 2.5D packaging technology to combine the 16nm logic chips with a 28nm logic chips.

The 32-core ARM Cortex-A57 processor is aimed at wireless communications and routers and achieves a clock frequency of 2.6-GHz for next-generation base stations, routers and other networking equipment. 

TSMC to cease solar manufacturing

Through the last decade TSMC has wisely expanded into packaging, MEMS and LEDs so it was to be expected that they would also try their hand at solar. Well that experiment looks like it is over. TSMC has announced that TSMC Solar, its 100%-owned subsidiary, will cease manufacturing operations at the end of August 2015 as TSMC believes that its solar business is no longer economically viable [link].

TSMC has come to the conclusion that despite what it considers as its world-class conversion efficiency for its CIGS [Copper indium gallium (di)selenide ] technology, TSMC Solar will not be viable even with the most aggressive cost reduction plan.

“Despite six years of hard work we have not found a way to make a sustainable profit,” said Steve Tso, chairman of TSMC Solar and senior VP of TSMC.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…


By Dr. Phil Garrou, Contributing Editor

A few years ago in IFTLE 62, we laughed when EE Times reporters got confused and unknowingly compared 3DIC to 3D finfets thinking they were the same thing. Well, things have now gotten even more confusing as the key NAND memory manufacturers have announced commercialization of vertical – NAND memory products which some are calling 3D NAND.

3D technologies

We have noted before that 3D ICs can be categorized as either (A) 3D Stacked ICs (3DIC), which refers to stacking and bonding thinned IC chips using TSV interconnects, or (2) monolithic 3D ICs [see IFTLE 177, Monolithic 3DIC….] which use sequential fab processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy which result in direct vertical interconnects between device layers. V-NAND is an example of the monolithic approach.

Toshiba TSV stacked NAND

Last week, in IFTLE 250, we noted that Toshiba had just announced the world’s first NAND flash memory packages, which stack eight or 16 dies of NAND flash memory devices and feature 128GB or 256GB capacities. Toshiba’s new stacked NAND flash packages integrate (16) 128Gb NAND memory devices connected together using through silicon vias. The multi-layer chips by Toshiba feature 1Gb/s data rate, 1.8V core voltage and 1.2V I/O voltage. The new packages use 50 percent less energy on write operations, read operations, and I/O data transfers than Toshiba’s current products.

The NAND flash memory chips are designed for low latency, high bandwidth and high IOPS/watt flash storage applications, including high-end enterprise SSD. For example, (64) 256GB multi-layer chips would provide 16TB of NAND flash storage, but in order to build such a drive a special controller and other peripherals would be needed.

Toshiba did not say if or when it plans to release its new TSV-based NAND flash memory devices commercially.

PMC Sierra had a working SSD demo at the 2015 Flash Memory Summitt which used the new Toshiba TSV stacked memory (see below). [link] They report that the upfront costs are minimal ( prices for these TSV stacked NAND chips have not been released publically) compared to the long term costs due to power consumption differences. PMC Sierra demonstrated a significantly higher power efficiency for the TSV flash vs standard non-TSV flash for high end enterprise storage. Such power efficiency would also positively impact consumer notebook battery life.

PMC Sierra SSD

PMC Sierra SSD


Vertical NAND memory devices, V-NAND, which some like Intel are calling 3D NAND, are fabricated sequentially and are connected on the cellular level as they layers are built.

Samsung has been working on V-NAND the longest (over a decade) announcing V-NAND based SSD, for use in enterprise servers and data centers, in 2013 and commercializing a 1 TB SSD last summer. Soon after Toshiba, SK Hynix and the Micron / Intel JV IMFT also announced V-NAND roadmaps.

From what has been publically reported, IMFT and Hynix have chosen to stack the current floating gate cell architecture ( the architecture for the vast majority of current 2D NAND) while Samsung and Toshiba have each chosen completely new vertical architectures for their V-NAND technologies. For those with interest, a comparison of these architectures has been published by NCTU Taiwan [link]

So, it looks like NAND can be manufactured both by TSV based 3DIC stacking and by 3D monolithic fabrication.

Are the advantages of TSV based NAND significant enough to compete with monolithic V-NAND which is being commercialized by all the key NAND suppliers ?

What applications would TSV stacked NAND be superior in?

Will Toshiba really commercialize two competing memory stack technologies at the same time?

As these answers become apparent, we will let you know.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE…

IFTLE 250 Toshiba Extends TSV Stacks to NAND; UMC to Supply TSV Based Silicon Interposers; Nvidia’s Pascal Coming in 2016 with HBM2

By Dr. Phil Garrou, Contributing Editor

Wow, the big 250!

Thanks to all of you that continue to read my updates and opinions. Thanks to all of those who have supplied me information to pass on to all of you.

I have told many of you that these blogs are my way of keeping myself up to date. I’ll keep doing these as long as I’m still having fun and as long as Extension Media and Pete Singer want me, too.

Before we get to some major 3DIC news, long time readers know I never miss a chance to update you on how my granddaughters are doing. Hannah (11) and Madeline (7) were in NC visiting a few weeks ago, so I will share this shot with you.



and now the news…

Toshiba Extends TSV Memory Stacking to NAND

IFTLE (Insights From the Leading Edge) which started in August of 2007 as Perspectives From the Leading Edge in the now defunct Semiconductor International has mainly focused on advanced packaging with emphasis on 3DIC since that was the hot and coming technology. By blog #12, I announced that Toshiba had would be commercializing CMOS mage Sensors with TSV (albeit one layer devices, but most would conclude, like I do, that this was the commercial start of what we now call 3DIC.

It is therefore somehow fitting that as I hit IFTLE 250 (and IFTLE + PFTLE 378 ) that Toshiba would be the first to announce the extension of TSV technology to NAND. [link] For years, I have been taking the position that NAND could not come till DRAM was commercialized since it is a less costly product. Well, since TSV DRAM has now been announced in many forms by the major DRAM players (Samsung, Hynix and Micron) I guess its now time for the NAND announcement.

Toshiba’s TSV technology achieves an I/O data rate of over 1Gbps which is higher than any other NAND flash memories with a low voltage supply (1.8V to the core circuits and 1.2V to the I/O circuits) and approximately 50% power reduction of write operations, read operations, and I/O data transfers.

They see this stacked NAND flash memory providing the ideal solution for low latency, high bandwidth solutions in flash storage applications, including high-end enterprise SSD.



Sold as 152 pin BGAs, the 8 stack modules are 14 x 18 1.35mm and the 16 stack devices are 14 x 18 x 1.90mm. 

UMC Enters HVM on SI Interposers for AMD FIJI

We announced the AMD FII graphics processor would use high bandwidth memory and silicon interposers in IFTLE 240 “AMD Introduces HBM on Fiji R9 390X GPU.”

WBM on interposer


It has recently been announced that the silicon interposers are being supplied by UMC making them the second entrant into the commercial silicon interposer business (after TSMC and their CoWoS process). The interposers are reportedly being manufactured by UMC in Singapore, at 300mm Fab 12i.

FIJI graphics module

AMD FIJI graphics module with 4 stacks of HBM

The GPU package, measuring 50 x 50 mm, will actually reduce the graphics card PCB size, because the memory has been moved to the GPU package, with four 1024-bit HBM1 stacks surrounding the GPU die (n the package see below). 1GB of HBM memory takes up 95 percent less than the same amount of GDDR5 memory, so you free up a lot of room on a circuit board. AMD has yet to announced whether their next gen Greeenland GPUs, which will use HBM2 memory stacks will be made on TSMC’s 16nm or Samsung’s 14nm process.

SK Hynix ships their HBM stacked to UMC who integrates the HBM stacks and GPU onto their silicon interposer for AMD.

Nvidia Pascal Coming in 2016

Not to be outdone by AMD, Nvidia has announced further details on the their Pascal graphics processor due out in 2016.

Nvidia roadmap

Nvidia’s Pascal GPU ( GP100) will feature a 4096 bit bus and four HBM2 stacks each up to 8 memory layers. The Pascal chip set will reportedly be manufactured on both TSMC’s 16nm FinFET process [link 1] and Samsungs 14nm FinFET process [link 2] later next year. Rumors are that Nvidia has taped out the GP100 at TSMC and thus should be expecting the first chips from them in Q2 2016. The GPU will be made with either 4 or 8 memory layers in the HBM stacks. They believe the Pascal GPU will be able to achieve 10x better performance compared to Maxwell.

Nvidia Pascal GPU Module

Nvidia Pascal GPU Module

OK, Intel, your turn…we’re waiting !

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 249 Merger Mania or Simple Economics? ; Wide Band Gap Semiconductors and Advanced Cooling

Merger Mania or Economics 101?

SST has recently shared an article by IC Insights entitled “Tsunami of M&A deals underway in the semiconductor industry in 2015.” [link]

While IFTLE certainly agrees with their conclusion, that mergers are occurring on a larger scale and more rapidly than in the recent past, we do not agree with their characterization “…It would be hard to characterize the huge wave of semiconductor mergers and acquisitions occurring in 2015 as anything but M&A mania, or even madness.”

As IFTLE has been preaching for some time now Economics 101 tells us that this is the natural evolution of any industry. As was explained in IFTLE 241 “Simply Obeying the Laws of Economics” [link] all industries go through cycles or stages as they mature and most of our industry is now in late stage 3 or early stage 4. IBM saw what was going on, assessed their position and got out.

A major part of these later stages is consolidation (or M&A deals). Our industry has always gone through boom or bust cycles, the difference this time is we are further along the industry maturity pathway. Actually economics also tells us that as this massive consolidation occurs those that remain will actually see less of the boom-or-bust cycles because the industry as it matures will stabilize. Those that understand this understand that we are getting ever closer to the “acquire or be acquired” phase in the electronics business and they are making their moves. Those that don’t….well they won’t be around to much longer. Still confused? Try:



That said, IFTLE certainly agrees with the closing statement of the IC Insights article “…the increasing number of mergers and acquisitions, leading to fewer major IC manufacturers and suppliers, is one of major changes in the supply base that illustrates the maturing of the industry… The strong movement to the fab-lite business model, and the declining capex as a percent of sales ratio, all promise to dramatically reshape the semiconductor industry landscape over the next five years.”

Wide Band Gap Semiconductors Require Advanced Cooling Solutions

While much of our industry is maturing (as discussed above) new segments are always evolving. Wide bandgap semiconductors is such a new semiconductor segment.

Wide bandgap (WBG) semiconductor materials allow power electronic components to be smaller, faster, more reliable, and more efficient than their silicon based counterparts. These capabilities make it possible to reduce weight, volume, and life-cycle costs in a wide range of power applications. WBG semiconductors have great potential as enabling materials in high-density power applications, satellite communications, and high-frequency and high-power radar making them the darlings of the defense industry.

high bandgap

WBG materials have the potential to:

Reduce energy losses: Eliminate up to 90% of the power losses that currently occur during AC-to-DC and DC-to-AC conversion.

Higher-voltage operation: Handle voltages more than 10X higher than Si based devices, greatly enhancing performance in high-power applications.

Higher-temperature operation: Operate at temperatures over 300°C (twice the max temp of Si-based devices).

Higher frequency operation: Operates at frequencies at least 10 times higher than Si-based devices, making possible new applications, such as radio frequency (RF) amplifiers. [link]

WBG Thermal Challenge being addressed by DARPA

While WBG materials are rapidly gaining acceptance in numerous applications, one of the challenges that remains to be addressed to fully exploit the promise of WBG semiconductors is thermal management . Alternative cooling solutions will be required to withstand the high temperatures of WBG devices.

bar cohenDARPA has been addressing this issue since 2013 under their MTO ICECool program headed up by Dr. Avram Bar-Cohen. Bar-Cohen, recently recognized by IEEE with the IEEE CPMT field award (the highest level packaging award available in the IEEE) is regarded as one of the world experts in thermal management issues.

The ICECool program has many of the countries key aerospace companies such as BAE, Boeing, HRL, Lockheed Martin, Northrup Grumman and Raytheon, developing solutions for this WBG thermal problem.

The key vs previous thermal solutions (see figure below) is to remove heat at the chip as close to the transistor heat generation as possible.


Click to view full size.

Although I cannot share the specifics with you here (ITARS restrictions), I can say that significant advances are being made in several of the ICECool programs that should allow WBG semiconductors to make major impact on our microelectronics future.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 248 ECTC 4 Oxidation of EMC in Thin Packages; Compression Molding Large Panels; TSV Noise Coupling in 3DIC

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 ECTC.

Freescale – High Temperature Storage of Ultra-Thin Molded Array Packages

Ultra-thin molded array packages (TMAP) with package thickness ≤ 500 μm are desirable for applications where system integration space is limited. Such ultra-thin packages require careful selection of the epoxy molding compound (EMC) to control package level warpage.

In this presentation, the ultra-thin package (8 mm x 8mm) had an EMC thickness of 0.250mm, substrate thickness of 0.1mm. This package was found to exhibit tensile warpage of 160μm after 175°C, 500 hrs of high temp storage (HTS).

The primary mechanism for this warpage behavior was found to be thermal oxidation of the EMC in HTS. These conditions caused thermo-oxidative crosslinking leading to densification and shrinkage of the EMC inducing stresses leading to package warpage. Oxidation also changed the CTE and elastic modulus of the EMC making it more brittle and stiffer.

Cross-sectioned samples showed that the packages subjected to 175 °C, 500 hrs had a “dark brown” appearance closer to the package edges and progressing towards the die region (see below). This was not seen for the T0 samples. This dark brown area is due to EMC that has been oxidized under the high temperature exposure. Oxidation is proportional to time, temp and exposed surface area. Thus thinner packages show more of an impact of the same time/temp oxidation conditions than thicker packages since a higher % of the overall material present would be oxidized.

This shrinkage of the outer layer of EMC causes stress on the package which generates increased warpage of the package.

oxidized EMC

Fraunhoffer IZM & TU Berin – Compression molding for Large Area Panel Processing

The group at Fraunhoffer IZM and Tech Univ Berlin have studied large area (18 x 24”) compression molding of panalized packages. The large panel size was selected to achieve process compatibility with cost efficient PCB processes. They examined the so-called “mold first” process which starts with die assembly on an intermediate carrier followed by overmolding and debonding of the molded wafer/panel from the carrier. The redistribution layer based on e.g. thin film or PCB technology is finally applied on the reconfigured molded wafer/panel.

Using an ASM Siplace CA3 5680 chips were placed on the panel with an assembly speed of around 6500 chips/hr. An 8×8 mm, 2-chip package consisting of two 2×3 mm chips the test vehicle.

They used a APIC Yamada molding tool with a cavity size 24”x18” and thickness range from 100 – 5000μm. The fig below shows the principle of compression molding with mold cavity in the upper tooling and the reconfigured wafer in the lower tooling with liquid encapsulant.

comp mold

EMC Materials can be can be either liquid, granular or sheet compounds. Mold embedding materials should have low chemical shrinkage, low cure temperature and match thermo-mechanical properties for low warpage of the molded panel and low die shift after molding.

Both the liquid and granular material underwent a significant change in mechanical properties after post mold curing (PMC) since the curing reaction is NOT complete after leaving the molding machine. Their data indicates that heating and cooling the molded panel before PMC and carrier release should be avoided due to CTE mismatch and the related length changes between silicon dies, carrier material and moldings compounds. Such induced stresses causes a high risk for cracks in the molded panel especially when it is not fully cured.

They report that the most important requirement on the mold embedding process on large panels is the positional accuracy of the embedded dies after mold and cure.

IMEC – Noise Coupling between TSV and Active Devices

IMEC notes that TSVs can introduce noise coupling arising from electrical coupling between TSVs and the active devices. They investigated the TSV noise coupling to FinFETs and planar transistors up to 40 GHz.

By analyzing and comparing the impact of TSV noise on FinFET and planar device performance, the dominant coupling mechanisms were identified. For planar nMOSFETs, noise amplification through the bulk transconductance dominates for the ON state, leading to large noise coupling. For FinFETs the main coupling mechanism was capacitive even in the ON state. They conclude that nFinFETs have better noise coupling immunity than planar nNMOSFETs, i.e. TSV noise coupling to FinFET device is 20dB smaller than planar device at 1GHz and 4-8dB smaller at 40 GHz. They explain that the main reason for improved FinFET noise immunity is that the FinFETs are less sensitive to substrate bias due to the stronger gate control w.r.t. planar MOSFETs.

They have also investigated four different TSV architectures to predict their impacts on the noise coupling: 5um/50um via-middle TSVs with 200nm oxide liner; scaled 3um/50um via-middle TSVs with 200nm oxide liner; 5um/50um via-middle TSVs with 400nm oxide liner; and via-last TSV architecture with thick (3um) polymer liner (“Donut” TSV).

They conclude that scaling the TSV diameter, using thicker liner materials, and polymer based liner materials with smaller dielectric constant all reduce the coupling level mainly at low frequencies where TSV liner capacitance is the dominant factor on noise coupling. At 100 MHz, for the 3/50 um and “Donut” TSVs, the noise coupling reduces by about 4dB and 20dB respectively.

They conclude that In order to extract the KOZ accurately, coupling induced current variations must be considered together with the stress induced current change. Stress induced current change decreases rapidly with increasing distance; i.e. when the active device is 20 um away from TSV, the stress induced current change is close to zero for both planar and FinFET devices.

However the coupling induced current change decreases with distance much slower, which means the noise coupling can have significant influence on the KOZ. When an active device is located at 10um away from TSV, the current change induced by TSV stress is only 0.2% for FinFET device and 0.6% for a planar device, but these values increase to 2.23% and 3.55% when the impact from TSV noise coupling is added up at 10 GHz (2.03% for FinFET device and 2.95% for planar device). They conclude that it is important to use noise mitigation techniques such as “substrate contact and guarding” to reduce the electromagnetic coupling effects in order to minimize the KOZ.

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IFTLE 247 ECTC part 3: More Thermo Compression Bonding from Intel and ASM

By Dr. Phil Garrou, Contributing Editor

In IFTLE 245, we looked at some of the key thermo-compression bonding (TCB) papers at ECTC. Is there any question that TCB is real and will be the next big bonding technology ? This week, more coverage on this very important new assembly process from Intel and ASM.

Intel & ASM – TCB for fine pitch Flip chip (C2)

Intel introduced TCB into high volume manufacturing in 2014. As substrate and die become thinner and solder bump sizes and pitches get smaller, the thin organic substrate tends to warp at room temp and as the temp is increased during the reflow process. The thin die can also demonstrate temperature dependent warpage, which can come into play during the reflow process. The extent of warpage of the substrate and die at high temperatures can overcome the natural solder surface tension force leading to die misalignment with respect to the substrate, resulting in tilt, non-contact opens (NCO) and in some cases solder ball bridging (SBB). The figure below shows shows these various defects.

C2 defects

In the Intel TCB process, the substrate with pre-applied flux is held flat on the hot pedestal under vacuum. The die is picked up by the bond head, held securely and flat on the bond head with vacuum. After the die is aligned with the substrate, the bond head comes down and stops when the die touches the substrate. A constant force is then applied while the die is heated up quickly beyond the solidus temperature. As soon as the solder joint melts, the die is moved further down (solder chase) to ensure all solder joints are in contact. The die is held in position allowing the solder to reflow completely, and to wet the bump pads and copper pillars. While the solder is still in the molten state, the bond head retracts upwards controlling the solder joint height. The bond head then releases the vacuum holding the die and moves away as the solder joints have solidified. The major process parameters, i.e temperature, force and displacement are continuously monitored during the TCB bonding process.

A schematic of the bonding tool is shown below.


Large differences in the CTE between the organic substrate and die results in different magnitude of expansions when heated which can lead to serious bump offset at corners. To minimize the thermal expansion mismatch, the substrate is processed at a lower temperature (e.g. 140ºC) while the die and solder is rapidly heated up for reflow and cooled down for solidification using a pulse heater with heating ramp rate exceeding 100ºC/s and cooling ramp rate exceeding 50C/s. This reduces the heat transfer to the substrate. The bulk of the substrate can remain at low temperature and does not expand extensively.

ASM – High Throughput Thermal Compression Bonding

In another ASM paper on TCB, they examined what they call liquid phase contact (LPC) TCB. The goal is to increase the throughput of the TCB process. Process flow is shown below. Flux is printed or sprayed on the substrate. Then the bonding head picks up a die from the carrier at an elevated temperature, but below the solder melting point. Hen the bonding head is heated up to a temperature higher than the solder melting point and the chip is aligned with the substrate. The chip is then contacted and wetted on the substrate at a predetermined bonding height. After a predetermined bonding time, the bonding head can move is cooled down to a temperature below the melting point of solder.



They claim this results in attachment of 1200 units/hr vs 600 for the std. TCB flux process.

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IFTLE 246 ECTC 2: IMEC 2.5/3D Process Developments and Low Temp Bonding for Si on Diamond

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 ECTC:

Kaiung Paik – KAIST and Jay Im – U Texas

Kaiung Paik – KAIST and Jay Im – U Texas



Nancy Stoffel – GE, Chris Bower & Carl Heinz Bock –                                                                                        Emerging Tech Committee Chairs & Marsha Tickman -                                                                                       Exec Dir CPMT

Nancy Stoffel – GE, Chris Bower & Carl Heinz Bock –
Emerging Tech Committee Chairs & Marsha Tickman –
Exec Dir CPMT

Stress & Bowing in Passive Silicon Interposers – IMEC

Three modifications of the structure of a 4 BEOL layers with 10×100μm TSV Si interposer are proposed to mitigate the tensile stress and release the interposer warpage. The use of a thicker and more compressive PMD layer enable a wafer bowing reduction of 75% after TSV processing. By reducing the thickness of Metal1 (ground plane with 75% Cu density) from 1000 nm to 300 nm, the single contribution of the Metal1 module to wafer bowing was reduced by 37%. Finally, by using a more compressive oxide (from -170 MPa to -230 MPa) to process the Via2/Metal3/Via3/Metal4 layers (total of 8μm thickness), their contribution can change from tensile to compressive, inducing a total reduction of -120%. In total, a global bowing reduction after full front side processing of 75% was measured compared to the initial interposer structure.



Effects of Packaging on Mechanical Stresses in 3DIC – IMEC

IMEC has studied the mechanical stress induced in 3D stacks by different packaging process steps. The 3D stacks used in this work are assembled using two identical dies containing a number of stress sensors which are designed and manufactured in 65nm technology. It is observed that the contribution of the package substrate and the die-attach process to the redistribution of mechanical stress inside the 3D stacked IC is more significant than the one of the EMC and that the influence of packaging on the shape and amplitude of local stress around the micro-bumps is not significant. These observations are supported by the measurements of stress done using micro-Raman spectroscopy and are correlated with the results of finite element modeling and with optical warpage measurements of different packaging configurations.

Advanced Metallization Scheme for 3 x 50 um TSV Middle Process – IMEC

Scaling down the TSV diameter from 5μm to 3μm is very attractive for the 3D IC implementation in more advanced CMOS nodes. For instance, stress caused by the mismatch between the coefficient of thermal extension (CTE) of Si and Cu may generate strain in the Si around the TSV, degrading the device performance of transistors located close to a TSV. To reduce the impact on transistors, a so called keep-out-zone (KOZ), is generally defined around the 3D TSVs. This keepout-zone is however significantly smaller when scaling down the TSV diameter from 5μm to 3μm. When increasing the aspect ratio of the TSV from 10:1 to 17:1 (for 3μm diameter and 50μm depth), the conventional PVD barrier and seed options reach their conformality limits. Very thick barrier/seed layers need to be deposited in order to assure a continuous film at the bottom of the TSV. This not only fundamentally limits the extendibility of this integration scheme, but also increases the PVD deposition cost itself and the required CMP time, among other technical challenges. For these reasons, a new advanced and scalable TSV metallization scheme was developed.

Atomic layer deposition (ALD) has emerged as a key enabling technology for conformal film applications such as TSV oxide liner. Typical step coverage or conformality of other CVD oxide films is only 60-75% for high aspect ratio TSVs . In contrast, the VECTOR ALD oxide film shows 100% conformality.

ALD WN serves as a barrier layer and is deposited on the Altus Max tool. It is highly conformal with >90% step coverage regardless of geometry. ALD WN is deposited at 375°C and has excellent adhesion to ALD oxide and subsequent ELD NiB. The conformality of the ALD process results in a pinhole-free WN layer, as opposed to barriers deposited by PVD, which potentially struggle with pinholes at the bottom of high aspect ratio TSV.

NiB electroless deposition on WN barrier was carried out on a Lam ELD2300 tool using a plating chemistry developed at Lam. The entire deposition process was made of several sequential steps such as a brief pre-clean, activation, deposition, rinse and dry. The concentration of reducing agent and nickel ions as well as the pH and temperature are controlled to maintain optimum deposition condition for seed formation during the NiB deposition. After deposition of ELD NiB, TSV copper electrofill is processed on a Lam SABRE 3D electroplating system using an industry standard acid copper sulfate electrolyte with a Lam

exclusive organic additive package. The conductivity and corrosion resistance of the Lam ELD NiB film enable compatibility with the electrofill process on 300mm wafer scale. Bottom-up fill of the vias proceeds without the need for the additional copper seed film that has been used with other conformal metal liners (e.g. Co or Ru).

Because of the high conformality of liner, barrier and seed layers, this proposed Via-middle metallization scheme is believed to be scalable to even higher aspect ratio TSVs with 2μm diameter.

Silicon on Diamond by Low Temp Bonding – Kyushu Institute of Technology

Diamond has long been known as an excellent thermal material, but has been a hard material to process. Researchers at Kyushu Univ had recently developed a low temp diamond bonding technique. The process flow is shown in the figure below. The SOD fabrication process includes: (a) Fabrication of thermally grown SiO2 film on Si wafer as a bonding substrate. (b) Deposition nanocrystal diamond film on Si wafer as another bonding substrate. (c) Removal of big nanocrystal diamond particles. (d) Deposition of SiO2 film on the nanocrystal diamond film by CVD. (e) CMP of the SiO2 film. (f) Thinning of the CMP SiO2 film by 2.5% HF solution. (g) Surface chemical cleaning of the bonding substrates by piranha solution. (h) Surface activation by O2 plasma. (i) Bonding of the substrates.

Si on Diamond


The middle figure shows (a) the morphology of 300nm-thick of nanocrystal diamond on the wafer 525nm-thick wafer. The surface roughness of nanocrystal diamond was characterized by AFM which was 13.9nm rms approximately. Generally, the roughness of thin film from the CVD process is dependent on the substrate. Thus a surface roughness of SiO2 that we plan to deposit in the next step is probably close to 13.9nm rms.

In addition, the big nanocrystal diamond particle may be an obstruction to the thinning SiO2 before bonding. Therefore, we remove the big particles using CMP equipment before deposition of SiO2 film on it. Fig. (b) shows the morphology of CVD-SiO2 500nm thick deposited on substrate after remove big particle already. The roughness was reduced to 8.1nm rms compared with the substrate. Fig (c) shows the morphology of CVD-SiO2 after polishing by CMP. The roughness was reduced to 0.50nm rms.

An average CVD-SiO2 roughness of > 1 nm rms failed to bond, the bonding results show 95% confidence level for bonding with a roughness is 0.97±0.03nm rms.

The figure on the right shows the cross section of the stack shows the dimensions of the overall structure.

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