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IFTLE 360 IMAPS 2017 – 50 Years and Counting

By Dr. Phil Garrou, Contributing Editor

IMAPS 50th

IMAPS (the Int Microelectronics Assembly and Packaging Society) 2017 was held this year near their Research Triangle Park headquarters, in Raleigh, NC, certainly a convenient location for IFTLE. Having started operations in 1967 as ISHM (Int Society for Hybrid Microelectronics), they changed their name and focus during my Presidential year of 1998 to IMAPS. This is the 50th year of existence for this nonprofit society. I emphasize the term nonprofit intentionally. This is important to me since the conferences we all attend request we give our free time to serve as presenters or session chairs or organizers and I want to be sure that the profits from such enterprises are going to a nonprofit and not into someone’s personal bank account, as is the case for so many of these conferences you and I attend. Basically, I don’t work for free unless it is a non profit, only seems right to me, so conferences that I give my limited time to, tend to be organized by IEEE and IMAPS.

My first IMAPS conference was in 1985 as my professional focus in Dow Chemical shifted from R&D on organometallic catalysts to the electronics industry. I was 35 but only a rookie in the electronics industry with lots to learn. This was the first electronics conference of my career (which I then followed up with the ECTC conference in the spring of 1986) and as importantly, it introduced me to many of the contacts and long term friends that I was able to develop in this industry through the years.

Fig 1

I recently took a look at the Proceedings (which I still have in my professional library) and during this trip down memory lane thought you might be interested in what was considered groundbreaking 32 years ago.

In the mid 1980s the industry was just getting comfortable with surface mount components and Harry Charles of Johns Hopkins was talking about “Design Optimization and Reliability Testing of Surface Mount Solder Joints”.

In the computer aided design session authors from Tektronix were sharing their thoughts on “Just-in-time Manufacturing – An essential technique for Process Control”.

In the Polymer Applications session, Englehard (that’s right Englehard the precious metals company) was showing us how to spin coat polyimide in their paper “Multi-layering with PI dielectric and metallo-organic conductors.” This paper had a significant influence on my personal career since, working for Dow Chemical at the time, I went back home wondering whether I could find a Dow polymer material that could be used for similar thin film polymer IC applications. This eventually led me to the discovery (it existed in the bowels of Dow R&D without a clear application need) and commercialization of BCB dielectric which by the mid 190s led to the commercialization of low cost bumping and WLP at FCT and Unitive and subsequently all the key bumping houses in Taiwan as they licensed the technology. By the early 2000s, BCB was being used in components put into nearly every cell phone being manufactured in the world!

The interconnect technologies session contained the paper “Recent advances in Die Attach Adhesives for Microelectronics” given by epoxy legend Dick Estes from Epoxy Tech. At the time polymeric die attach were not allowed in high rel military applications. He described the issues of thermal stability, outgassing and most importantly halide contamination of devices.

Kohji Nihei of Oki , later to become infamous as the photographer of the generation that proceeded me, gave the first paper I had ever seen describing the use of “LEDs for the electrographic, non impact printing of text and images” entitled “Development of High Quality LED Print Head” (shown below) Think that’s a technology with a commercial future?

Fig 2

For those of you that don’t remember Kohji, you should, both as a wonderful person and a technologist. Below he is shown a few years later in Japan with the American contingent at an IEEE VLSI workshop.

(l-r) Kohji Nihei (Oki), Len Schaper (AT&T, Alcoa, U. Arkansas), Garrou, Jan Vardaman (TechSearch), George Harman (NIST “Mr. Wirebonding”)

(l-r) Kohji Nihei (Oki), Len Schaper (AT&T, Alcoa, U. Arkansas), Garrou, Jan Vardaman (TechSearch), George Harman (NIST “Mr. Wirebonding”)

That’s enough of the past. Next week, we will begin our look at the 2017 IMAPS Conference content, I promise.

For all the latest on advanced packaging and nostalgia, stay linked to IFTLE…

IFTLE 359 ARM on IoT; SEMICON Taiwan Part 4

By Dr. Phil Garrou, Contributing Editor

Will IoT require “dirt cheap” packaging?

Those of you following IFTLE’s position on IoT know that while I certainly see a future where the wireless collection of data proliferates, I see this, in general, for extreme low cost packaging solutions, certainly not, as some have said in the past, an IoT using 2.5/3D solutions.

In seeming agreement with that conclusion, Rick Merritt of EE Times describing the recent ARMTechCon reports that the panel discussion on “Breakthrough Technologies enabling the future of IoT” concluded that the future of IOT could depend on a chip that sells for less than 50 cents, that SoCs will need new kinds of memories, connectivity and sensors to scale to dimensions the IoT will demand, and that the path to get there is still unclear. [link]

He reports that SRAM and flash memories, Bluetooth interfaces and sensors consume too much power to serve volume IoT nodes in 2027 where ideally, ARM reports, an end node SoC would consume just 10 microwatts/MHz and send and transmit data on a radio drawing only 1 or 2 mW. In terms of transmission, radios need to ultimately scale to power levels of a tenth the power of today’s Bluetooth Low Energy which perhaps will require a new radio maybe on new frequency bands which might take a 10-year effort to execute. Sensors will also need to explore new materials and design techniques to lower power, shrink size and add features. Sensors will need heterogeneous integration packaging technologies to integrate them into modules. “ … so the package becomes the sensor with silicon inside it”. Bottom line seems to be, as we have stated before, that the packaging solutions for IoT will have to be “dirt cheap”

SEMICON Taiwan continued…

Brewer Science

In his presentation on “New Materials for Fan-out WLP,” Tony Flaim of Brewer proposed an interesting new fan out concept where cavities are laser drilled into a laminated sheet, chips are inserted face up into the cavities and thin film RDL is created over the chips as shown below.

Brewer 1

 

SavanSys

IFTLE is not a big fan of making technology decisions based on cost modeling. My past experience has shown that he cost models that I have used are generally very accurate when all the inputs are well known and not very accurate when the inputs are being “guestimated”. Having said that, I do like the slide presented by Chet Palesko of SavanSys Solutions on the general comparison of embedded die vs FOWLP vs TSV solutions shown below…

Savansys 1

ITRI

ITRI always gives us a nice update on activities in Taiwan. Below we see that Taiwan foundry services currently account for 70% of the world wide market and the Taiwanese IC packaging and test services account for 55% of the world wide SATS market.

ITRI 1

Global Foundries

Dave McCann of GF showed a nice process flow for their 2.5D production where the interposer fab, logic fab, memory fab and OSATS must work together to deliver the finished product.

iftle

Next week, we will begin our look at IMAPS 2017. For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 358 SEMICON Taiwan Part 3: ASE & Powertech Fan Out Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at 2017 SEMICON Taiwan.

ASE

John Hunt of ASE discussed his thoughts on “Fan Out Packaging – Simple to Complex”.

An interesting slide was his chronology of wafer Level (WL) packaging sine the adoption of bumping and RDL (the advent of Taiwan licensing the FCT technologies).

ASE 1-2

Hunt divides fan out (FO) categories into low density and high density options:

  • Low Density fan out

– Less than 500-600 I/O

– L/S > 8µm

  • High Density fan out

– Greater than 500-600 I/O

– L/S < 8µm

Early applications for low density FO include baseband and Rf transceivers. New opportunities include:

ASE 2

Early high density fan out opportunities include PoP and SiP

New Opportunities include:

– APU + memory

– GPU + memory

– Network applications

– SiP/Modules

Note the GPU and Network apps begin to intrude into the space carved out by Silicon 2.5D. Such a product is described below:

ASE 3

Hunt showed the following ASE fan out package platform:

ASE 4

Powertech

David Fang, CTO of Powertech discussed PTI panel level processing developments.

– Packaging for more than Moore modules is usually larger than 10x10mm and thus panel level processing provides 3-5X the efficiency of wafer level even at 300mm.

– They have found that the initial investment per module is 30-40% higher for panel level fan out modules than for fan in WLP.

Continuing challenges for panel processing include:

– No worldwide standards

– Tool and accessory readiness

– Process difficulties, i.e. panel warpage, chip shift, fine line patterning

An interesting slide details their thoughts on panel equipment selection based on technology from the Wafer, LCD and PWB industries.

powertech 1

Powertech fan out solutions are shown below.

powertech 2

For all the latest on Advanced packaging, stay linked to IFTLE…

IFTLE 357 SEMICON Taiwan Part 2: Laser Processing

By Dr. Phil Garrou, Contributing Editor

Continuing our look at SEMICON Taiwan 2017, we’ll look at some of the papers dealing with laser processing for advanced packaging.

Suss

Habib Hichri examined the reliability of ultra fine line redistribution. Redistribution, developed in the 1990s to facilitate bumping or chips designed for peripheral interconnect, is now indispensable for WLCSP, fan out WLP and Embedded IC packaging.

The claim he best process is a dual damascene process flow creating the trenches and vias by laser ablation as shown below.

Suss 1

 

  • Excimer laser ablation patterning does not require photosensitive materials

–allowing wider choice of dielectric materials

  • Ablation patterning is performed after cure
  • Significant reduction in lithography-related steps

–No photoresist application, develop or strip required

ASE

YE Yeh of ASE described their “Laser Technologies In Advanced Packaging and SiP Process” They offered the following use of lasers for their advanced packaging technologies.

ASE 1

Trumpf Lasers GmbH

Michael Lang of Trumpf Lasers discussed Laser application development for advanced packaging.

Ultra short pulse lasers enable extremely precise, cold ablation of different materials as shown below in the comparison of ns and ps lasers. Typical materials used in Advanced Packaging can be machined without heat-affected zone.

trumpf 1

 

Orbotech

Nimrod Bar-Yaakov of Orbotech discussed laser via formation for Advanced Packaging.

They offered the following as key advantages of laser drilling for Advanced Packaging applications:

  • Cost and process reduction: Direct material ablation saves photo-litho processes
  • “Digital Patterning”: adjusts the drilling pattern according to the actual location of the die
  • Same tool and process suites various substrate compositions
  • Laser processing tools are panel format ready

They offered the following process flow for PoP laser ablation of TMV:

Orbotech 1

Pattern-based registration

  • Die placement and process variation can cause misalignment between fiducials and pattern
  • Using actual pads pattern as registration targets can overcome this issue

orbotech 2

They offered further visual evidence that thermal effects are reduced by using short pulsed lasers.

orbotech 3

For all the latest in advanced packaging, stay linked to IFTLE…

ITLE 356 SEMI Taiwan Part 1: Fan-out Packaging Players, Applications and Market Growth

By Dr. Phil Garrou, Contributing Editor

SEMICON Taiwan

Although threatened by Typhoon Talim, SEMICON Taiwan went forward Sept 13-15 in Taipei. Over the next few weeks IFTLE will be covering Interesting advanced packaging disclosures and topics with relevance to advanced packaging. Our thanks to Semi’s Debra Geiger, Jamie Liao and Grace Wang for linking IFTLE to the relevant materials.

CP Hung of ASE chaired the SiP forum “3D IC, 3D interconnection for AI & High-End Computing” and Albert Lan of Applied Materials chaired the forum “Innovative “Embedded Substrate” and “Fan-Out” Technology to Enable 3D-SiP Devices.”

albert Lan

Albert Lan – Applied Materials

CP Hung - ASE

CP Hung – ASE

Let’s first take a look at the embedded and fan-out forum

TechSearch

Jan Vardaman presented the following list of Fan-out WLP suppliers

TechSearch 1

TechSearch lists the following as why Apple chose this TSMC packaging format for their A10 processor

  • Improved electrical and thermal performance of InFO vs. FC-­‐CSP

– InFO PoP Power Noise Reduction and Signal Integrity Improvement

  • Thinner than flip chip package (no substrate)

– InFO-­‐PoP is 20% thinner than FC-­‐PoP

– Can enable a low-­‐profile PoP solution as large as 15x15mm

TechSearch 2

An interesting comparison of Amkor’s SWIFT vs ASE’s FOCoS vs TSMC’s InFO.

techsearch 3

Lastly, the TechSearch list of fan-out WLP evolving applications:

  • Baseband processors
  • Application processors
  • RF transceivers, switches, etc.
  • Power management integrated circuits (PMIC)
  • ConnecDvity modules
  • Radar modules (77GHz) for automotive plus other ADAS applications
  • Audio CODECs
  • Microcontrollers
  • Logic + memory for data centers and cloud servers
  • Power devices
  • Fingerprint sensors

Yole Developpement

Jérôme Azémar of Yole gave their take on “Fan-Out Packaging Technologies and Markets”.

Long time IFTLE readers know that we dislike the term fan out since all packages except fan-in WLP are fan out packages. To add to this Yole has added the following:

yole 1

Their take on applications is show below plotting package size vs IO count.

yole 2

Yole sees significant future growth initiated by the Apple adoption of the TSMC InFO package.

yole 3

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 355 iPhone 8 Teardown; NHanced Semi; Morris Chang to Retire

By Dr. Phil Garrou, Contributing Editor

iPhone 8 Teardown

TechInsights has begun their teardown of the iPhone 8. [link]

Pics of the main board are shown below.

TechInsights

 

techinsights 2-2 TechInsights 1-2

– The AP (application processor) is in a Package on Package (PoP) with Micron 3GB Mobile LPDDR4 SDRAM.

– The biggest new feature of the AP at announcement is a dedicated “Neural Engine” primarily for Face recognition.

– The video performance is claimed to be the highest quality video capture available in a smartphone. The AP features an Apple-designed video encoder enabling 4K video at 60 fps and Slo-mo 1080p video at 240 fps.

– For we packaging aficionados, the big news is the absence of TSV arrays in their CIS. Preliminary analysis of the die photo suggests to TechInsights that it’s a Sony back-illuminated Exmor RS stacked chip from which they infer that the stack is using hybrid bonding (what Sony licensed from Ziptronix) for the first time in an Apple camera. [see IFTLE “Updating CMOS Image Sensor Technology”]

The SEMI 3D Packaging and Integration Committee

The SEMI International Standards Committee, at their SEMICON West 2017 meeting, approved the transformation of the existing 3D Stacked IC Committee and Assembly & Packaging Committee into a single, unified 3D Packaging and Integration Committee [link] with a charter to:

To explore, evaluate, discuss, and create consensus-based specifications, guidelines, test methods, and practices that, through voluntary compliance, will:

  • include the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration, either single- or multi-chip configurations. It relates to the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, flexible electronics technology
  • promote mutual understanding and improved communication between users and suppliers, equipment, automation systems, devices, and services
  • enhance the manufacturing efficiency, capability and shorten time-to-market and reduce manufacturing cost

You can get involved with the SEMI International Standards Program at:  www.semi.org/standardsmembership.

Enhanced Semiconductor

NHanced Semiconductors Inc. was launched as a spin-off of Tezzaron Semiconductor in 2016. In the course of developing its advanced 3D memory devices Tezzaron developed technical expertise in ancillary semiconductor technologies.  While Tezzaron will continues to develop and manufacture memory devices with specific focus on its DiRAM4 products, Bob Patti, Bob Patti, past CTO of Tezzaron informed IFTLE that NHanced Semi exists to implement and expand that expertise for process development, prototyping, small volume manufacturing. “We will help determine the optimal packaging solution for customer needs.  If they need custom design work, we can do that; if their design is complete, we’ll assist with 3D or 2.5D enablement.  Sourcing, manufacture, assembly, test – we will handle the entire process from concept to completion”

NHanced Semi has recently completed the purchase of the former Morrisville NC Novati fab, the fab that used to be Ziptronix. Bob indicated that Nhanced will be doing customer R&D development projects and then passing them off to partner Novati to scale and commercialize. Nhanced has replaced tools that Novati had shipped from Morrisville to Austin and their full line in Morrisville should be operational shortly. The 24,000 square foot fabrication Morrisville, NC facility is equipped for rapid prototyping, with a focus on 2.5D and 3D integrated circuit assembly. Current equipment can perform surface prep, bonding, thinning, and pick-place on multiple wafer sizes (100mm to 200mm). NHanced is currently quoting and taking orders for 4Q activity

Speaking of Novati, a recent report from Austin indicates that they have been acquired by start-up Skorpios, a fabless semiconductor manufacturing company producing communications products. [link]

Morris Chang announces retirement

ChangWhen a wise man speaks it is best to listen. Certainly we must all agree that Morris Chang, the “father of Taiwans chip industry,” who has led TSMC, for 30 some years, is a wise man. Long time IFTLE readers will recall my encounter with Chang in the late 1990’s when I was visiting TSMC introducing materials for bumping. He personally attended this low level meeting telling me “I need to better understand this bumping technology…so teach me”

Well, Morris Chang, 86, has announced that he will retire in June, after having built the world’s biggest foundry chipmaker [link].

Earlier this summer, this wise man was quoted as saying “Packaging can extend physical limits of semiconductors…” [link]

Chang identified the impact of packaging on high-performance computing applications such as AI and deep learning, graphics processors, augmented reality (AR) and virtual reality (VR) applications which he feels will drive future IC market growth.

We are all aware that TSMC has developed a new generation of packaging , its integrated fan-out (InFO) wafer-level packaging (WLP) technology and has recently expanded its chip-on-wafer-on-substrate 2.5D (CoWoS) technology to the fabrication of 16nm chips, and offered second-generation High-Bandwidth Memory (HBM2) and a GPU modules to support artificial intelligence (AI), deep learning and other high-performance computing applications.

When a wise man speaks, it is best to listen!

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 354 The Case for µLED Displays

By Dr. Phil Garrou, Contributing Editor

AntmanIt is true, as Shakespeare one said, that “A Rose by any other name would smell as sweet” but … in our times, it is important to have an unambiguous name that clearly indicates what you are talking about. Unfortunately, this is not the case for micro LED displays (µLED Displays). There are those for which this term brings to mind a millennial trying to read the Wall Street Journal on his smart watch with a magnifying glass or possibly a display worn by the Astonishing Antman.

The problem obviously is the grammatical issue of what the µ modifies…i.e. a micro (LED display) or a (micro LED) display. While it may be fun to consider how to create a display for the Antman, we will be talking about the latter. IFTLE thought a primer on the subject was in order since this technology has become more and more dependent on interconnect and assembly technologies being supplied by the packaging community.

IFTLE certainly considers this a “futures” technology, meaning still a few years out, but always remember “…the leading edge is where the money is made!”

Comparing the Display Technologies

TFT LCD (thin film transistor liquid crystal displays) were being developed in the 1970s, but by the late 1980s it was publically thought to be way too difficult to yield (“.. you cannot have bad pixels on a TV set”) and certainly a much too expensive a technology to ever displace the cathode ray tubes used for TV and desktop computer displays. Well we all know what happened next and clearly without that technology transformation there would be no laptops or smartphones or smart watches today.

Next on the time line came OLED developed initially by Eastman Kodak in the late 1980s. An organic light-emitting diode (OLED) is a LED in which the emissive layer is a film of organic compound that emits light in response to an electric current. This layer is sandwiched between two electrodes (typically the upper electrode is transparent such as ITO). An OLED display works without a backlight, and is thinner and lighter than a LCD. OLEDs have traditionally been expensive to manufacture and only LG and Samsung made them. Samsung has been working in OLED devices for a decade and is currently using the technology in their smart phones and televisions. Today, the cost has come down dramatically, and now OLED TVs are very affordable. Apple began using OLED displays in its watches in 2015 and in its laptops in 2016.

The term “Micro-LED” was first used by Cree in its US patent “Micro- led arrays with enhanced light extraction” in 2001. The patent describes arrays of interconnected LEDs with individual sizes of less than 30μm.

While there currently are no µLED displays in production, the companies developing the technology believe that it has the potential to challenge OLED and LCDs in the future. Like OLED, it does not require a backlight, producing light in each individual pixel. µLED have the advantage of lower power consumption, higher brightness, ultra-high definition, high color saturation, faster response rate, longer lifetimes and higher efficiencies compared to LCDs and OLEDs.

The three technologies are compared in cross section in the figure below [link]

led 4

 

µLEDs were placed onto the industry technology roadmap 2 years ago following Apple’s acquisition of LuxVue, which claimed that its technology was 9x brighter than OLED and LCD. Then Oculus (Facebook) acquired InfiniLED another µLED company which claimed “… a 20 – 40X reduction in power consumption” [link].

In most cases, the µLED chips are manufactured separately then positioned and connected to the transistor matrix via a pick and place process show in the figure below.

LED 1

Singulation of μLED display chips is typically achieved by bonding the epi wafer to a carrier and plasma etching in the die streets. According to Yole Developpement LEDs as small as 5μm have been demonstrated, but applications requiring >1500 PPI (pixels per inch) might require even smaller sizes.

led 5

 

Traditional pick and place equipment cannot pick up such small dies. Such tools typically have throughput around 25,000 places per hour. If large displays are to incorporate millions of tiny LEDs they cannot be assembled by such a method. Thus a requirement for µLED displays is a massively parallel pick and place technology. Players who have developed such technology include Luxvue and X-Celeprint who we have discussed on IFTLE before [see IFTLE 203, “Apple Acquires LuxVue µ-assembly Technology”]

X-Celeprint has developed MEMS-like sacrificial release processes for LED chips. Luxvue uses an electrostatic technology for their massively parallel pick-up, while Xceleprint uses an elastomeric stamp.

The µLED display concept was first validated by Sony in 2012 [link]. Their 55 inch “Crystal LED TV“ which utilized 6MM tiny LEDs (2 million each for red, green, blue subpixels) to reproduce a picture in Full HD resolution. Sony claimed that it had 3.5 times the contrast ratio, 1.4X the color range, and 10X faster response time compared to a traditional LCD.

HVM at costs acceptable to the proposed applications still faces significant engineering and manufacturing challenges. Most expect to see smart watches, being worked on now, as the first application to reach commercialization in the next few years with Apple in the lead. The drivers for this application include battery life and display brightness.

µLED performance and supply chain players are compared below [link].

led 2

While it will likely take considerable time, effort and investment to establish an HVM infrastructure, µLED could emerge as an alternative to OLED in the future as LCD fades away.

For all the latest in Advanced packaging, stay linked to IFTLE…

IFTLE 353 Updating CMOS Image Sensor Technology

By Dr. Phil Garrou, Contributing Editor

A few weeks ago, we covered the Sony announcement of the Xperia XZ1, which features a 19MP Exmor RS camera with 960fps video capture and reportedly is fabricated as a stacked 3 layer CIS with DRAM. [see IFTLE 346 “Sony Introduces Stacked Image Sensor with DRAM in Xperia XZ phones]

This technology was first disclosed at IEEE IEM in 2016 as their “Cu2Cu Hybrid Bonding” [link] and discussed in IFTLE coverage of last falls 3D ASIP Conference [see IFTLE 319 “ …3D ASIP Part 2: Image Sensing – Sony, Tessera, SMIC”]

Those of us that have been following 3DIC for the past decade recognize this as the Ziptronix “DBI process” which they licensed to Sony a few years ago. It is now quite clear that the literature is generically calling this technology “hybrid bonding” since the bonding occurs to a surface containing both copper and oxide. Hybrid bonding does not have TSVs since it simultaneously connects the two substrates physically and electrically.

They depict there process flow as follows

Sony 1

The trench and via are made at the BEOL top layer of each wafer. Then, barrier metal and Cu seed are formed by PVD. Cu is plated up and annealed at the appropriate temperature. Excess Cu is removed by CMP to reveal the Cu connection pads and oxide dielectric. After face-to-face bonding, the wafer stack is annealed. As illustrated in their figure 4, the upper Cu pad and lower Cu pad are connected by Cu diffusion and grain growth, and the upper dielectric and lower dielectric are connected by dehydration-condensation reaction. They report that it is important to remove any voids from the Cu pad bonding interface during the post-ECD annealing.

Samsung CIS now include Stacked DRAM too

According to new reports [link], Samsung has developed and will begin mass production in November 2017 of a similar mobile camera sensor capable of 1,000 frames per second (FPS). Reports are that the camera contains a stacked 3 layer image sensor, with the layers made up of the sensor itself, logic chip, plus a DRAM chip that can temporarily store data.

While we are at it, let’s take a look at the advances covered at the recent Int Image Sensor Wkshp held in Hiroshima this past May.

Omnivision

Venezia of Omnivision described their “1.0um pixel improvements with hybrid bond stacking technology” discussing their Gen2, 1.0um CMOS image-sensor technology featuring hybrid bonding stacking.

Their first generation, stacked chip technology used oxide-oxide bonding and TSV to bond and electrically connect the sensor and logic wafers, respectively. “With stacking technology, the logic circuitry is placed under the array, resulting in an overall smaller chip size than is possible with standard BSI-CIS; where the circuit is located on the same wafer. Stacking also allows for sensor-only processes that improve CIS performance which could have negative impacts on circuit performance in a BSI-only process.”

The gen 2 technology uses hybrid bonding “where wafers-to-wafer bonding occurs at both the oxide and metal interfaces, and water-to-wafer interconnection is made at the top metal bonding pad. This architecture offers a better interconnect pitch and more flexible interconnect placement than the previous Gen1 approach. For instance, bonding can occur closer to the array edge, or even within the array.” The resulting chip size is 10% smaller using HB technology for the Gen2 1.0um, 16MP product.

fig 2

 

TSMC

Hseih of TSMC gave a joint paper with Qualcomm on “A 3D Stacked Programmable Image Processing Engine in a 40nm Logic Process with a Detector Array in a 45nm CMOS Image Sensor Technologies”

They designed & fabricated a RICA (Reconfigurable Instruction Cell Array) ASIC wafer stacked with a pixel arrays wafer of 8MP, 1.1 um pitch BSI image sensor test vehicle. This device used “the 3D stacking technologies of a 45nm CIS process and a 40nm logic process at TSMC”.

Sony

Kagawa of Sony discussed “Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding” further detailing their Cu2Cu hybrid bonding technology.

They describe the positive attribute of not having to create TSVs in their devices as follows “Making TSVs needs special fabrication equipment, such as deep Si etcher and high coverage metal/dielectric deposition tool. In addition to the fabrication problems, there are device problems. In particular,

the keep-out-zone (KOZ) strongly affects device specifications and circuit design. On the other hand, hybrid bonding does not have such problems. It can basically be fabricated by the conventional back-end-of-line (BEOL) process, and special equipment is never needed….Moreover, the Cu connection pad is located on top of the BEOL layer, and it never interferes with the MOS-FET during the fabrication process. It enables enormous circuit design flexibility and further chip size reduction can easily be achieved.”

Reliability tests were carried out under voltage and temperature stressed conditions. Predicted lifetime was estimated from Black’s equation as over 10 years. Extremely low leakage current and good TDDB reportedly indicate that the Cu connections are well isolated by the dielectric. They fabricated a stacked back-illuminated CMOS image sensor with “22.5 megapixel 1/2.6 size CIS featuring a 1.0μm unit pixel size and an ISP…” using their Cu2Cu hybrid bonding process.

TechInsights

Ray Fontaine of TechInsights in his “Survey of Enabling Technologies in Successful Consumer Digital Imaging Products” detailed the technologies responsible for the remarkable advances in mobile phone camera performance over the last decade.

He notes that “Two-die stacks, comprising a back-illuminated CIS and mixed-signal image signal processor (ISP), have emerged as the dominant configuration for leading smartphone camera chips” and adds that “The recent manufacturing trend for back-illuminated CIS chips in a stacked configuration seems to have stabilized at the 90/65 nm process generation “ as shown in the fig below.

Techinsights 1

He notes that Sony’s current leadership position in the industry is due to the fact that they were the first to bring stacked CIS chips to market, by implementing homogenous wafer-to-wafer bonding (oxide bonding) with TSVs in 2013 and Cu-to-Cu hybrid bonding, (also known as Cu2Cu bonding or DBI), in 2016. OmniVision’s first observed stacked chips, fabricated with foundry partner XMC in 2015, used a ‘butted’ TSV structure in which a single, wide TSV contacted both a CIS and ISP pad structure. OmniVision later adopted a unified TSV structure for its 1.0 μm pixel generation PureCelPlus-S chips, fabricated by foundry partner TSMC. The observed Samsung stacked chips in production also feature a butted TSV structure, but instead use a W-based TSV window liner for vertical interconnect. These are shown below.

techinsights 2

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 351 ASE Tech Forum Part 3: Plasma Dicing, 2.5/3D Options

By Dr. Phil Garrou, Contributing Editor

Several of you have asked how Hannah, Madeline and family have survived the floods down in Houston. Thanks for your concern. Luckily, the old time Texans built Rice University on high ground and my son bought in a neighborhood near there. However, that doesn’t mean they didn’t see water. The pic below shows Maddie standing on the sidewalk outside their house knee deep in water, but, as you can see to the right, it was nothing compared to other parts of the city!

madeline

 

PLASMA DICING

Finishing off our look at the ASE Tech Forum, Plasma-therm (working with ON Semi and DISCO) examined Plasma die singulation. One would look to plasma dicing to avoid the damage caused by mechanical blade dicing or the HAZ caused by Laser dicing which requires as larger than normal street to act as a keep out zone. Stress is also reduced by plasma dicing as is shown in the figure below. It is also clear that plasma dicing can result in more die per wafer due to the smaller required street/kerf.

plasmatherm 1

 

However, plasma dicing cannot etch through metal so any features in the streets (such as test structures) must be dealt with.

One solution is to isolate the test structures and process control monitors and etch around the die as shown in the fig below.

plasma-therm 2

In terms of market adoption of plasma dicing, they offered the following slide showing us what was qualified in production and what was in development.

plasmatherm 2

2.5 / 3D Technology Choices

ASE’s Chris Zinck in his examination of 3D packaging presented an interesting slide on 2.5/3D options plotting technology solutions vs substrate L/S capability. It is shown below. In their view what is evolving is a technology choice based on required density with std FC and PoP at > 10um; fan out using advanced laminate silicon-less RDL solutions between 10um and 1um and silicon interposers at less that 1 um. IFTLE is not so sure about the advanced substrate solutions in the 3-1um range , but in general this is a good way of looking at how the market is breaking out.

ASE 1

IMAPS 50th in Raleigh

Hope to see many of you at this years fall IMAPS meeting which just so happens to be the 50th anniversary of IMAPS and just so happens to be down the road from me in Raleigh NC. As I explained a few blogs ago [see IFTLE 336 “ISHM to IMAPS…” ] IMAPS has been there since the beginning of our industry and it will be fun to see all of those who have contributed to packaging through the years.

IMAPS

 

For all the latest in advanced packaging, see you at IMAPS 2017 and, of course, keep reading IFTLE…

IFTLE 350 DARPA Electronics Resurgence Initiative: Going Beyond Moore’s Law

By Dr. Phil Garrou, Contributing Editor

IFTLE has discussed in detail the coming end of Moore’s Law and the implications that holds for our electronics industry. For instance see IFTLE 300 “ITRS 2.0 – It’s the End of the World As We Know It”,

Well DoDs DARPA has stepped up and is attempting to lead the industry out of the quagmire that is the myriad of options that have presented themselves.

On June 1, DARPA’s Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) “to open pathways for far-reaching improvements in electronics performance well beyond the limits of traditional scaling”. Key to the ERI will hopefully be new collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD. The DoD proposed FY 2018 budget reportedly includes a $75 million allocation for DARPA in support of this, initiative. It is reported that in total we are looking at a $200,000MM program.

For details on the ERI see DARPA-SN-17-60 [link]

chappellThe program will focus on the development of new materials for devices, new architectures for integrating those devices into circuits, and software and hardware designs for using these circuits. The program seeks to achieve continued improvements in electronics performance without the benefit of traditional scaling. Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO), which will lead the program, announced “For nearly seventy years, the United States has enjoyed the economic and security advantages that have come from national leadership in electronics innovation…..If we want to remain out front, we need to foment an electronics revolution that does not depend on traditional methods of achieving progress. That’s the point of this new initiative – to embrace progress through circuit specialization and to wrangle the complexity of the next phase of advances, which will have broad implications on both commercial and national defense interests. ”He continued “We need to break away from tradition and embrace the kinds of innovations that the new initiative is all about…”

The chip research effort will complement the recently created Joint University Microelectronics Program (JUMP), an electronics research effort co-funded by DARPA and SRC (Semiconductor Research Corporation). Among the chip makers contributing to JUMP are IBM, Intel Corp., Micron Technology and Taiwan Semiconductor Manufacturing Co. SRC members and DARPA are expected to kick in more than $150 million for the five-year project. Focus areas include high-frequency sensor networks, distributed and cognitive computing along with intelligent memory and storage.

The materials portion of the ERI initiative will explore the use of unconventional materials to increase circuit performance without requiring smaller transistors. Although silicon is used for most of the circuits manufactured today, other materials like GaAs, GaN and SiC have made significant inroads into high performance circuits. It is hoped that the initiative will uncover other elements from the Periodic Table that can provide candidate materials for next-generation logic and memory components. One research focus will be to integrate different semiconductor materials on individual chips, and vertical (3D) rather than planar integration of microsystem components.

The architecture portion of the initiative will examine circuit structures such as Graphics processing units (GPUs), which underlie much of the ongoing progress in machine learning, have already demonstrated the performance improvement derived from specialized hardware architectures. The initiative will explore other opportunities, such as “reconfigurable physical structures that adjust to the needs of the software they support”.

The design portion of the initiative will focus on developing tools for rapidly designing specialized circuits. Although DARPA has consistently invested in these application-specific integrated circuits (ASICs) for military use, ASICs can be costly and time-consuming to develop. New design tools and an open-source design paradigm could be transformative, enabling innovators to rapidly and cheaply create specialized circuits for a range of commercial applications.

DARPA CHIPS

As part of this overall Electronics Resurgence Initiative, DARPA, last week, had their kick of meeting for the CHIPS program (Common Heterogeneous Integration and Intellectual Property (IP) Reuse). We have previously discussed CHIPS here [see IFTLE 323 “The New DARPA Program “CHIPS”…”

The CHIPS vision is an ecosystem of discrete modular, IP blocks, which can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of such IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. The CHIPS program hopes to develop the design tools and integration standards required for modular integrated circuit (IC) designs.

Program contractors include Intel, Micron, Cadence, Lockheed Martin, Northrop Grumman, Boeing, Synopsys, Intrinsix Corp., and Jariet Technologies, U. Michigan, Georgia Tech, and North Carolina State University.

The CHIPS program will tackle digital interfaces and systems and their supporting technologies with the goal of:

– developing common interface standards                                                                                                                                                    – enabling the assembly of systems from modular IP blocks                                                                                                               – demonstrating the reusability of the modular IP blocks via rapid design iteration

CHIPS 1 CHIPS 2

For all the latest in advanced packaging, stay linked to IFTLE…