Author Archives: sdavis

IFTLE 295 Advances in FO-WLP at 2016 IEEE ECTC

By Dr. Phil Garrou, Contributing Editor

Continuing our look at IEEE ECTC 2016. Let’s examine some of the activity in the FOWLP arena.

ASE

At the recent ECTC conference, Bill Chen of ASE proposed categorization of fan out packaging.

While the initial driver for fan-out packaging like the Infineon e-WLB was to increase available IO for niche baseband applications, the main driver now is clearly to achieve multi chip packaging.

ASE 1

 

Chen now proposes we categorize FOWLP options as follows based on chips first, chips last, multichip or stacked chips (PoP):

ASE 2

DECA – Adaptive patterning for FO WLP

FO-WLP enables size and performance capabilities similar to Wafer-Level Chip- Scale Packaging (WLCSP), while extending the capabilities to include multi-device system-in-packages, with lower costs than 2.5D interposer technologies. But – Adopting these new technologies for single die and multi die system-in-packages requires more advanced design methodologies and tools than traditionally used in traditional WLP.

In a fan-out process the key step is the creation of a reconfigured wafer or panel. First copper studs are formed on the native device wafer over the bond-pads, and then the wafer is singulated. A pick-and-place machine then attaches the dies face-up to a carrier with a temporary adhesive. Then, the carrier and dies are over-molded, the temporary adhesive is removed, and the front of the panel is ground to reveal the copper studs. After this process, called panelization, a first via layer (VIA1), redistribution layer (RDL), second via layer (VIA2), and under-bump metallization (UBM) are formed using processes similar to WLCSP.

Two main challenges prevent widespread adoption of wafer-level fan-out technology are warpage and die shift during processing. Warpage is caused by the mis-matched CTE between mold-compound and silicon and can be addressed using structural approaches, such as the fully molded structure, or by tuning process parameters. Die-shift is the accumulation of die position error from chip-attach tolerances and movement during over-molding. Tuning process parameters such as pick-and-place force can help minimize shift, and movement due to molding is often predictable enough to compensate for during chip-attach. However, the total die shift can still range from 30 μm to 45 μm with rotation up to 0.3°on a high-throughput machine.

The die-shift problem has limited traditional FO-WLP from widespread adoption. In order to meet industry requirements, FO-WLP must be processed with high-throughput chip-attach machines, typically resulting in shift distributions that cannot be handled by traditional processes. Additionally, these processes cannot handle finer pitch connections to the die with wider shift distributions

The DECA technology derived to do this is called “Adaptive Patterning”. In this manufacturing process, an optical scanner is used to measure the true position of each die after molding, and a uniquely generated fan-out design is applied to each package. One design technique, adaptive alignment, shifts and rotates the first via and RDL layer to match the die location. Another technique, adaptive routing, utilizes a fan-out RDL design with sections removed near vias that contact the die. The final RDL connections to the die are generated by an auto-router after the true die locations are known.

In the case of adaptive patterning, the design rules specify the maximum die-shift for which the design can be adjusted. For both cases, a simple approach limits the die-shift to a range of X, Y, and θ values (e.g. −30 μm to 30 μm and -0.3°. The table below shows the magnitude of shift possible from rotation alone on several package sizes.

DECA 1

By adapting to die-shifts that are an order of magnitude larger than can be tolerated by traditional processes, this technology solves the last major industry challenge to adoption of fan-out packaging. The design rules for adaptive patterning are more complicated than traditional rules; however, this may be required for designs with high density interconnects and scarce routing space.

Siliconware – Fine Pitch RDL for High Density 2.5D

The original purpose of the Redistribution Layers (RDL) was to assist in the adaption of metal bumping and flip chip packaging technologies, by the addition of the metal and dielectric layers onto the wafer surface to re-route the legacy designed irregular peripheral I/O layout, into a new area array bond pads layout to facilitate a balanced metal bumps and flip chip bonding. The redistribution layer technology required polymeric thin film (e.g. BCB, Polyimide, PBO) as insulator and a semi-additive metallization scheme (often Cu pattern plating).

RDL technology, has extended its application into advanced packaging technologies, such as fan out wafer level packaging (FO WLP) and various TSV-less, substrate-less multiple chip integration, that to drive the cost effective miniaturization of system-in-package (SiP) application. The Cu RDL that in production, the line width/ spacing are 10 μm/10 μm or pitch of 20 μm .

The capability for fine pitch and multi layer RDL must be established at OSATs because the market is currently driving towards multiple chips integration and SiP applications. Furthermore, it is more difficult for the L/S < 2um due to there is no sufficient process window of lithography process.

While scaling from 10 to 3 μm poses no significant technical difficulties with existing tools, as long as the Cu thickness are proportional shrunk to keep the width/ height aspect ratio, below pitch of 6 μm, it is difficult to make such fine pitch layers on top of other layers, since the topography of multiple RDL with any planarization, that is out of the depth of focus (DoF) range of 2 μm and 1 μm, and such 2 μm / 4 μm pitches, would be limited to the first RDL in the multiple RDL scheme.

Cu dual damascene technology are generally used in ICs manufacturing or silicon interposer fabrication. CVD dielectric films (Si oxide, Si nitride) are commonly used in the modern IC fabrication fab (90nm and beyond), and can be used for up to three levels of 1um Cu RDL .

A comparison between a Cu dual damascene process and traditional organic RDL process are shown below. The Cu dual damascene process can provide a flat surface with excellent topography and we can combine this advantage with traditional RDL process to resolve the surface topography issue for the multiple RDL layers. For example in 3 layers RDL structure, we can use one dual damascene layer and two organic RDL layers to reduce the TTV of surface topography and then satisfy the DoF requirement of photo-resist materials.

SPIL 1

Cu dual damascene technology is a challenge for traditional bumping process and tools, especial for the lithography, Reactive-Ion Etching (RIE), Cu electroplating, and Chemical-Mechanical Planarization (CMP) steps. For the lithography process of Cu dual damascene, the key points are the opening dimension and profile of photoresist materials after the lithography process. Current development and research direction focus on the high resolution photo-resist materials and high numerical aperture (NA) exposure tools. The dielectric material of Cu dual damascene is generally silicon oxide (SiO2). In order to increase the oxide etching thickness accuracy, a thin silicon nitride (SiNx) film is deposited as stop layer between the oxide layers.

The figure below shows a silicon interposer structure with TSV and there are 3 dual damascene metal layers with u-pad in frond side of interposer and there is one RDL layer with C4 bumps on the backside of the interposer. The L/S are 1um and thickness 1um also for 3 dual damascene layers. And layers are connected by 0.5um diameter and 0.9um thickness via opening.

SPIL 2

Hybrid integration of the fine pitch CVD RDL with polymeric dielectric RDL is shown in the figure below. It is a substrate-less package with 0.4mm pitch BGA balls; the package size is 15mm x 14mm with one CVD dual damascene RDL with 2/2um line L/S combined with two organic RDL with 5/5um and 10/10um line L/S.

SPIL 3

 

The top die jointed with RDL by 40um pitch u-bump and molded by molded underfill (MUF) technology. The CVD oxide and nitride RDL 2/2um line L/S connected to organic RDL 5/5um line L/S by 10um via open which made by deep reactive-ion etching DRIE process. The second RDL contains 10/10um line L/S. This hybrid test vehicle passed open/short test after 96hrs of HAST, 1000 TCB cycles and 1000hrs of HTS.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 294 ECTC 2016: IMEC Discusses Economics of TSV Implementation Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2016 IEEE ECTC conference.

IMEC – Economics of TSV Implementation Options

IMEC discussed their conclusions about the integration cost of TSVs for TSV middle vs TSV last processing. A 3D cost model developed at IMEC was used to analyze the cost of the different TSV integration approaches with different dimensions investigated for each flow.

IMEC 1

TSV lithography

The main difference in this step between the TSV middle and TSV last flow is that the TSV middle lithography is processed at a FEOL-fab compatible tool. In the case of TSV last an OSAT-fab compatible lower-cost tool can be used. This difference results in a TSV litho step cost which is approximately 30% more expensive for the TSV middle flow compared to TSV last flow. Furthermore, no difference on the lithography cost is observed due to different TSV dimensions.

Si TSV etch

The processing time for TSV etch depends on the TSV depth and the TSV aspect ratio. Smaller depth TSVs have faster etching times (for example the 5×50 vs. the 10×100 TSV process). In addition, TSVs with more aggressive aspect ratio have slower etching times (the 3×50 TSV middle compared to 5×50 or the 5×50 TSV last compared to 10×50).

TSV liner processing

Following the opening of the TSV hole in silicon, an insulating oxide liner layer is deposited. In the case of TSV middle, different liner deposition approaches are applied, depending on the aspect ratio of the via. In the case of an aspect ratio up to 1:10 a TEOS oxide is deposited. As the TSV aspect ratio becomes more aggressive (for 3×50 and 2×40 TSVs), a more conformal liner layer is required with higher uniformity in the liner thickness along the TSV. Therefore, a PEALD oxide deposition approach is preferred to achieve a liner thickness of 100nm, capped with 30nm SiN layer.

In the case of TSV last, the liner needs to be opened (etched) at the bottom of the via prior to further processing, therefore a highly conformal layer is required. For this reason a PE-ALD oxide deposition is used for all TSV geometries processed with the TSV last approach.

TSV liner opening (for TSV last flow) In the case of TSV last process flow, the oxide liner layer at the bottom of the TSV should be opened after deposition to allow for a conductive path towards the metal layers at the TSV bottom. This is one of the differentiating steps between the TSV middle and TSV last flows. Longer processing times (resulting in smaller tool throughput) are required for the narrower TSV diameter sizes.

TSV Barrier and Cu Seed processing

The first steps towards metallization of a TSV structure are the deposition of a barrier layer to prevent Cu diffusion, followed by a deposition of a Cu seed layer that will allow the Cu filling of the TSV through electroplating. Different deposition options are considered for different TSV sizes . In the case of TSV middle with aspect ratio 1:10 (i.e. 10×100 and 5×50), a PVD Ta barrier layer followed by a PVD Cu seed layer can be applied. As the TSV diameter is scaled further and the TSV aspect ratio becomes more aggressive, alternatives such as ALD processing are required. ALD deposition of 12nm TiN has been demonstrated as a successful barrier layer for a 3×50 TSV middle structure. The barrier and seed layers should be removed by CMP after the TSV processing flow. The cost of the CMP process depends on the thickness of the deposited layers. Therefore, the thin layers deposited by ALD can offer an advantage from a cost perspective when the processing cost of the CMP is also considered.

TSV Cu plating and impact on CMP

Plating time and material cost for the TSV filling depends upon the depth and the diameter of the TSV structure. TSV plating results in an overburden of Cu plated on top of the entire wafer area that needs to be removed by CMP. The Cu CMP process has two stages: (i) bulk Cu polish that is relatively fast and removes most of the plated Cu and (ii) fine Cu polish that is slower and clears the remaining Cu traces from the wafer surface, including the Cu seed layer.

Cost Comparison:

The overall processing flow cost can now be compared for different TSV geometries as shown in the figure below.

IMEC 2

In the case of the TSV last processing, the additional costs for the PE-ALD liner, etching the TSV liner within the via, and the backside CMP result in higher processing cost for the TSV last 5×50μm flow by up to 10%.

In the figure below it is demonstrated that scaling the TSV size and the TSV pitch is possible while keeping the processing cost under control. This is achieved by replacing the thicker PVD deposited layers used in the larger TSV geometries with thinner ALD layers for the scaled TSV sizes. Although the processing cost for the ALD layers is higher, the cost for CMP polishing of these thinner layers is lower. This tradeoff helps to control the processing cost as the size and pitch of TSV is scaled from 5×50 down to 3×50 and 2×40 TSV sizes.

IMEC 3

Overall it has been shown that main cost contributors for TSV processing are the CMP, the deep Si etch, and the barrier and seed deposition steps.

IMEC – Bumpless Process for 10µm Pitch Assembly

IMEC detailed the use of Damascene processing to achieve a bump-less assembly process for sub 10um pitch interconnects.

Microbumps and high density TSV pitches enable high density interconnects between two or more chip stacks for different applications. However, the mechanical stability of microbumps, bump height uniformity, microbumps under-cut during seed and barrier wet etching, high aspect ratio lithography process, dicing and handling issues and difficulty in thermo-compression bonding (TCB) alignment and stacking for fragile microbumps in 10um pitch range ae serious concerns.

In the IMEC bumpless process UBM in the bottom die is embedded in BEOL dielectric and is fabricated in by damascene processing enabling less bump height variation, smooth UBM surface and thus pitch reduction. Schematic of the bump-less process concept is shown below. The top die which contains UBM and solder, the UBM is plated in dielectric followed by Sn plating in resist. After stripping resist and seed/barrier wet etching, polymer (CA6001B from Hitachi ) is coated and planarized by CMP or surface planer. After Sn plating and seed etch, microbumps were embedded in a spin coated polymer followed by a soft bake step. For planarization, CMP and surface planer tools were used. Polymer acts as support material for planarization and also as underfill material for 3D stacking.

IMEC 4

During fast TCB bonding, the polymer starts to reflow and bond to the oxide followed by Sn / Cu reaction and IMC formation and final polymer cure.

Processing is on-going in IMEC with 5um pitch TSV and bump for die to die, die to wafer and wafer to wafer bonding applications.

For all the latest on 3DIC and other advanced packaging applications, stay linked to IFTLE…

IFTLE 293 Sarda Voltage Regulators; ECTC 2016 – Copper Pumping; Copper Pillar on Embedded Trace

By Dr. Phil Garrou, Contributing Editor

Sarda Heterogeneously Integrated Power Stage

Sarda, UTAC and AT&S announced at the recent Int Symp on 3D Power Electronics, Integration and Manufacturing Symposium that they would be using UTAC’s “3D SiP” technology (based on ECP technology from AT&S) to deliver small, fast voltage regulators for use in data centers.

Sarda’s Heterogeneous Integrated Power Stage (HIPS) technology replaces Si switches with GaAs switches in voltage regulators which reportedly increases switching frequency by 10X, improves transient response by 5X and reduces size by 80%. This in turn can reportedly reduce data center power consumption by 30%.

Sarda

Continuing our look at the 2016 ECC presentations:

 

Osaka Fine Feature Electrodeposition Res Center – Copper Pumping

Kondo from the Fine Feature Electrodeposition Research Center in Osaka discussed his solutions for copper pumping. We have known for years that the use of silicon vias (TSVs) causes copper extrusion during copper annealing due to the mismatch of the thermal expansion coefficient of Cu and Si. This extrusion can cause damage to the interconnect above it, as shown in the figure below.

Beyne and co-workers at IMEC developed a solution for avoiding this damage by annealing the TSV at >425 °C and then CMP’ing the resultant copper protrusions before building the layers of on chip interconnect.

Kondo 1

The Small Feature Electrodeposition Lab has now reportedly developed an additive “A”, which restricts the copper pumping phenomena and thus eliminates the need for CMP. A comparison of pumping with and without additive A at 450°C is shown below.

Kondo 2

Pumping at 450°C (a) room temp; (b) without additive “A” at 450°C ; (c) room temp ; (d) without additive “A” at 450°C

 

The resistivity of electrodeposited copper TSV after 450℃ annealing for the wiring is only 1.09x that of conventional electrodeposited copper.

Initial investigations of the mechanism of this reaction point to 100nm carbon deposition into the triple point of the copper grains which causes unit cell contraction upon annealing .

Amkor – Copper Pillar on Embedded Trace

The continuing push toward miniaturization in both planar & stack-up dimensions, has driven the use of chip-scale packages (CSP) in consumer microelectronics.

The state of the art method for joining die and substrate is currently using solder-capped copper pillars. The pillar and solder are previously plated onto the die through wafer level processing. The advantages of copper pillar technology have been well documented and include greater reliability by inhibiting electromigration , as well as enabling fine pitch interconnects.

There have also been advances on the substrate side where thinner packages are the goal. One

enabling technology has been the development and use of Embedded Trace Substrates (ETS), where the top-layer metal is embedded into the dielectric material instead of being deposited on top of it. This results in a near-planarity of the dielectric material and the top-layer of metal as shown in the figure below.

amkor 1

The advantages of ETS include a lower profile, potential layer reduction and reportedly lower cost. Substrate manufacturing costs and stack-up height are both reduced due to the absence of a core material. Layer reduction can take place due to removal of restrictive core-layer design rules.

Warpage is a real concern in the assembly of packages with ETS, but for applications where warpage can be properly managed, the combination of copper pillar bonding on ETS offers low-cost, thin solutions for packaging advanced devices.

While the near-planarity of metal traces with the surface of the substrate in ETS is effective at reducing the risk of bump-to-trace shorting, there is a corresponding increase in the risk of electrical opens especially as L/S shrinks. Amkor has developed a model to test for interconnection reliability between copper pillar bumps and ETS bond pads, based on design parameters and in-process variables. The critical recess depth of the ETS bond pad is identified as a key parameter linked to interconnection success. Reducing the risk of non-wets requires attention to design and processing during substrate manufacturing, bumping, and assembly.

For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…

 

IFTLE 192 New Fab Construction? Look to China; Rumors from ECTC: InFO — ASE — DECA

By Dr. Phil Garrou, Contributing Editor

Fab Construction Declining, New Construction be mainly in China.

Over the last few years, IFTLE has detailed the slowdown in scaling which is leading to the construction of fewer and fewer latest node fabs. We have also noted that this maturity of our industry has led to the consolidation trend that has been so prevalent the past few years.

Peter Clarke of EE Times Europe recently reported the latest SEMI data on new fab construction [link]. They predict 19 wafer fab starts in 2016 and 2017 and predict that China, will be responsible for more than half of them. This is a low total number by historical standards consistent with our trend of slowdown.

(12) of the fabs are 300mm, (4) are 200mm, and the (3) LED fabs are 150mm, 100mm, and 50mm respectively. Activity in the 3D NAND, 10nm logic, and foundry segments is expected to push equipment spending up 1.5% globally vs 2015. Fab equipment spending declined by 2 percent in 2015. SEMI lists a probability 60% or higher for these predictions but admits that some may be delayed.

fabs 1

The heavy participation by China is also consistent with IFLE noting that China would be the Wild card when it comes to future IC production (see “IFTLE 238 ASE & the Apple watch, ASE / TDK JV; China: the Wild Card” [link]).

SEMI estimates far more manufacturers are looking at fab upgrades or facility conversions as shown in the table below. IFTLE agrees that this is likely the way of the future.

fab 2

Continuing our look at the 2016 ECTC

Wafer Level Integrated Fan Out Packaging (InFO) – TSMC

TSMC’s InFO

TSMC’s InFO

IFTLE has stated over and over that the front end practitioners are paying more and more attention to packaging because they understand that it is the future way of customizing a circuit and could have more value in the long run than further scaling. (At least till the CMOS replacement is found sometime in the future). This was never made clearer than by the rumors that TSMC had been selected as Apple’s exclusive manufacturer for this year’s A10 chip expected to power the iPhone 7 and new iPad models. “The new chip is expected to use a 16nm process combined with a new InFO packaging, which allows chips to be stacked on top of each other and mounted directly to a circuit board, instead of onto a substrate first, reducing both the thickness and the weight of devices. Apple is rumored to be TSMC’s first customer to use InFo.”[link]

In fact it is likely that this was also a main motivation for Samsung EM’s recent announcement that they would be entering the FO-WLP business by the end of the year.( see IFTLE 291 : “Samsung EM enters FO-WLP Packaging Mkt…” [link] ).

Session 1 paper 1 at the 2016 ECTC was a TSMC paper on InFO by Doug Yu and his team at TSMC. Up until a few years ago, Doug had been the key technology Mgr developing the latest front end copper low K interconnect for each succeeding scaling generation at TSMC. He now runs 2.5D and wafer level packaging like InFO…does that tell you anything ? I think it does.

Since they first indicated that InFO was on their radar , ~ 2012, TSMC has focused on presenting comparative data showing the better performance that InFO would deliver vs other options. This latest paper continues in that venue comparing the form factor and performance advantages of InFO PoP over std FC-PoP. What’s been missing from the InFO presentations has been any detail on the process flow. (see IFTLE 261: “….The info on InFO…” [link].

In IFTLE 261, we reported on a rumored InFO process flow which consists of (1)copper pillar plating on the die,(2) die placed face up on tape, (3)molding to generate reconstituted wafer, (4) polish down to reveal tops of pillars, (5) RDL processing on this polished surface. The capability for finer features than standard fan out packaging comes from the more planar starting surfaces and better control of the photo processes.

A prevalent rumor going around ECTC is that ASE will become the second source of InFO technology for the industry. Does this make sense ? Well ASE is known to be a preferred partner for TSMC packaging and ASE has won its own Apple contracts for supplying SiP for the Apple watch (see IFTLE 238: “ASE & the Apple watch…” [link]). So yes I’d say this is plausible.

In addition ASE and DECA have just announced that ASE has licensed the DECA FO technology and will be putting in a line to manufacture it. [link]

Is it logical that ASE is about to scale up two different fan out packages at the same time ?…..probably not.

It is more logical if the TSMC process and the DECA process are similar enough that this really constitutes only ONE line for both products.

The DECA process flow (as published in the 2013 IWLPC) is shown below.

DECA

DECA Process Flow

Enough said…

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…

IFTLE 291 Samsung EM enters FO-WLP Packaging Mkt; Mold Cmpd Free FO-WLP for Sub MM ICs

By Dr. Phil Garrou, Contributing Editor

Samsung Electro-Mechanics launches IC packaging business

Reports are that Samsung EM (Electro-Mechanics), part of the Samsung Group, is entering the integrated circuit packaging business [link]

Samsung Electronics system LSI and Samsung Electro-Mechanics will join forces to staff the project and launch the business. They will transform current LCD assembly lines in Cheonnan KR into IC packaging lines. It is unclear whether they have developed full panel processing capability which many packaging OSATS have been trying to accomplish, or they will work in smaller formats.

Certainly their goal is to supply both Samsung and win the business of smartphone makers, like U.S.-based Apple. Apple recently gave a large order to Samsung’s competitor TSMC who will be using their InFO based FO-WLP packaging technology in Apples next smartphone.

Samsung EM has announced that they will be packaging power management ICs with Fan-out Wafer Level Package (FO-WLP) in their new factories.

IFTLE speculates that Samsung EM, a major provider of high density substrates also saw that FO-WLP was going to, or already has, begun to eat into their high density substrate business since FO-WLP can do the same job at a lower cost.

Plans are for the packaging factories to be operational in the first half of 2017.

Continuing our look at the 2016 ECTC

X-Celeprint & RTI Int Propose FO-WLP Free of Mold Compound for sub mm ICs

Closing out the morning for the “Advances in Fan Out Packaging” session at the 2016 ECTC, Matt Lueck of RTI Int discussed the results of their joint program with X-Celeprint.

A common aspect to all fan-out packaging is the requirement to physically assemble devices into dispersed arrays, often called reconfigured wafers, which provides the real estate needed to fan-out. Devices made in sub-mm chip sizes can impose cost and performance challenges to FO-WLP using serial pick-and place assembly technologies. RTI and X-Celeprint joined forces to develop a fan out package for sub mm IC using the X-Celeprint massively parallel assembly technology called micro transfer-printing, which is well-suited for handling very thin and fragile devices.

In their micro transfer-printing technology a polymer layer is first applied to the substrate before the assembly process, and the devices are assembled in a face-up configuration. Following the formation of the reconfigured substrates, conventional redistribution layer (RDL) and solder ball processing was performed. Two different photoimageable spin on dielectrics, HD4100 PI and Intervia 8023 epoxy,

were used as the RDL dielectrics. The fan-out package contains no molding compound and is made using standard wafer-level packaging tools.

There are potential benefits from fan-out packaging strategies that do not require molding compound. The process described here does not suffer from the “die drift” that occurs during compression molded fan-out packaging which often requires special adaptive alignment techniques. It also does not suffer from the wafer and package warpage that can occur in molding compound based fan-out packages.

Micro-transfer printing was used to assemble reconfigured wafers of devices (80um x 40um chips with a redistribution metal and six contact pads), onto 200mm wafers. After assembly, they undergo a standard wafer level redistribution and bumping process. The final fan-out package pitch on the 200 mm wafer is 1.4mm x 1.0mm with six 250 μm solder bumps. The fan-out packages were assembled and reflowed onto FR4 test boards.

In the figure below shows (A) the chiplet source wafer after partial removal of chiplets with the elastomer stamp; (B) a completed fan out package before solder ball placement; (C) close-up of the interconnect to the chi pads; (D) Final FO-WLP

WLP

 

Initial yields are reported to be 97%.

Two PCB test vehicles populated with 60 die each were built for thermal cycle testing. The board level thermal cycle testing was run under -40°C to 125°C. None of the die showed more than 0.2 ohm change in average resistance.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 290 ASE / SPIL: The Struggle Continues; UMD’s Pecht Wins IEEE Packaging Field Award

By Dr. Phil Garrou, Contributing Editor

More on the ASE / SPIL “holding company”

In IFTLE 289, I described the formation of a holding company to reach a peaceful merger of ASE and SPIL. After a week at the recent ECTC, I have concluded that maybe the merger will not be so peaceful after all. Rumors abound that SPIL is still not a happy camper.

While both sides are awaiting legal Oks, reportedly from Taiwan, China and the US, I hear that the holding company board will be composed of 14 members. 9 will be from ASE, 2 from SPIL and 3 from the outside. Hummm…….still sounds like an acquisition to me. Wonder who will be running the show in this operation? If anyone feels that is not correct, feel free to comment.

No Resisting Consolidation

My blogs on consolidation in the Microelectronics industry started way back in the predecessor to IFTLE, perspectives from the leading edge or PFTLE, which ran for > 3 years in Semiconductor International. When I saw AMAT making acquisitions of back end of line equipment companies it became clear that consolidation was underway.

In IFTLE 195 (June of 2014), I explained the 4 stages of a Business cycle as discussed thoroughly in the Harvard Business Review. These stages have held true throughout history for planes, trains and automobiles and every other industry that has ever existed on this planet. Microelectronics is no exception, it is not beyond the control of the basic laws of economics.

The best examples of this in our industry has been DRAM and hard disk drives. They have run their course and arrived at stage 4 of the business cycle where the top 3 companies claim 70-90% of the market. It was inevitable and it happened.

Our growth rate for many segments of the industry are now following the GDP (i.e we are a mature industry in stage 4 of the business cycle) as shown in the IC Insights slide presented at the recent IMAPS Device Packaging Conference. IC growth is now 96% in correlation with GDP.

consolidation 1

 

The 4 stages of the business cycle notes that growth for stage 4 companies must come from spinning off new businesses or buying into aligned fields. In our case that may be the front end buying up the back end and/or foundries buying up the “lucrative segments” of the packaging industry. This will also hold true for materials and equipment suppliers, conferences and everything else in our microelectronics infrastructure.

Supplier consolidation was evident at the ECTC exhibits this past week. Going past the Dow Chemical, Dow Corning and HD Micro booths it struck me that next year there may be only be one booth and probably fewer attendees from the newly merged company (assuming the legal hurdles are met). While Dow Corning (the JV between Dow and Corning Glass) was included in this merger of equals, it is currently unclear what happens to HD Micro (the Hitachi Dupont PI JV) . While Dupont and Hitachi were never really competitors in the rest of their electronics business, Hitachi and Dow are (mainly through the R&H operation now part of Dow). So will Hitachi or Dow/Dupont buy out the HD JV ?? or will it just stay as it is?? No one seems to have that answer.

ECTC 2016 the 66th ECTC

HuffmanAlan Huffman of RTI Int. presided as the General Chair of the 66th ECTC Conference in Las Vegas week before last. The ECTC Conference is the flagship conference of the Components, Packaging and Manufacturing Technologies (CPMT) society of IEEE. That name is a mouthful that none but the members really understand. Many favor a simpler name like the “Electronics Packaging Society”, which, at a high level, really fully describes what it is. This Conference is the undisputed leader in all things packaging. While most other conferences struggle to get the number of presentations necessary to put on their shows, ECTC routinely turns away > 50% of submissions. If you want to know what’s going on everywhere in the world, in electronic packaging, this is the place to be.

It was started the year after I was born and had been jointly owned by IEEE CPMT and the EIA (Electronic Industry Association) till Bill Chen and I, under our CPMT Presidencies bought out the EIA. That’s was a deal that we both are very proud of. It is certainly our legacy to the organization.

Anyway, this years 36 sessions, courses and exhibits covered the entire Microelectronic packaging infrastructure. I will be sharing what I consider key presentations with you for the next few weeks.

2016 CPMT Field Award – Michael Pecht UMD

PechtThe highest award honoring technical achievement in electronic packaging is the IEEE Components, Packaging and Manufacturing Technology Society Award – an IEEE Technical Field Award, sponsored by the CPMT Society and administered by the IEEE Awards Board. Past winners include Rao Tummala, CP Wong, John Lau, Herb Reichl, Avi Bar-Cohen, George Harman, Demitri Grabbe and Paul Totta. If you don’t know who any of these leaders are, you need to do more reading in the area. This year’s winner is Michael Pecht from Univ. of Maryland where he runs the Center for Advanced Life Cycle Engineering and has been a leader in physics-of-failure based electronic reliability. IFTLE salutes Professor Pecht who truly belongs in this elite group.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 289 ASE / SPIL: A Non-Hostile Resolution; IMAPS Polymers Conf Part 2

By Dr. Phil Garrou, Contributing Editor

ASE & SPIL find a non hostile Solution

When the ASE acquisition of SPIL stock began last year, I labeled it as a hostile takeover despite ASE’s pronouncements that it was not. Certainly we have seen SPIL resisting this acquisition. Last week, it was announced that they have found a non hostile solution where they will be joined through a new holding company. Under the holding company, SPIL and ASE conduct their own business/operations Independently as now. [link]

The deal creates a holding company that will list in Taiwan and the United States, with current securities of ASE and SPIL being delisted. Each will retain its management and staff. All working conditions, benefits etc remain unchanged. Both companies have one month to approve the deal, subject to the regulatory approval, most critical is the anti-trust examination from Taiwan, China, and USA governmental agencies.

Continuing our look at the IMAPS Polymers Conf.

Merck – Photoresists for Fine Line RDL

Toukhy of the old AZ group (now Merc performance materials) looked at photoresist development for fine RDL Applications.

They see future requirements for fine line RDL as:

– continued demand for thick uniform resist films

– higher resolution, aspect ration and vertical profiles

– improved focus latitude and process window

– chemical resistance to plating solutions

– longer allowed post exposure delays

– eliminate or reduce post exposure bake sensitivity

Conventional resist platforms are usually either chemically amplified or DNQ based. Positives and negatives are shown below:

Merck 1

 

Their product lineup includes:

Merck 2

 

Toray – Wafer Level NCF

Tomikawa of Toray looked at new non conductive films for their collective bonding process. Toray NCF has been used in HVM since 2010 on application processors and graphics ICs. The standard process flow is shown below:

Toray 1

A close up of flip chip bonding solution is shown below:

Toray 2

 

Assembly could be speeded up considerably as the chips could be pick and placed and then gng bonded with a single heat treatment as shown below.

Toray 3

Toray has developed a NCF for gang bonding that shows not voids and passes TCT (temp cycling testing).

Dow – BCB laminate film

With the upcoming merger of Dow Chemical, DuPont and Dow Corning (pending Govt approval) I wonder what will be the disposition of HD Micro, which provides a majority of the PI and PBO market? Will PI, PBO and BCB all be coming from the same company in the future? Just one of the questions that consolidation brings to our industry.

O’Connor of Dow Electronic Materials addressed the use of photo BCB film for Advanced packaging.

The old R&H group has developed both solvent (14-P005) and aqueous (16P-008) developable BCB dry film with enhanced flexibility, elongation and fracture toughness.

Processing and properties are shown below:

dpw 1

 

dow 2

 

Chip level reliability testing is underway.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 288 Consolidation on the Conference Circuit: 2016 IMAPS Polymer Conf

By Dr. Phil Garrou, Contributing Editor

Conference Consolidation under IMAPS

Recently, consolidation has hit the conference circuit, much the same as it has hit the corporate world. The 2016 IMAPS Polymers Conference which we will discuss below focuses, as you might imagine, on the use of polymers in microelectronics. It has been a biennial conference sponsored 15X by DuPont and was held in Wilmington DE. It was acquired by IMAPS and for now continues to operate at the Wilmington location.

IMAPS has also acquired the RTI 3D ASIP Conference. As you may know, 3DASIP is the longest running 2.5 / 3DIC conference focused on commercialization and infrastructure. The IMAPS supported 2016 meeting will be held December 13-15th, at the Marriott San Francisco Airport Hotel in Burlingame, Ca. As in years past, all presentations will be invited.

Continuing in the technical direction that was started last year, 3D ASIP will grow its focus on not only 2.5 and 3D IC, but other competitive high density packaging technologies that are being developed. With the ending of the Ga Tech interposer conference they have asked Corning to join the polymer conference and provide a session on the status of this technology.

The US Technical Chair will be Alan Huffman from RTI, the European Chair will be Mark Scannell of Leti and the Asia Chair will be Mitsu Koyanagi of Tohoku Univ.

There will be two AM tutorials, plenary presentations to start off each day and (8) sessions structured and developed by 8 “topic leaders” who will develop their 3 or 4 paper sessions and serve as session chairs.

IMAPS 17th Symp on Polymers for Microelectronics.

Continuing in the Winterhaven DE site that has held these meeting for many hears, the conference was spearheaded by a 6 person steering committee and a 6 person advisory board.

Yole Developpement

Amandine Pizzagalli of Yole gave a nice presentation on the use of polymers in advanced packaging platforms. The following generic packaging slide first breaks down technology options into leadframe packages vs substrate based and non substrate based packages etc. Another conclusion from this slide which John Hunt made in a later talk was that ALL packages are fan out except wafer level packages.

yole 1

Their wafer count forecast shows that while fan out shows the strongest growth rate, FC based packaging is responsible for > 75% of all adv packaging wafer count through 2020.

yole 2

Yole’s 2015 marketing study shows that PI accounts for ~ 63% of dielectric usage in advanced packaging.

yole 3

ASE – Fan Out Packaging

In the fanout panel packaging session John Hunt of ASE made the point that while fan out today has taken the connotation of “eWLB” packaging, it truly has been around forever since all packaging except wafer level is fan out including all leadframe and substrate packaging. He showed the following chart for ASE fan out package offerings ad noted that ASE like many others were focusing on panel level processing to attempt to cut costs.

yole 4

 

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 287 SMIC Ups the Ante on Packaging; IMAPS DPC 2016 part 4; SiP, Sputtered Cu Shielding and Si TF Caps

By Dr. Phil Garrou, Contributing Editor

SMIC Ups Ownership in JCET

Following the lead of global foundry leader TSMC, SMIC, in two separate moves has put an additional $0.5B into JCET (Jiangsu Changjiang Electronics Technology), mainland China’s largest semiconductor packaging assembly and test business, uping their ownership position to $14.25% and making it the biggest shareholder in JCET. [link].

SMIC used a straight cash investment and it’s subsidiary SilTech Shanghai which agreed to sell to JCET its 19.61 per cent equity interest in semiconductor packaging and test services company Stats ChipPac in exchange for JCET shares. SilTech, JCET and the China IC Industry Investment Fund jointly acquired Stats ChipPac in 2014.

With TSMC and SMIC moving into packaging (as IFTLE has predicted for years) it will be interesting to watch for the response from GlobalFoundries and or UMC.

Continuing our look at the IMAPS Device packaging Workshop

ASE – SiP

Bill Chen’s plenary presentation on SiP contained a nice section on WLP (or WLCSP as it used to be called). IFTLE has recently pointed out that WLP should end up being a very important package for IoT which need very small forma factor and very low cost. [ see IFTLE 268 IMAPS 2015 Part 1: A Comeback for WLP in IoT]

I admit to being very partial to the WLP package since I spent many years in the 1990s working with FCT and Unitive as they created the package and made it an industry standard.

Chen points out that the WLCSP of the 1990s paved the way for may other WL packages as shown below.

ASE 1

Based on Yole data, Chen estimates that todays leading edge smart phones contain ~ 35% WLCSP.

As technology developed to apply WLP to larger and larger die more applications came into reach and more I/O ae available at the same pitch as shown below.

ASE 2

IPDIA

Bunel of IPDIA discussed their “Low profile flip-type or embedded Silicon Capacitors in high speed decoupling and broadband filtering”. Communication applications are requiring compact capacitors with large capacitance and low impedance.

IPDIA silicon capacitor technology is based on the structure shown below which can be built in thin film technology with very low profile.

Ipdia 1

It is compared to a std MCC (multilayer ceramic) cap below.

ipdia 2

The silicon caps are thinner and have a smaller footprint than standard MLCC caps.

The main take away of this paper is that the insertion loss at frequencies above 15GHz is dependent on the environment and the mounting parameters. The comparison between the Silicon capacitor and the MLCC shows that on top of the performances required for the UWBB capacitors, the Silicon capacitors offer a combined solution of low profile, high capacitance and low ESR/ESL to meet the requirements in decoupling applications.

Amkor

Amkor discussed sputtered copper vs metal can shielding for cell phone components. They contend sputtering is a lower cost smaller footprint solution.

amkor

 

The process flow is shown below.

amkor 2

 

Excellent shielding effectiveness is achieved, mostly above 30 dB, up to12 GHz for far field and up to 6 GHz for near field, and low frequency from10 MHz-100 MHz. Amkor recommends 3 μm sputtering copper solution for best shielding performance and lowest cost.

Hope to see a lot of you in a few week at the ECTC conference in Las Vegas.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 286 IME Forum; IMAPS DPC 2016 part 3: IMEC Assembly Challenges for 2.5/3D

By Dr. Phil Garrou, Contributing Editor

IME Forum

In late March IME held an industry forum in Singapore to discuss “High Density WLFO WLP for next gen mobile 2.5D/5G Systems” Of special interest was their process flow for PoP package constructed from a FOWLP as shown below. This is a chips last FOWLP assembly with access to the top surface by TMV (through mold vias) and subsequent formation of stacked memory as the upper PoP level.

IME

Continuing our look at the 2016 IMAPS Device Packaging Workshop

IMEC – Assembly and Packaging Challenges for 2.5/3D

IMEC addressed assembly and packaging challenges for 2.5/3D. One the main changes we will see moving from 50um to 10um micro bump pitch will be the move from solder ball reflow to thermo-compression bonding.

imec 1

This will require the use of pre applied underfill to insure:

  • Mechanical connection (adhesion)
  • Protection of joints and chips during operation

Two types of pre-applied underfill are available:

  • No-flow underfill (NUF) – dispensed on bottom die
  • Wafer-level underfill (WLUF) – applied on top wafer

imec 2

If the TCB is done to quickly, heavy voiding results. A comparison of NUF and WLUF (which IFTLE sometimes calls WUF) is given below.

imec 3

The process flows for NUF and WUF are compared below.

imec 4

Amkor moves SWIFT and SLIM into Mass Production

Anyone questioning whether Amkor would move their high density TSV-less packaging technologies SWIFT and SLIM into HVM should question no more following their announcement that they have teamed with Cadence and will be releasing PDK for these technologies.[link]

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…