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IFTLE 234 IBM to Share Technology with China; More on Apple A9 Business; Fujitsu puts liquid Cooling in Smartphones

By Dr. Phil Garrou, Contributing Editor

IBM to share technology with China

In IFTLE 222, we discussed the recent announcement by China that they are becoming a major predator of the IC business. This is exemplified by recent acquisitions of STATSChipPAC (see IFTLE 222)(link),  FlipChip Int (FCI) (link) and Omnivision.

Now, according to Reuters, IBM Corp has announced that they will share technology with Chinese firms and will actively help build China’s industry. “IBM’s new approach allows Chinese companies to build everything from semiconductor chips and servers based on IBM architecture, to the software that runs on those machines”.

Apple A9 Orders Shift to TSMC

EE Times reports that TSMC will take more orders for Apple’s A9 processor (for the iPhone 6S) at the expense of Samsung, which reportedly is having yield problems. Apple originally gave Samsung about 80% of the A9 orders and the rest to TSMC. Now reports are that TSMC will get about 70% of Apple’s overall business starting in the third quarter of 2015 (see previous discussions in IFTLE 228).

There are reports that TSMC’s 16nm yield is better than Samsung’s 14nm yield (both using finfet technology).

This will be the first time that Apple has split the foundry service of the same processor at two suppliers. Equipment and materials will likely see rush orders from TSMC to meet demand. TSMC will also need to work more closely with OSATS such as ASE and SPIL for the full solution.

Because of the reported overheating issue in Qualcomm’s 20nm Snapdragon being made at TSMC,  Qualcomm is reportedly cutting its 20nm orders at TSMC and is accelerating its transition to 14/16nm at Samsung. Since Qualcomm accounts for 40% to 50% of TSMC’s 20nm demand, this will have a significant impact on TSMC revenue.

This has also caused issues at Sony who recently reported overheating Issues were stalling release of Sony’s Xperia Z4 smartphone (link).

“The Xperia Z4 is expected to be an extremely thin smartphone; thus the need for successful heat dissipation is important. The Xperia Z4 tablet is also powered by the Snapdragon 810; however, there is more surface area for heat dissipation on this 10-inch tablet than the small smartphone”.

Fujitsu Puts Liquid Cooling in Smartphones

Many manufacturers struggle with removal of heat from chips in phones and tablets. Unless that heat is removed, hotspots can form when devices are in use, causing thermal damage.

Engineers at Fujitsu have now developed a liquid cooling solution for smartphone devices (link).

Fujitsu has built a microscale heat pipe, less than 1mm thick. It’s comprised of two parts — the first is an evaporator that absorbs heat from a heat source and the second is a condenser that dissipates the heat away, with the two parts connected by pipes.

Fujitsu

 

Capillary action to drive flow. Inside Fujitsu’s device, the tubes are filled with pores that are just the right size to get fluid to circulate. Fujitsu reports that “Compared to the previous thin heat pipes and material of highly thermal conductive sheets, this new device allows for approximately five times greater heat transfer,” The technology allows CPUs and other parts to function at low temperatures while preventing heat concentration within localized areas. Fujitsu reports the technology should make its way into smartphones around 2017. Fujitsu adds that it’s also looking into potential applications in communications infrastructure, medical equipment, and wearable devices.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 233 Package Shrinkage Continues with ASE FOCLP

By Dr. Phil Garrou, Contributing Editor

The IMAPS Device Packaging Conference in Ft McDowell, AZ is an annual meeting where we have grown to expect major new technical introductions from the OSAT and materials community. This year’s meeting was no exception with key new package introductions from Amkor and ASE. This week we’ll look at the ASE FOCLP (fan out chips last package) and next week we’ll take a look at the new offerings from Amkor.

ASE FOCLP

We’re all aware that miniaturization has driven our industry  for decades until we finally reached the WLCSP (wafer level chip size package) where the size of the package became the size of the chip. At this point we all looked at the vertical dimension and became focused on stacking chips (to gain x,y area) or thinning chips and package to produce thinner lap tops and or  cell phones.

John Hunt offered this interesting slide showing the thinning of the Apple I phone plotted against the increase in use of WLPs.

fig 1

 

As chips have been shrunk to the 22nm node and beyond there is not a lot of room under the chips for I/O, thus the focus on fan out WLP (FOWLP).  ASE addressed the question, “How do we reduce the cost structure in fan out packaging ?”

By moving to a totally laminate based solution they have been able to combine coreless laminate substrate, copper pillar bumping and molded underfill to produce a low cost ultra thin ( < 375um) package.

fig 2

 

  • Chip Last vs Chip First for Higher Assembly yields
  • Fine Pitch bumping direct on die pad without RDL
  • Thicker Copper (15-50µm)allows higher current
  • Thin Package < 375µm

The single layer coreless substrate utilizes embedded traces and pads for fine feature resolution.

fig 3

 

Fabrication is done on a 510mm x 410mm panel which is assembled in strip form similar to what is done for BGAs. No fan out wafer fab investment is required.

fig 4

 

FOCLP can be identical in size, thickness, foot print, trace layout and performance as FOWLP while using only lower cost  laminate packaging technologies. Electrical Simulation shows comparable performance.

fig 5

 

Multiple actives and passives can easily be included in FOCLPs using existing volume production equipment. Thermal Heat spreaders can be included in molded FOCLPs. Thick Copper can be used for high current and/or thermal transfer. Standard packages such as SiP and PoP will be transferrable to WLCLP.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 232 SEMI 3D Summit Part 3: Besi, IMEC, AMS, Asahi Glass and Yole Developpement

By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the Semi 3D Summit in Grenoble we’ll look at the presentations of Besi, IMEC, AMS, Asahi Glass and Yole.

BESI – 3D Stacking with Thermocompression Bonding (TCB)

Hugo Pristauz of Besi updated the attendees on the advances in 3D Stacking with thermocompression bonding (TCB).

Thermocompression bonding which requires both heat and pressure is contrasted to mass reflow bonding (also simply called solder reflow) where no pressure as to be exerted. The latter is a high productivity process whereas the former is known for slower throughput.  It is usually accepted that TCB is required at pitches less than 40um.

TCB may be done with capillary underfill or more recently with NCP (substrate side) or NCF (chip side) as shown below.

Besi 1

 

Besi indicates that TCB is being used for Micron HMC production.

IMEC – 3D Technology Depends on Application

Eric Beyne of IMEC examined mapping 3D technology to 3D applications.

For instance,

–        Logic + wide I/O density: high interconnect density

–        Mixed signal/MEMS : lower interconnect density

Interconnect technology options include:

IMEC 1

 

A high bandwidth interconnect bus requires a ref/shielding plane for signal integrity and reduced cross-talk which would mean:

IMEC  2

 

Choices will depend on the interconnect density that is needed.

[added note from IFTLE] All interposer products announced thus far are still requiring the high density dual damascene interconnects.

AMS AG – Sensors for Smart Systems

Martin Schrems of AMS AG reported on “3D Sensor Integration for Smart Systems”. Certainly we would all agree that sensors are a major part of what will make smart systems smart. AMS offers the following as a standard block diagram for a smart system:

AMS 1

 

For instance, indoor air quality sensors measures standard  temperature, humidity and carbon dioxide (CO2) levels as well as the amount of volatile organic compounds (VOCs), such as smoke, cooking odors, bio-effluence (body odor), outdoor pollutants or human activities. While temperature and humidity are easy to measure, sensors for measuring CO2 (IR absorption) can be expensive.  VOC detection uses micromachined metal oxide semiconductor (MOS) technology to detect a broad range of VOCs while correlating directly with CO2 levels in the room.

AMS 2

 

The motivation to move to 2.5D packaging is the size reduction advantages.  At this point these systems are still at the R&D conceptual stage.

Asahi Glass – Update on glass for 2.5D Interposers

Asahi Glass is one of the glass producers putting their money where their mouth is in terms of funding R&D and development into the use of glass as a 2.5D interposer material. We have discussed in length their investment into Triton, a start-up looking at manufacturing  commercial glass interposers [ see IFTLE 141 “IFTLE 141 100GB Wide IO memory; AGC Glass Interposers; Nvidia talks stacked memory”]

At the 3D Summit in Grenoble Shin Takahashi of Asahi Glass reviewed the status and challenges of glass interposer activity. Below we can see their listed technical and manufacturing challenges.

AG 1

 

With thin silicon (100um) they are now able to create 25-30um tapered TGV (through glass vias) on a 50um pitch.

AG 2

 

For via filling, they are looking at both conformal copper plating and copper paste filling where their capabilities are currently 50um dia. on 130um pitch.

Reports on panel based processing, which is viewed as the primary means of lowering the cost structure on interposers, is seen as lacking infrastructure.

Yole Developpement – Wafer Level continues market penetration

During her overview of the industries packaging efforts, Rozalia Beica of Yole indicated that wafer level processing will this year account for 20% of all semiconductor IC wafers.

Yole

 

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 231 SEMI 3D Summit : The Future of Assembly and Test

By Dr. Phil Garrou, Contributing Editor

Continuing our look at presentations from the Grenoble SEMI 3D Summit which took place in January lets look at an interesting presentation by ATREG consultants on the future of Assembly & Test.

ATREG – The Future of Assembly & Test

Barnett Silver from ATREG Inc. discussed their thoughts on “The Future of Assembly and Test…” They base their predictions on the following themes which are in alignment with what you all have been reading in IFTLE for the past 230 blogs.

  • Packaging and test is an enormously important component of semiconductor manufacturing.
  • Technology and economics are driving convergence / consolidation between front-end and back-end manufacturing.
  • Prior concepts inhibiting front-end / back-end convergence / consolidation are fading
  • In the future the packaging landscape will look different from today.

They proposed the following sequence time line for the evolution of the packaging and test industry  : stage 1 – fully vertically integrated companies did their own chip design, manufacture, test and packaging; stage 2 – back end packaging and test began to separate into assembly companies ; stage 3 – foundries and fabless companies created a period of specialization and separation of tasks; stage 4 –(which ATREG indicates starts around 2010) they see  re-integration.

IFTLE sees it slightly differently with convergence of package and test skills into the foundries but not a reintegration for fabless or IDMs.

ATREG 1

 

Of the total industry COGS of $205 billion, ~25% (or $51 billion) is spent on assembly & test.

ATREG 2

 

Five firms dominate outsourced packaging, accounting for over half of the total OSAT industry and 25% of the total back-end spend of $51B.

ATREG 3

 

It has normally been assumed that since foundry margins are significantly higher than OSAT margins, traditional OSAT business would be unattractive to foundries. With a few exceptions, foundry / OSAT acquisitions would be dilutive to foundry’s gross margins yet foundries show interest in aspects of A&T.

ATREG 4

 

This perceived dichotomy can be understood by looking at the difference between packaging margin on standard chips vs advanced chips. In fact, over the last five years, OSAT firms have delivered better returns for investors than foundries partially because assembly houses spend far less per year on capex than foundries [ i.e. 18% vss35% in 2013].

As prostheliytized by IFTLE,  the economics of the latest node chip fabs are limiting those who can move forward with such expendatrures, and products are being customized  by the packaging that is being chosen. It is quite likely that this will be  where margin will come from in the future. 

Customers will be choosing between a turnkey model controlled by the foundry (proposed by TSMC) or a collaborative model where the foundry and the OSAT remain as separate entities (proposed by GlobalFoundries).

ATREG 6

 

Among other things ATREG concludes that:

• Foundries, OSATs, and IDMs will fight over the $51 billion A&T market.

–        IFTLE agrees that foundries will battle with OSSATS but is not yet convinced that IDM are getting back into the fray.

• As technology drivers change, there will be significantly more focus on the back-end industry.

–        IFTLE absolutely agrees.

• There will be re-integration and convergence between front-end and back-end.

–        IFTLE agrees through both convergence (which some now call “mid end”) and consolidation.

•Disruption in the OSAT industry will increase.

–        IFTLE agrees again through convergence and consolidation.

• IDMs / fabless may invest in advanced packaging

–        IFTLE is not convinced.

In conclusion, although IFTLE agrees with ATREG on most point (and has been documenting these facts for many years) we are not convinced that IDMs and the fabless are looking to get back into the packaging business.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 230 SEMI 3D Summit – Grenoble: Oerlikon, ST Micro, Qualcomm

By Dr. Phil Garrou, Contributing Editor

In the next two weeks, we’ll take a look at some of the more interesting presentations from the SEMI 3DIC Summit in Grenoble last month.

Oerlikon – Capabilities of Highly Ionized Sputtering (HIS)

Juergen Weichart of Oerlikon Systems discussed the capabilities of highly ionized sputtering.

It has been known for many years that filling of high AR TSV required ionized plasmas as shown below.

Oerlikon 1

 

Cross sectional analysis shows that HIS which deposits 462um of Ti adhesion/barrier layer on the Si top surface and 17um in the bottom of the TSV only results in a 10-12nm coating on the TSV sidewalls.

oerlikon 2

 

Deposition rates, step coverage deposit resistivity and stress for both TSV and RDL processes are compared in the table below.

oerlikon 3

 

ST Micro – Interposers for Networking ASICS

Georg Kimmich of ST Micro gave a presentation on Network packaging trends.

Below we see the current typical packaging for a networking ASIC chip

ST 1

 

Higher I/O density and memory bandwidth, required for future Networking ASIC chips, can be handled by use of 2.5D packaging with high density interposers. Both Hynix high bandwidth memory (HBM) and Micron Hybrid  memory cube (HMC) memories are suitable for such networking applications.

Memory can be inserted into the packages with the following silicon and laminate interposer options.

ST 2

 

While the Hybrid Organic Substrate solutions (2.1D) are the most promising in terms of cost and supply chain simplicity technologically they are less advanced.

They conclude that the very high cost of ASIC, HBM and high density interposers results in very high pressure to achieve high assembly yield. The supply chain for HBM integration are ready for prototyping now and volume production in the H2 2016 time frame.

Qualcomm – Partitioning of Large Die

Mustafa Badaroglu of Qualcomm addressed the topic of “2.5 and 3D Integration: Where we have been, where we are now and where we need to go with much the same presentation that Riko Radojcic gave at the Ga Tech Interposer Workshop in November.

They conclude that large dies can be economically partitioned into smaller dies and repackaged with several options including (1) low cost SI interposer with no substrate, (2) fan out WLP or (high density organic interposer as shown below.

qualcomm 1

 

  • Split die requirement: 2um L/S between die

Required to support ~ 2000D2D connections

  • PoP memory requirement: PoP via + RDL

Required to leverage standard PoP package

  • Si form factor : two ~12mm x ~6mm die
  • Electrical Requirement: 3LM interconnect

Required for signal, PoP and PDN/SI needs

  • Package = 15mm x 15mm x <1mm

Required to meet the usual SP constraints

  • Cost requirement < 1c/mm2 in HVM

 

SoC large die partitioning challenges

–What function goes on which die

–Balance of die areas

–Power-performance trade offs

 

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 229 Semi Industry Strategy Symp 2015

By Dr. Phil Garrou, Contributing Editor

The SEMI ISS (Industry Strategy Symposium) brings together industry leaders to share their opinions on where our industry is going. The US meeting is held each January in Half Moon Bay, CA.

The new darling of the microelectronics industry is obviously the Internet of Things (IoT). Many of the speakers focused on this topic though there was far more predicting than there was hard data. The thing that we know least about is always promoted as the next savior…correct ?

VLSI Research

Andrea Lati VLSI research showed an interesting slide on their opinion of what went right and what went wrong in 2014.VLSI 1

Capex continues to be concentrated in the big 3 with Intel, Samsung, Global Foundries and TSMC responsible for 72% of capex expenditures.

VLSI 2

 

Assembly and Test capex remains a fraction of IC expenditures:

VLSI 3

 

Assembly equipment sales are not expected to get back to 2010 levels till 2018.

VLSI 4

 

Intel

Frank Jones, Vice President, GM of the internet of things group in Intel gave their perspective on IoT.

This is the first time I have seen anyone break out the predicted chip requirements by number of units and price. My presumption has always been that IoT would require super low cost technologies. Make of these projections what you will.

Intel 1

 

Broadcom

Scott McGregor CEO of Broadcom concurred with the IFTLE oft quoted theme that 28nm may be the sweet spot in terms of scaling lowering the cost per transistor.

Broadcom 1

 

IFTLE had been quoting the NRE costs of design at the 22nm node as $150MM. We now see that the projection for design at 16nm is up to $350MM making it even less accessible to most electronic device manufacturers.

Broadcom 2

 

An interesting conclusion that Broadcom has reached is that cost reductions in the future will result from better design engineering rather than better process engineering.

Samsung

Jim Elliot, VP of Samsung memory, pointed out that while cell phoned has just about saturated the market globally, smartphones are only in the hands of 30% of the world’s population.

Samsung 1

 

I especially liked their photo of a cargo plane being required to transport a 3.75 Mb IBM disk drive in 1956.

Samsung 2

 

Linx

Mike Corbet, Managing Partner for Linx examined the wafer fab materials (ALD, CMP, CVD, ECD, Litho, PVD, SOD and Process Chemicals) market. The following plot shows that litho materials will dominate logic wafer fab materials cost as we move forward.

LINX 1

 

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 228 Samsung goings on

By Dr. Phil Garrou, Contributing Editor

Let’s take a break from the conference circuit to take a look at some significant Samsung goings on in the industry.

Battling over Apple

Not since the Garden of Eden have we seen so much activity generated by an apple?

Recall, Apple signed up TSMC back in 2013 to produce its future A series processor chips while undergoing legal battles with Samsung their current provider. However, Apple has not been unable to completely disengage from Samsung. Both TSMC and Samsung produced the 22nm A8 processors for the iPhone 6  though TSMC had the majority of the order.

Now, according to South Korea’s Maeil Business Newspaper, Apple has turned back to Samsung to manufacture its A9 chip. Reports are that Samsung will get 75% of the chip production for the next iPhone [link].

Samsung reportedly began production of Apple’s A9 in their Austin TX plant using the 14nm FinFET technology. Samsung has 14nm FinFET production capability in both Austin, and Giheung, Korea, but will produce A9 only in Austin initially. IFTLE guesses that this “technically” makes the chips “made in the USA.”

Rumors of Samsung dropping Qualcomm Snapdragon in next Galaxy phone

228 Exnos vs snapdragon

 

Samsung also is putting significant pressure on Qualcomm with the pervasive rumors that Samsung will use its own microprocessors in the next version of the Galaxy S smartphone. Both Qualcomm and Samsung have declined comment.

Citing “people with direct knowledge of the matter,” Bloomberg has reported that that Samsung, “…tested the new version of Qualcomm’s Snapdragon chip, known as the 810, and decided not to use it”. Qualcomm’s Snapdragon processors, combined with its cellular baseband chips, have dominated the market for smartphones in recent years.

Qualcomm has faced rumors in recent months about potential overheating in the 810. While it is believed that Qualcomm has solved the 810’s overheating problems, the issue has put Snapdragon 810 production a few months behind schedule [link].

Qualcomm has publically confirmed that it will no longer supply chips for a “large customer’s flagship device”. While the company did not confirm that this was Samsung, the firm in question is big enough for Qualcomm to lower its 2015 outlook in its first quarter fiscal financial results [link].

It remains possible that Qualcomm will convince Samsung that they have fixed the overheating problem and be reinserted into the Samsung phone.

Samsung mass producing high-density ePoP memory for Smartphones

Samsung has announced that the company will be mass producing the extremely thin ePoP (embedded package on package) memory, a single memory package consisting of 3GB LPDDR3 DRAM, 32GB eMMC and a controller for use in high-end smartphones [link].

The 3GB LPDDR3 mobile DRAM inside the ePoP operates at an I/O data transfer rate of 1,866Mb/s, with a 64-bit I/O bandwidth.

228 samsung ePoP

 

Because of its “thinness and special heat-resistant properties,” Samsung claims that the smartphone ePoP does not need any space beyond the 225 square millimeters (15 x 15mm x 1.4mm high) taken up by the mobile application processor. A conventional PoP (also 15 by 15mm), consisting of the mobile processor and DRAM, along with a separate eMMC (11.5mm by 13mm multimedia card) package, takes up 374.5 square millimeters. Replacing that set-up with a Samsung ePoP reportedly decreases the total area used by approx. 40%.

Samsung is basically stacking all the memory, both RAM and NAND, on a single ePoP module that’s then positioned on top of the processor, rather than beside it as shown below.

228 Samsung ePoP 2

 

The use of such ePoP chips seems to be a likely choice for the upcoming Galaxy S6. It is intended to be used in mobile devices packing 64-bit processors and 3GB of RAM which is  what’s rumored to be spec’ed in the Galaxy S6 and other top mobile devices later this year.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE.

IFTLE 227 Yole’s Beica examines Internet of Things at RTI 3D ASIP

By Dr. Phil Garrou, Contributing Editor

Closing our look at presentations from the RTI ASIP Conference lets check out what Rozalia Beica had to say about the latest tech buzz word “the Internet of Things.”

Yole – Internet of Things

Rozalia Beica is defining IoT as “Objects becoming interactive information sources…..while the internet connects people…..IoT will primarily connect machines.”

Sensing applications include:

yole 2-1

 

Yole predicts that the main applications of IoT sensor devices will be:

yole 2-2

 

Yole lists the following as IoT challenges:

yole 2-3

 

Invensas

During Sitaram Arkalgud’s presentation on assembly challenges in 2.5 and 3DIC, he addressed the issue of unbalanced interposer warpage. As we see in the table below, backside RDL dielectric thickness and balance can have significant impact on substrate warpage.

Invensas 1

 

What’s going on with TSMC and  Qualcomm

From our friends at Digitimes comes rumors that Qualcomm is having problems on multiple fronts

Taiwan Semiconductor Manufacturing Company (TSMC) will reportedly be facing  tough questions at its upcoming investors conference to be held on January 15…. TSMC chairman Morris Chang is expected to host the January 15 conference

TSMC is expected to address speculation printed in the Chinese-language Liberty Times on January 14, that Qualcomm has put a halt on trial production of 16nm FinFET at TSMC. According to a Chinese-language Economic Daily News (EDN) report, citing sources in TSMC’s supply chain, TSMC has postponed the installation of its 16nm production lines to the 2nd half 2015 instead of the 1st half as originally planned,.

Further rumors indicate that Qualcomm’s Snapdragon 810, the first  20nm Snapdragon chip manufactured by TSMC, is suffering from overheating issues. The overheating issue is likely to cause delay of Snapdragon 810 shipments, the Liberty Times reported. The chips are scheduled to be shipped starting March.

TSMC also reportedly plans to temporarily reduce the production of its 20nm process by 20%.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 226 RTI ASIP Part 2: 3D Memory, Heterogeneous Integration, High Density Laminates, Embedded films

By Dr. Phil Garrou, Contributing Editor

Let’s continue our end of year look at presentations at the RTI ASIP Conference.

Yole Developpement

During my 2014 market Update presentation 2.5 / 3DIC for Yole Developpment, we looked at the timeline for introduction of the various new memory architectures as shown below:

Yole 1

 

Another popular slide discussed cost vs density for current available and proposed interposer solutions. While silicon clearly achieves the highest density it is at the highest cost. Laminate originates from a position of low cost, but to achieve higher density (both L/S and via dia/pad size) will processing and equipment costs be able to maintain low costs? Is large area processing or panel processing a credible concept for high density packaging? Glass while intriguing has no standardization of ground rules and no announced fabrication facilities that can supply large volume orders.

While it is clear that 1-10um L/S is a density sweet spot, it is not clear what technology will end up delivering a reliable technology at the lowest cost.

Yole 2

 

Fraunhoffer IIS / Siemens

Schneider of Fraunhoffer ISS and Siemens reported on heterogeneous integration for Sensor Systems.

One key point is that there currently is no accepted definition for heterogenous integration and it includes:

– different devise with different functions

– dies manufactured from different substrate materials

– dies manufactured with different technologies.

For example:

Fraunhoffer IIS 1

 

Unimicron

 We last discussed Unimicron’s thoughts on producing high density laminate with 2/2 (L/S) in IFTLE 223. At the RTI 3DASIP DC Hu detailed further thoughts on technologies to achieve silicon like densities on laminate substrates.

Target Line Width

  • Copper trace, 2013:10/10um, 2014; 8/8, 2015: 5/5, 2016: 3/3or 2/2
  • Target via size, 2013: 60um, 2014: 50um, 2015: 40um, , 2016: 30um

8/8 Lines and maybe even 5/5 can be achieved by todays lamination technology

But below 5/5um, new methods are under consideration

–  Semi additive

–  line first by embedding

– line last by embedding

–  Copper Damascening

Photo Process

– Exposure tool, Stepper, LDI, but need large panel processing

– Liquid photo resist may be required.

–  Slit coating, Spin coating of PR

Planarizaton

– Large Area CMP may be needed.

Fine Lines on Large Panel Glass Substrate

– 3/3um L/S with thickness of 5um Cu patterns can be realized on 508x508mm glass panel.

unimicron 1

 

Line Embedded Line Last Technology

unimicron 2

Line Embedded Line First Technology

unimicron 3

New Structure – embedded high density film

– High Density Film with three metal layers can be as thin as 40 um.

–  Super thin package.

–  Low Cost

unimicron 4

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 225 IEEE 3DIC – Cork: The Thermal Impact of TSVs – reexamined; Parylene: an IFTLE alternative opinion

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the key presentations at the 2014 IEEE 3DIC Conference recently in Cork, Ireland.

Global Integration Institute (GINTI) –    µ-XRD for Thermo-mechanical Stress Measurement

Copper-Through-Silicon-Via (Cu-TSV) is increasingly used for two reasons: (i) the very low resistivity of Cu as compared to that of the other TSV-fill materials that significantly reduces the (RC) delay, and (ii) the ease of Cu-electroplating to fill the TSV without any voids which enhances the production throughput.

Cu-TSV also suffers from some of the critical reliability issues such as diffusion of Cu in to active Si from back-metal contamination and the thermo-mechanical stress caused by Cu-TSV pumping.

Parasitic capacitance is approximately proportional to the size and length of the TSV. Therefore, in order to reduce the parasitic capacitance due to Cu-TSVs, one has to reduce the TSV size and length. To improve the yield of Cu-TSVs the aspect-ratio of the TSV has to be kept as small as possible. This forces one to reduce the thickness of Si thickness that leads to decrease in the mechanical strength of the 3D-LSI. The thermo-mechanical stress in 3D-LSI is widely measured using Raman spectroscopy.

In the future 3D-LSI will have TSV dia from few um down to sub um, one will no longer be able to use Raman to be used as a stress metrology tool. Micro X-ray diffraction (u-XRD) uses one order smaller diameter probe, as small as 200nm.

Ginti has studied stress values deduced from u-XRD data from LSI samples containing Cu-TSVs, whose diameter varies from 2 to 20um. It was observed that the TSV diameter has huge impact on the magnitude of resultant thermo-mechanical stress. The 20um-width Cu-TSV has induced more than -1500 MPa of stress in the vicinal Si, while the 2um-width Cu-TSV induced less than -10 MPa of compressive stress in the surrounding Si. Therefore by decreasing the TSV diameter, one can virtually eliminate the thermo-mechanical stress induced by TSV.

CEA Leti / ST Micro  – Thermal Performance of 3DICs 

Leti and ST Micro presented two papers on the thermal performance of 3DICs.

3DICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology.

There are four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs.

Heat dissipation in small hotspots is primarily diffused through the high thermal conductive silicon substrate and spreads in a semi-spherical direction, rapidly decreasing the heat density and lowering the peak temperature. In case of thinned silicon dies in a 3D stack, the inter-die interface layer acts as a thermal barrier due to its poor thermal properties, forcing the heat to spread laterally in the silicon substrate and thus resulting in a temperature distribution which approximates a cylindrical shape.

Thinned silicon dies present reduced lateral heat spreading capacity while poorly conductive adhesive materials used to bond dies together contribute to increase the vertical thermal resistance.

An increase in power density may come from higher power dissipation and/or from a reduction of the chip footprint. It means either more power needs to be removed from the same package or that the same power dissipation has to go through a reduced chip footprint. While chip footprint reduction is one of the advantages of 3D integration, it usually leads to higher temperatures for the same amount of energy dissipation when compared to single-die implementations.

Leti shows that inserting TSVs as thermal vias is of limited value. They contend that it is more important to reduce the thermal resistance between the stacked silicon dies which is due to  poor thermally conductive layers such as  BEOL metallization and underfill.

Thinned dies can present a severe thermal impediment especially to chips with hot spots. Thinned dies present high lateral thermal resistances thus forcing the heat to go through the underfill layer to the next die, which acts as a heat spreader reducing the hotspot temperature. Consequently, the thinner the die the more important is the thermal coupling between dies in case of hotspot heat dissipation.

The use of “thermal TSVs” for thermal mitigation has been routinely reported in the literature. Several thermal-aware physical optimization techniques can be found in the literature which rely on simplistic thermal models where the TSV is treated as a vertical lumped thermal resistor with thermal conductivity calculated according to its diameter and length. Such thermal models ignore the lateral heat transfer and the impact of the thin Si02 layer, which surrounds each TSV and thermally isolates TSVs from silicon substrate. The poor thermal conductivity properties of the SiO2, dominate the thermal impact of the TSVs in case of hotspot dissipation. Thus while having TSVs in the silicon substrate increases the equivalent vertical thermal conductivity at the same time it causes a lateral thermal blockage effect, especially for fine TSV pitches.

The thermal test chip is composed of two stacked dies connected through TSVs in the bottom die and μ-pillars (μ- bumps) in a face-to-back stacking configuration. Large FC Cu-pillars (bumps) are used to connect the bottom die to a BGA substrate. Gaps between layers are filled with underfill material for mechanical strength purposes.

leti 1

 

The SiO2 layer around each TSV leads to an increase of the hotspot temperature compared to the case without TSVs (+1.9 °C). Contrary to the common expectations, TSVs have a negative thermal impact on the hotspot temperature.

 

Increasing the TSV density increases the vertical thermal conductivity as well as the lateral thermal blockage effect. Splitting large TSVs into smaller ones, as suggested in [4] for instance, increases the ratio of the SiO2 layer thickness to the TSV diameter and hence increases also the lateral thermal blockage effect. Considering TSV technologies with very fine pitch, where this ratio is typically 1:10, also lead to TSV arrays with higher lateral thermal blockage effect.

 

An explorative study including multiple TSV array configurations and power dissipation profiles shows that, contrary to the common belief, TSVs are not effective for thermal mitigation in current TSV technologies and may even provoke exacerbated hotspots. Although TSVs help to convey heat vertically, the lateral thermal blockage effect prevails over any thermal benefit arising from TSVs in the case of hotspots. In the reported investigation, TSVs placed around a small hotspot may result in peak temperatures worsened by up to 15%.

 

Parylene HT for 3DIC – An Alternative Opinion

 

Researchers at AIST reported at Cork on Parylene HT’s use as an insulator layer for copper TSV. While it certainly is true that “the capacitance of parylene liner is much lower than that of SiO2 liner. This provides benefit in minimizing the signal delay, lowering power consumption, and reducing cross-talk between neighboring paths.” No consideration was given to the mechanical properties of Parylene HT.

HTParylene HT aka Parylene AF4, aka Parylene F has been reported in the literature for more than 35 years.  It was available commercially in the late 1990’s as Novellus AF4 when it  was thoroughly screened as a potential ILD Low=K replacement material. It was never implemented as a Low-K ILD for many reasons amongst which was the reactivity of the F with the Ta barrier layers in dual damascene structures.

Parylene (though not the HT product) has been examined as an insulator for 3D TSV  by the RTI group working on the DARPA VISA program since 2006 and by IMEC since 2008. The use of Parylene as a TSV insulation dielectric has been detailed in Chapter 7 of Volume 1 of the “Handbook of 3D Integration.”

[Garrou, Bower And Ramm Eds, Wiley VCH 2008]

While the Parylene family of products has found a nice niche as a protective coating for PC boards and medical components, it is NOT known for its superior mechanical properties.  While Parylene HT reportedly has superior thermal properties (vs other Parylenes) it’s mechanical properties remain poor as shown below.

HT properties

So the tensile strength of Parylene HT, is ~ 50 MPa and the elongation is 2%. The yield strength, i.e. the stress at which it begins to deform plastically is 35 MPa. These are not properties that I would want encapsulating a copper TSV which is known to undergo “copper pumping” and is known to exert so much stress that it cracks SiO2 liners as it expands.

Suffice it to say that I would examine mechanical reliability tests very carefully before implementing such materials into a 3DIC process flow.

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