Author Archives: sdavis

IFTLE 334 On High Performance Computing, Chiplets and Interposers

By Dr. Phil Garrou, Contributing Editor

Most of us packaging focused technologists do not traditionally follow what’s being presented at the IEEE High Performance Computing Architectures Conference (HPCA)…but that’s why you follow IFTLE…i.e. to find such material. This year’s conference was held in Austin, TX the first week of Feb. What I want to focus on is the presentation by AMD on “Design and Analysis of an APU for Exascale Computing.”

If some of these concepts look familiar, check out IFTLE 323, “The New DARPA Program “CHIPS.”

The need for ever more computational power continues to grow and exaflop (1018 ) capabilities may soon become necessary. This paper presents the AMD vision for an exascale node architecture for exascale computing including low-power and high-performance CPU cores, integrated energy-efficient GPU units, in-package high-bandwidth 3D memory, die-stacking and chiplet technologies, and advanced memory systems.

Two of the building blocks for this exascale node architecture are (1) it’s chiplet-based approach that decouples performance-critical processing components like CPUs and GPUs from components that do not scale well with technology (e.g., analog components), allowing fabrication in individually optimized

process technologies for cost reduction and design reuse in other market segments and (2) the use of in-package 3D memory, which is stacked directly above high-bandwidth-consuming GPUs. 

The exascale heterogeneous processor (shown below) is an accelerated processing unit (APU) consisting of CPU and GPU compute integrated with in-package 3D DRAM. The overall structure makes use of a modular “chiplet” design, with the chiplets 3D-stacked on other “active interposer” chips. “The use of advanced packaging technologies enables a large amount of computational and memory resources to be located in a single package”. The exascale targets for memory bandwidth and energy efficiency are incredibly challenging for off-package memory solutions. Thus AMD proposes to integrate 3D-stacked DRAM into the EHP package.

AMD -1

In the center of the EHP are two CPU clusters, each consisting of four multi-core CPU chiplets stacked on an active interposer base die. On either side of the CPU clusters are a total of four GPU clusters, each consisting of two GPU chiplets on a respective active interposer. Upon each GPU chiplet is a 3D stack of DRAM. The DRAM is directly stacked on the GPU chiplets to maximize bandwidth. The interposers underneath the chiplets provide interconnection between the chiplets along with other functions such as external I/O interfaces, power distribution and system management. Interposers maintain high-bandwidth connectivity among themselves by utilizing wide, short distance, point-to-point paths.


The performance requirements require a large amount of compute and memory to be integrated into a single package. Rather than build a single, monolithic system on chip (SOC), AMD proposes to leverage advanced die-stacking technologies to decompose the EHP into smaller components consisting of active interposers and chiplets. Each chiplet houses either multiple GPU compute units or CPU cores. The chiplet approach differs from conventional multi-chip module (MCM) designs in that each individual chiplet is not a complete chip. For example, the CPU chiplet contains CPU cores and caches, but lacks memory interfaces and external I/O.

While a monolithic SOC imposes a single process technology choice on all components in the system.

With chiplets and interposers, each discrete piece of silicon can be optimized for its own functions.

It is expected that smaller chiplets will have higher yield due to their size, and when combined with KGD testing, can be assembled into larger systems at reasonable cost (IFTLE note – this is yet to be proven).

It is expected that the decomposition (or disintegration as IFTLE prefers to call it) of the EHP into smaller pieces will enables silicon-level reuse of IP.

(note – this is one of the main drivers of the DARPA CHIPS program …see IFTLE 323)

Thermal Issues ? 

EHP’s in-package DRAMs stay below the 85°C limit. The figure below shows the temperature difference in the bottom-most in DRAM die in a stack (in the package). They conclude that their use of aggressive die stacking should be thermally feasible with air cooling. However, “…more advanced cooling solutions may become necessary as the hit rate of the in-package DRAM improves, more power from the external memory is shifted to the EHP, or if a design point uses a greater per-node power budget.”

amd 2

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 333 Amkor & Global discuss FOWLP at IMAPS Device Pkging Conf

By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the IMAPS Device Packaging Conference with presentations by Amkor, Global Foundries and Huan Tien (FCT) on their FOWLP technologies.

Huan Tien

With reported revenue of $972MM, Huan Tian is ranked #6 among global OSATS. They bought FCI in Phoenix in the fall of 2014. For you younger readers, Flip Chip Technology was a JV of Delco and K&S where Pete Elenius, Tom Strothmann and a host of others developed the bumping technology used today in most of the OSATS and foundries globally. They also invented and commercialized the first fan in WLP. For a review of where things stood in 2000 try this excellent review [“Wafer level chip scale packaging (WL-CSP): an overview”   IEEE Transactions on Advanced Packaging ( Volume: 23, Issue: 2, May 2000]

They have now developed an embedded silicon fan out technology as shown below.

Instead of mold compound, silicon is used as the carrier with KGD embedded and bonded in the wafer cavities. The micro gap between the die and cavity ( ~ 35um) is filled with polymer. Cavities are formed by Bosch etching and are generally ~ 100um deep.

Huan Tian 1


They report:

– lower warpage     – higher density RDL capability

– larger CTE miss match to the motherboard

– parts passed all standard reliability tests.

A roadmap for their embedded silicon fan out (eSiFO) is shown below.

huan Tian 2


Suresh Jayaraman discussed “silicon wafer integrated fan out technology”. Amkor sees a migration from Flip chip and fan in packaging to FOWLP as shown below.

Amkor 1

Key drivers in the High Perform Computing (HPC) and Mobile markets are shown below. They project that eventually the high density FOWLP segment will be > 70% of the total fan out market.

Amkor 2

Below is their roadmap for high density an out evolution.

Amkor 3


Gaurav Sharma discussed “development of fan out package platform for high performance and Rf Applications”.

Suggested benefits for Rf Performance are shown below:

GF 1

They also shared their roadmap for introduction of high density fan out technology

GF 2

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 332 Wither Goest the Toshiba NAND Business?; Unity SC; IMAPS DPC part 4: JCET eWLB-SiP

By Dr. Phil Garrou, Contributing Editor

Now, at first glance you may be saying, “Why is IFTLE concerned with the Toshiba’s memory business? This is an advanced packaging blog!” But I hope most of you have learned IFTLE lesson #1 which is whatever effects chips, directly affects chip packaging. So with that in mind, the recent report by Reuters that Apple is looking into joining the Foxconn bid is very interesting. [link]

The sale of the Toshiba memory business is reportedly being driven by “…multi billion dollar writedowns at Toshiba’s US nuclear unit, Westinghouse” which has recently declared bankruptcy. The collapse of Westinghouse, once the key to Toshiba’s plans to diversify away from consumer electronics, has been hastened by nuclear power project delays in Georgia and South Carolina. Reports from Toshiba are that losses for the year may total > One trillion Yen [link]

To prevent total corporate bankruptcy, Toshiba put up its memory business for sale. Toshiba reportedly narrowed down its list of offers to bids from Broadcom, SK Hynix, Western Digital and Foxconn. According to the Reuters report, Apple was not part of the initial Foxconn bid. .

According to Reuters, Apple is considering taking a 20% stake (several billion dollars) in the Foxconn bid, Foxconn would take 30% and Toshiba would keep a partial holding so the business would remain under US and Japanese control. Reportedly “…Foxconn has been considered a national security risk (to Japan) due to its ties with China”.

This would fit with Apples stated goal of insuring a stable supply of key components. Apple has traditionally used Toshiba’s flash memory in its iPhones and iPads, especially after competitive issues with Samsung developed. Ownership of Toshiba’s NAND flash business would increase Foxconn’s control of the parts it procures for Apple to assemble their phones. Apple, in return, ensures that it gets the best NAND flash for its products, forcing its competitors to stand in line.

But….According to reports in the Financial Times, even if Foxconn successfully partners with Apple, Japanese government officials could still block the sale because they have reservations about al bidders with factories in China. “The Japanese government, Toshiba and its partner Western Digital will likely do everything in their power to prevent any buyer that could potentially allow technology leakage to China and South Korea,” … “Partnering with Apple will not eliminate their concerns regarding Foxconn.” [link]

There are also reports that a consortium consisting of SK Hynix and several Japanese financial institutions reportedly has offered more than $9B for a majority stake in Toshiba memory chip business [link, link] This would make Hynix a major player in both DRAM and NAND and make them more of a threat to rival Samsung. It would also put even more of the worlds memory supply on the Korean peninsula.


Yann GuillouAny of you looking for Yann Guillou at SEMI Europe will have your emails bounce back like mine did recently. Yann is now at Unity SC. Unity was formed last summer by combining Fogale Nanotech’s SEMICON division with Altatech [link]. Unity SC remains a subsidiary of Fogale Nanotech with headquarters in Grenoble FR. Their goal is to provide process control solutions for the semiconductor industry, with a focus on the advanced packaging and MEMS markets.

They claim to have the only complete solution for 3D TSV and FOWLP.

unity 1

So, if you’re doing advanced packaging and/or MEMS and looking for measurement of thickness, CD, surface profiling, TTV, bow, warp, roughness, overlay or defect inspection take a look at their offerings.

unity 2

Continuing our look at fan-out presentations at the recent IMAPS Device Packaging Conference…


As we detailed in IFTLE 331, Yole Developpement reports that JCET leads all FOWLP vendors edging out TSMC with a 37% market share. [link]

At the recent IMAPS Device Packaging Conference JCET discussed advanced 3D eWLBB-SiP technology.

He following slide is a nice summary of target applications for SiP packages.


JCET claims their ability to create ultrafine L/S ground rules, down to 2/2 in a 3 RDL layer format, enables improved routability and tighter component placement. In addition since eWLB eliminates the use of substrate, it reduces the overall package thickness by up to 50% (down to 0.2mm in 2017).


Through additional technologies like thick Cu RDL, embedded inductors and IPD integration JCET provides options to meet RF performance requirements of L, Q factor etc.

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 331 IMAPS DPC Part 3: K&S Describes InFO Process Flow

By Dr. Phil Garrou, Contributing Editor

As one might expect, there were quite a number of fan-out packaging presentations at the recent IMAPS Device Packaging Conference and the next few IFTLE will examine some of those presentations.


Tom Strothmann of K&S discussed “Speed and Accuracy Optimization for Fan Out Die Placement”. Die placement accuracy in conjunction with die shift from the reconstitution process must accommodate the design rules for RDL via size, passivation opening size and pad pitch for the intended devices.

– die placement speed is directly related to cost and the highest UPH is preferred. Typically 10K UPH at 3-5um accuracy. Multi head placement has potential to place 12K UPH with accuracy of 7-10um.

– Accuracy is directly related to yield and the subsequent cost for advanced products

– > 98% yield is required for each RDL layer since compounding yield loss from multiple RDL layers rapidly erodes margins ($$). Thus a lower RDL count is better.

Panel Processing (or as we called it in the late 1990s “Large Area Processing”)

– still remains > 2 years out

– many versions still in development, panel size has not been standardized, equipment suppliers still have moving target

– panel line cost estimated at $100MM

– high speed placement required for lower costs

– panel warpage is still a problem

– die shift occurs as mold cmpd cures

– plating uniformity difficult on large rectangular panels

“High Density fan out will remain on round format for the foreseeable future”

InFO Process Flow

Of great interest was Strothmann’s discussion of the InFO process flow. IFTLE has reprduced the slides below:

K&S 1

K&S 2

Yole Developpement

Jerome Azemar of Yole discussed fan out packaging market trends. Of interest was the following chart showing various applications vs general requirements for I/O and package size ranging from the small, low IO Codec for WiFi to large, high I/O FPGA’s.

yole 1

Fan out technical challenges are described in the slide below including warpage, die topography, failure to planarize chips with mold compound resulting in RDL distortion, die shift during mold cmpd cure and solder joint issues for large packages.

yole 2


Yole reports 2016 fan out packaging revenues at $492MM with SCP / JCET holding 37% market share. TSMC is close behind with 35% share based on their one client Apple.

Yole 3


For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 330 2017 IMAPS DPC Part 2: “80% of Value-add Growth from Wafer Based Packaging”

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2017 IMAPS Device Packaging Conference (DPC) held annually in AZ.


Brandon Prior of Prismark examined “the Changing Landscape in the Back End.” The Prismark punchline is that even though the industry is maturing and entering a period of consolidation and slower growth, “…packaging technology remains critical to delivery of semiconductor and sensor functionality”

Below are some of the system trends that they report:

– 0.4mm pitch components have been mainstream now for > 10 years due to package test below 0.4mm     SMT processes, equipment and materials are not ready for ).3mm

– 0.8mm thick packages are in flagship smartphones (WLCSP,QFN, PoP, FCCSP) Users are asking for 0.6mm; EMI shielding in the package is becoming common.

– SiP use is growing not only in Rf solutions due to smaller footprint and lower total cost potential

– WLCSP has now been commercial for nearly two decades. Both OSATS and foundries have significant capacity. Mobile phones and tablets most significant users. Concerns about cost, reliability and assembly remain.

– FOWLP receiving significant interest. Products are developing for solutions based on: single die, PoP and Multidie with passives as shown below.

Prismark 1

While panel based FOWLP remains of great interest at companies like: STATS/JCET, ASE, DECA, PTI, SEMCO and Unimicron, imaging equipment players (Rudolph, ORC and Ushio) reportedly have not shipped any tools. DECA an SEMCO continue to lead in promoting panel based technology.

A very interesting slide is shown below. It indicates that Prismark sees 80% of value add growth coming from wafer based packaging. [for someone like IFTLE who was promoting WLCSP back in the late 1990s, while at Dow Chemical, when the popular response was that wafer based packaging was absurd, this is great vindication!]

prismark 2


Ron Huemoeller of Amkor examined “Heterogeneous Integration: Packaging for the Future”. Huemoeller indicated that creating value at the packaging level is dependent on (a) smaller form factor, (b) enhanced performance, (c) modularization and (d) high reliability.

Amkor indicates that the high end packaging market can be categorized by application as follows:

Amkor 1

Also of interest is the depiction of key technology drivers by Industry segment:

Amkor 2

DOW Chemical

Speaking of my former employer (been gone since 2004), Eric Huenger discussed “Advanced Materials and Interconnect Technologies for Next Gen Smart Devices”. Although you may have seen it before, I still enjoy seeing the slide shown below which depicts the materials necessary to develop todays high end packaging. It’s good to see Dow with such a broad portfolio. That’s exactly what some of us were pushing for > 15 years ago.

Dow 1

From a historical perspective those that drove electronics in Dow Chemical in the early years (1985-2005) consisted of the following folks:

dow 2


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 329 3D Integration Leaders – Europe; Trolls; More on Intel EMIB

By Dr. Phil Garrou, Contributing Editor

SEMI Honors European  3D Integration Leaders

The European SEMI Award was established in 1989 to recognize individuals and teams who have made a significant contribution to the European semiconductor and related industries. At the SEMI ISS meeting (Industry Strategy Symposium) in Munich, SEMI announced the recipients of the European SEMI Award for 2017. Winners were nominated and selected by peers within the international semiconductor community in recognition of outstanding contributions in the field of 3D Integration.

Rolf Aschenbrenner, deputy director of the Fraunhofer IZM; Eric Beyne, fellow and program director of 3D System Integration at IMEC; and Gilles Poupon, CEA fellow on Advanced Packaging and 3D Integration at CEA-Leti were this year’s award winners.

semi winners



A recent EEE Times article took a look the increase in activity that they have seen from “patent licensing companies”[link], aka trolls.

JC Eloy of Yole Developpement offered that chip vendors have become more vulnerable in recent years because M&A in the semiconductor market, has put many patents is up for sale.

For those of you around the world that don’t understand what this is about, I thought I’d add some background to the EE Times discussion. As the Yole figure below shows these are companies that neither make nor markets products. They derive income by licensing patents to / litigating against companies suspected of infringing said patent(s).

yole 1

trollFrom the work that IFTLE has done for legal firms as an expert witness, I have learned that the legal term for such firms is “non-practicing entity” or simply NPE. The slang term used in the industry for such entities is “patent trolls” which is not meant in any way to be complimentary. I’m not talking the Dreamworks cartoon for kids here, I’m talking old school trolls (…the Norse nouns troll and tröll …mean fiend, demon or werewolf – Wikapedia).

Now trolling in the English language especially modern day slang has many meanings (none of them positive) like internet trolls, but for our discussion here Patent Troll is a term applied to a person or company who attempts to enforce patent rights, against accused infringers, far beyond the patent’s contribution to the prior art, often through borderline illegal, legal tactics”. I hope this definition is polite enough for any trolls out there reading this.

Their standard MO (modus operandi) is to buy up patents with some lifetime left on them at depressed prices. Then, their hoard of lawyers are unleashed on companies that are thought to, or hoped to be, or in most cases just hoped to be fearful of the costs of fending off the accusations of being in violation of said patents. Some of them may have R&D operations which help them determine where to focus and others are simply offices full of lawyers and their helpers.

The MO (modus operandi) of the patent troll is to throw a wide net filing lawsuits against a large group of similar companies and then focusing on what is considered to be the weakest one. Getting them to “give up” and pay what might be an initially low fee, to avoid court costs, is key to their ability to intimidate the rest. Once the license precedent is set, the fact that a similar company has licensed the said patent(s), is a strong factor in court cases. After the first company is “hooked” the price for the rest normally goes up substantially.

Yole has identified the most active NPEs in the figure below. Wi-LAN, based in Ottawa, reportedly acquired 2000+ U.S. patents in 2015, mainly from Infineon/Qimonda and Freescale. In 2016, Wi-LAN initiated 17 lawsuits.

yole 2


In the EE Times article, Mike McLean of TechInisghts’ offered the following suggestion for dealing with NPE’s, “To deal with NPE’s, operators need to either take patents off the market before [NPEs] get them in their hands, or need to be able to effectively challenge patent validity.“ Helping deliver the latter has provided a steady income stream for IFTLE over the last decade.

More on Intel EMIB

At the recent Intel “Technology and Manufacturing day” in SF, Intel Sr. Fellow Mark Bohr again pushed for their EMIB technology [see IFTLE 324 “Intel EMIB Implementation in the Stratix MX”] as the best solution for heterogeneous integration. “Heterogeneous Integration …… This is where you can not only combine two similar die in a package, but in some cases two very dis- similar die….Heterogeneous Integration will be a bigger part of our future…”

Intel 1

In the expanded view and cross section shown below we see the tighter pitch peripheral IO connection to the silicon EMIB bridge. Bohr contends that EMIB solution is cheaper because it does not contain TSV, through silicon vias.

Bohr notes that this is not just a packaging technology since the chips must be custom designed to be used with the EMIB bridge technology. To IFTLE this is a very important limiting factor that I have not seen discussed previously.

Intel 2


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 328 IMAPS DPC Part 1: New MIL Qualified Player in FOWLP

By Dr. Phil Garrou, Contributing Editor

The annual IMAPS Device Packaging Workshop was held at its usual location outside Scottsdale AZ in early March. I noticed at this years meeting among the > 600 attendees were lots of new young faces who had no clue where this meeting came from.

Keeping the Historical Record Straight on IMAPS DPC

AndySince IFTLE is very picky when it comes to keeping the historical record straight, I just wanted to take a few seconds to remind the readership that this meeting was the brain child of Dr. Andy Strandjord who was both a colleague, in our days developing BCB at Dow Chemical, and the Tech VP of IMAPS at the time. In the early 2000’s there were several IMAPS workshops taking place on related thin film packaging topics like MCMs (now called system in package, SiP), bumping and the newly developed wafer level chip scale packaging (Fan in WLPs). Andy pulled them all together into tracks and initiated the Device packaging “workshop” which is really a conference complete with extensive exhibitions, but with no requirement to write a full paper for submission. The first one was held in 2005 and was an immediate success. Next to the fall IMAPS meeting that IFTLE calls the “National” this is the 2nd largest IMAPS packaging focused meeting in the US and after the national and IEEE ECTC is the 3rd largest packaging meeting in the US period. Ted Tessier followed Andy as General Chair for a few years and I was chair in 2010 and 2011. Since then, Chairs have rotated out of the technical committee. Now back to this years conference.

Aurora Semiconductor

I had heard rumors that there was a startup company doing FOWLP which was MIL qualified. Ends up this company is Aurora Semiconductor which spun out of DRAPER Labs in early 2016 by buying the St Petersburg FL facility. They indeed are DOD cleared, ITAR registered, ISO 9001 and are a DMEA Trusted Foundry Program member and accredited supplier.

IMAPS DPC was the first public presentation that I had seen from them, and is worthy of a closer look.

They have branded their technology 4DHSiP.

  • Patented and licensed MCM approach
  • Compatible with COTs (commercial off-the-shelf) components
  • Chips first technology; FOWLP (Fan Out Wafer Level Package),

Aurora 1

Similar to traditional eWLB technology chips are placed face down and overmolded into a wafer. The chips are then interconnected with RDL. These layers are then stacked and connected with through mold vias (TMV). They claim:

  • 4 total layers of interconnect (7 topside and 7 bottom)
  • Controlled Impedance Transmission lines
  • Power/Gnd Bus; Multiple Power Domains
  • Signal line Shielding for crosstalk isolation

Aurora 2

They have developed several techniques including metallic “fins” and “bridges” to conduct heat away. Thermal control appears to be a work in progress.


Santosh Kumar of Yole Developpement gave a new forecast for TSV applications as shown below. They project the market to increase to $7.2B by 2021. 3D memory stacks will grow at the highest CAGR – 48%. By 2021 MEMS & Sensors will become the biggest contributor to TSV application revenues.

Yole 1

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 327 SEMI 3D Summit Part 3: Increased Use of Sensors; HVM FOWLP Applications

By Dr. Phil Garrou, Contributing Editor

Finishing our look at the 2017 SEMI 3D Summit in Grenoble.


Thibault Bisson of Yole discussed 3D packaging as a key enabler.

Yole predicts a significant increase in the use of sensors in smartphones. While the use of sensors was limited to 3 during the advent of the smartphone in ~2007 (microphone, accelerometer and CIS), by 2021 they expect more than 20 sensors in the advanced smartphones.

yole 1

Smartphone APU options, their packaging and specs are shown in the chart below.

yole 2

System Plus Consulting

Romain Faux of System Plus Consulting presented a “technology and cost review of 3D packages in HVM.”

Sys Plus concludes that FOWLP could lead to cost reduction under several conditions:

– In replacement of a chip on board radar chipset.

– In combination with advanced CMOS nodes for single die consumer applications such as baseband, power management, Rf transceivers and/or audio codec solutions.

– in 3D PoP configurations for thin AP + memory solutions.

An interesting comparison is between the 77GHz radar chip sets packaged on COB vs FO-WLP as shown below. One can easily see the miniaturization achieved.

Sys plus 1

Other HVM FOWLP examples include audio codec, power management ICs, Rf transceivers and Application processors.

Sys plus 2

Sys Plus projects a 10% cost savings on the audio codec and a > 50% cost savings on the Rf transceiver.

While Amkors TMV is the predominant package for Application processors, he newer technologies such as the MeCP by Shinko and he InFO by TSMC offer better integration and lower package thickness. Specifically, the TSMC InFO package shows a thickness reduction of 30% while eliminating the laminate substrate.

sys  plus 3

For all the latest in Advanced packaging info, stay linked to IFTLE…

IFTLE 326 2017 SEMI Euro 3D Summit: Thermo-compression Bonding and Plasma Dicing

By Dr. Phil Garrou, Contributing Editor

Continuing our IFTLE look at the 2017 SEMI Euro 3D Summit.


Alistair Attard of Besi discussed “Productivity Improvements in Thermo-compression Bonding (TCB)”.

TCB allows stacking of thin devices at ultrafine pitch ansd as such is an enabling technology for 2.5D and 3DIC stacking. Currently TCB mainly addresses low value high end applications which are performance and form factor driven and have lower cost sensitivity. TCB can be used with non conductive paste, capillary underfill or non conductive films.

Besi 1



– Not well suited for 3D integration (dispensing at each stack layer, NCP bleed, etc.)

– Challenging process for thin dice (< 50μm) due to NCP climbing to the top of the die

– Underfill flow issues for high density fine-pitch bump arrays

– Risk of NCP entrapment in the solder joints


– No issues with adhesive bleed, adhesive entrapment, thin die handling, tool contamination

– Mature CUFs are available

– Proven process for HVM of memory stacks

BUT – Longer process times due to increased process control and solder solidification

– solder joints are not protected until the underfill step – greater risk of joint cracks


– NCF solves some issues of NCP & CUF, but it is still challenging

– Ideal process for thin die & 3D applications

– Reduced die stress due to presence of NCF (good for ULK)

– Shorter process times and collective bonding strategies enable higher UPH

– NCF voiding needs to be controlled

– NCF not yet a mature process

When compared to flip chip mass reflow, TCB is ~ 2X more expensive and is at least 5X slower. In order to be used in larger applications, these issues must be improved upon.

Productivity is increased by reducing the overall TC process time by either of the two approaches shown below (being called Vertical Collective Bonding or VCB):

Besi 2

Besi claims that VCB (gang bond in press) will reduce COO > 5X.

VCB bond profile needs to be optimized (Force, Temp, Timing)

– to get good NCF flow before solder reflow

– to minimize NCF voiding

– to get good soldering at all die levels


SPTS (Orbotech)

Dave Butler of SPTS (now Orbotech) discussed “Plasma Dicing is Becoming Mainstream”.

Conventional dicing includes the following techniques:



Plasma dicing, being offered by SPTS and others uses the same plasma source as DRIE, with the following reported advantages:

No Damage

– Clean, chemically etched scallops

– Active cooling to prevent wafer heating

– Increased die strength

– Yield improvement –no cracking or chipping with plasma dicing

– Advantage for thinner wafers (≤50μm)

Die Density

– Narrow lanes (<10μm) increase usable Si area

– Crack stop areas can be eliminated


– Parallel process

– High Si etch rates –even with more lanes for smaller die

– Option to use cluster platforms

SPTS reports plasma dicing gives ~ 2X die strength vs typical dice after grind techniques.


Reinhard Windemuth of Panasonic also presented info on “Advanced Plasma Dicing”. Pointing out the same advantages as SPTS, Panasonic reports ~ 20% increase in 0.5mm chips from an 200mm wafer due to the reduction in the size of the dicing streets as well as the near elimination of chipping and damage layers as shown below.

panasonic 1

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 325 Omnivision takes Ziptronix License; Semi Europe 3D Summit Part 1

By Dr. Phil Garrou, Contributing Editor

Before we take a look at the recent SEMI European 3D Summit, a little news on the licensing front.

OmniVision Signs License Agreement with Ziptronix

Well, actually Ziptronix as we all know by now was acquired by Invensas, a division of Tessera, in the fall of 2015.[see IFTLE 253 “China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix … “]

But now, Tessera has changed its name (as of Feb 22nd) to Xperi (link).

The key issue here is that Ziptronix owns patents for direct oxide bonding and copper/oxide so called hybrid bonding ( they call tehse technologies Zibond and DBI). This technology that is being used extensively in the CMOS image sensor (CIS) market and was licensed to Sony, the accepted world leaded in CIS in 2011 [link]

There has been ongoing litigation with Omnivision over violation of the Ziptronix patents since 2010. [link]

A few weeks ago that litigation was resolved when Tessera announced that its subsidiary Ziptronix had reached a licensing agreement with OmniVision. In turn, the outstanding litigation by Ziptronix against OmniVision and TSMC has been dismissed.[link]

FYI, the Ziptronix IP has also been licensed by aerospace leaders Raytheon, Teledyne and supplier Novati.

2017 SEMI European 3D Summit

The Annual SEMI European 3D Summit took place in late January in Grenoble France. For the next few weeks we’ll be taking a look at some of the interesting presentations that were given there.

Meyer – Infineon

Thorsten Meyer, one of the early players in FOWLP used a great simple slide to show the advantages of FOWLP over 2.5D interposers for select lower density cases. Basically the FOWLP (like eWLB) can reach the 200um pitch directly without the high cost silicon interposer. When this can generate enough IO for your application, this could be the most economical solution.

Intel 1


Wolf – Fraunhoffer Institutes

Juergen Wolf examined the technologies available in the Fraunhoffer institutes for “Heterogeneous Integration for 3D systems.”

Of interest is their work with Osram and Infineon to develop GaN LED chips n Silicon drivers as shown below.

Wolf 1


Wolf also announced that Fraunhoffer is working with Ziptronix on their DBI bonding technology and showed a 96% yield on DBI test vehicles.

  • DBI is an extension of Ziptronix’ ZiBond technology that allows an interconnect pitch of less than 10-microns, and accommodates 1.5 million connections per square centimeter.
  • The process uses advanced tools to planarize the wafer surface and allows hermetic bonding SiO2/Cu at low temperatures (300°C).
  • Technology is jointly developed by Invensas and IZM ASSID & partners

wolf 2

Also of interest was their interposer roadmap which included not only TSV but also integrated passives, embedded chips and fluid cooling channels down the road.

Gen 1 Interposer = TSV, multi layer redistribution(RDL)

Gen 2 Interposer = + integrated passive devices

Gen 3 Interposer = + embedded active devices and/or MEMS

Gen 4 Interposer = + integrated optical & electrical interconnects

Gen 5 Interposer = + active cooling (e.g. fluid channels)

Groothuis – Samtec

Steve Groothuis discussed the use of glass interposers. Samtec acquired Triton Microtech (a glass interposer startup) last year. Their approach is to use thin fil RDL with thick film filled vias. “Samtec Microelectronics will be processing borosilicate glass, fused silica, quartz, zirconia, and sapphire wafers and eventually panels for cost and scaling.”

While they acknowledge that the glass interposer platform has not become mainstream yet, they contend that glass interposers are a strong candidate to be used in RF applications because of superior electrical insulation, low dielectric constant, high hermeticity, low warping, and high resistance to corrosion. Their design rules are shown below.

samtec 1

Samtec shows copper diffusion data and concludes “No diffusion of Cu into the glass –No need for a barrier layer along sidewall,” this leaves me somewhat puzzled since the last time I checked glass was SiO2 and we now Cu diffuses like a rabbit in SiO2. Maybe the expts were not run under bias?

They conclude that Samtec will work with customers in various areas of Glass Core Technology for prototyping, low-volume production, and paths to high-volume manufacturing.

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