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IFTLE 245 2015 IEEE ECTC part 1 Thermo compression Bonding

By Dr. Phil Garrou, Contributing Editor

Over the next few weeks of the summer, I will be covering as much of the 65th IEEE ECTC as I can. They call themselves the “Premier International Packaging Conference” and they are. Authors from companies, research institutions, and universities from over 25 countries presented their work at ECTC, illustrating the conference’s global focus. In addition, the ECTC offered 16 Professional Development Courses (PDCs) and Technology Exhibits.

This year there were 350 papers presented in 36 oral sessions covering 3D and TSV technologies, wafer level packaging, electrical and mechanical modeling, RF packaging, system design, and optical interconnects.

This years conference leaders include (from L to R) Sam Karikalin, Broadcom, Beth Kesser, Qualcomm, Alan Huffman, RTI Int and Henning Braunisch, Intel.

ectc 1


First, let’s look at some advances in thermos-compression bonding.


Jie Fu of Qualcomm discussed “Thermal Compression Bonding for Fine Pitch Solder Interconnects”. Mass reflow-based interconnects, using either solder bump or Cu-column on bond on lead are the typical low-cost flip chip assembly approachs used by industry. These interconnects face challenges related to shorting and non-wets at sub 100um pitches. Transitioning below 100um pitch requires a new approach, such as thermos-compression flip chip (TCFC). While TCFC provides higher accuracy bonding and allows for use of smaller solder cap which enables tighter FC pitch, it also presents new challenges. The major challenges for TCFC bonding include lower throughput and control of non conductive paste (NCP) voids. Overall, bond head ramp rate, temperature uniformity, peak temperature and dwell time must be fine tuned in tandem to compensate for manufacturing tolerances and to get the desired end of line solder joint structure. In addition, controlling the temp exposure for the NCP material before NCP cure is critical to enable a robust TCFC solder joint. To much thermal exposure and the NCP begins to cure prior to solder melting, which can leading to NCP entrapment and unreliable TCFC solder joints. Laminate surface finish is also an important variable.


In a similar study Cho and co-workers at GlobalFoundries presented “Chip Package Interaction Analysis for 20-nm Technology with Thermo-Compression Bonding with Non-Conductive Paste”. Strong market demand for finer pitch interconnects to enable higher I/O counts in a smaller form factor is driving another transition from conventional MR bonding process to thermo-compression bonding using non-conductive paste (TC-NCP). FEA simulation results for TC-NCP vs mass reflow show that TCNCP has significantly reduced thermo-mechanical stress at the ULK level and the bump level.


Horst Clauberg of K&S discussed “High Productivity Thermocompression Flip Chip Bonding”. There is tremendous effort by IDMs, OSATs, materials suppliers and equipment suppliers to bring thermos-compression bonding to commercial reality. The most significant technical challenges have for the most part been solved and limited commercial production is taking place. However, relatively low throughput and high equipment cost create adoption resistance, especially in the all-important consumer market.

Due to the relatively high cost, the only component of the industry clearly adopting thermocompression bonding is the advanced memory segment, such has hybrid memory cube (HMC) and high bandwidth memory (HBM). The rate of adoption for applications processors, GPUs and the like may depend on the rate at which throughput and cost can be improved.

Thermocompression bonding can be segmented into two different processes. The first process differentiation is whether the underfill is pre-applied before the semiconductor chip is mounted or not. Pre-applied underfill comes either as a film applied to the die or as a paste applied to the substrate. In both cases the underfill must not only create a void-free bond, but also provide flux to remove oxide on the solder caps. The alternative process is thermocompression – capillary underfill (TC-CUF) where the die is underfilled in the same way as std flip chip,except that the underfill process is much more challenging because of the more narrow bondline of a typical thermocompression bonded device. In TC-CUF, flux can be applied either by dipping the die into flux before bonding, or applying flux to the substrate.

A K&S cost-benefit analysis of a C2 (copper pillar bump) TC bonding process was used to look at the total packaging cost. Besides enabling higher I/O counts and finer pitch interconnections through better control of the stress and warpage, the actual bonding process is just a small contribution to the overall assembly cost. K&S shows that the incremental assembly cost adder for thermocompression bonding is actually rather small in a high UPH TC bonder. The hurdle to wide-spread adoption of the TC bonding is more likely the initial capital expenditure associated with buying new equipment when depreciated infrastructure already exists for mass reflow processes. Adoption of the technology will therefore be driven by technical need and market forces. TC bonding will enable higher I/O counts and finer pitch interconnections than traditional interconnect methods through better control of the stress and warpage between devices and the substrate. Once the infrastructure is established, they predict that the cost will decrease directly proportional to throughput and they have demonstrated that throughputs of 1000uph are possible.

Fig 2

Amkor / Qualcomm

Doug Hiner in a joint presentation between Qualcomm and Amkor presented “Multi-Die Chip on Wafer Thermo-Compression Bonding Using Non-Conductive Film”. Non-conductive films have been in development as a replacement to the liquid preapplied underfill materials used in fine pitch copper pillar assembly.

Several assembly methods are available for chip on wafer assembly including: (1) traditional chip attach with mass reflow (MR) and capillary underfill (CUF), (2) thermo-compression

bonding (TCB) of copper pillar interconnects using nonconductive paste (NCP) underfill (TCB+NCP), and thermocompression bonding of copper pillar with non-conductive film (NCF) underfill (TCB+NCF).

The TCB+NCP process carries concerns with the underfill time on stage which prevents the dispensing of the NCP material across the wafer prior to the chip bonding process. This constraint effects process costs significantly. The TCB+NCF process to date have not met the cost/benefit needs of the industry. NCF assembly provides significant improvements in the design rules associated with die to package edge, die to die, and fillet size. The NCF process also resolves the time on stage concerns associated with the NCP process by laminating the NCF material to the bonded die instead of to the interposer or receiving wafer surface.

Development has proven the feasibility of a multi-die (gang) bond chip on wafer assembly process. Key assembly steps have been validated and major issues have been mitigated through optimization of materials and process parameters. A scale up phase of development has been initiated which targets the bonding of 8 die (4 units) in a chip on wafer format. Assembly cost of ownership estimates (OSAT) suggest cost parity between 8-die gang bonding and traditional mass reflow…

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 244 3D Stacked CMOS Image Sensors; IEEE 3DIC Conf

By Dr. Phil Garrou, Contributing Editor

At the recent 2015 Int Image Sensor Workshop, Ray Fontaine of Chipworks presented a review of “The State-of-the-art of Mainstream CMOS Image Sensors” Chipwork’s estimate, from other market research firms, is that the CIS market in 2014 was ~ $9B. Of this total it is estimated that Sony, Samsung and Omnivision hold > 66% market share driven by mobile phone and tablet camera chips.

Their look at the patent literature shows the field continues to grow with 2500 patents filed in 2014, the majority of them being processing patents.

cmos image sensor patents

Stacked Chip CIS

3D stacked CIS became a reality in 2012 when Sony announced the worlds first stacked chip CIS in consumer cameras. In 2013 they introduced the 8 MP ISX014 in a tablet computer [ref]

[P. Jagodzinski, “Sony ISX014 ¼ inch 8 MP 1.12um pixel size Examor RS stacked back illuminated CIS imager process review” Chipworks March 2013 ]

The first gen chips employed via last TSV to connect pads on the Sony 90nm CIS die to the pads on the Sony 65nm ISP. The die stack was partitioned such that most of the functionality of a conventional system-on-chip (SoC) CIS was implemented on the ISP die; the CIS die retained the active pixel array, final stage of the row drivers, and comparator portion of the column-parallel ADCs. The CIS (left) and ISP die (right) are shown below.

Click to view full size.

Click to view full size.

Sony’s 13 MP IMX214 second generation stacked CIS chips were fabricated using its 90/65 nm (CIS/ISP) technology generation. The key work on the second generation stacked process was to use the CIS silicon only as the active pixel array substrate and move the column readout chain and peripheral transistors to the underlying ISP die.

In 2014, Sony announced they were using TSMC as a foundry for the 40nm ISP wafers on the Apple iPhone 6/6 Plus iSight cameras. These chips incorporate Sony 90 nm CIS wafers and TSMC 40 nm ISP wafers.

In 2015, Samsung and OmniVision have both been sampling small-pixel, stacked chip CIS.

Given the continued, aggressive stacked CIS development underway from independent device manufacturers (IDM) and foundries it’s predictable that stacked chip adoption will occur very rapidly over the next few years.

IEEE 3DIC Conference Sendi Japan Aug 31st

Click to view full size.

Click to view full size.

The IEEE International 3D System Integration Conference (3DIC) will be held in Sendai, Japan August 31-Sepember 2, 2015. After the first conference in San Francisco in 2009, the 2nd IEEE 3DIC Conference was held in Munich in 2010, and then Osaka in 2012. The forth conference was back in San Francisco in 2013 and the fifth conference in Cork, Ireland in 2014.

IEEE 3DIC 2015 will cover all 3D integration topics, including 3D process technology, materials, equipment, circuits technology, design methodology and applications. The conference invites authors and attendees to submit and interact with 3D researchers from all around the world. Papers are solicited in subject topics, including, but not limited to:

  • 3D IC Process Technology
  • 3D IC Circuits Technology
  • 3D Applications
  • 3D Design Methodology

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 243 Amkor Fan Out Package Platforms

By Dr. Phil Garrou, Contributing Editor

Amkor recently held a customer Symposium covering their activities. Let’s take a look at some of the interesting points that they covered on their fan out package platforms.

2014 Amkor revenue is clearly dominated by the communications segment.

Amkor 1


When looking in general at the evolution packaging they see the largest focus on filling the gap between 1 and 10um as shown below.

Amkor 2


Their packaging roadmap to address this gap area is shown below and is tied to their Swift and Slim product families. Such ultra thin packages will have to be handled by temporary bonding to a rigid substrate in order to process them.

amkor 3


From a mobile products standpoint they see the 5+um range filling most of the needed requirements for density/IO, whereas the SWIFT product line will be needed for < 5um BB module (SiP) requirements.

Amkor 4


The SWIFT and SLIM processes are depicted below. SWIFT interconnect is carried out on an RDL bumping line by Amkor whereas 2-5um SLIM interconnect is fabricated by foundry.

Amkor 5


Since interconnect is fabricated first, higher densities can be achieved, i.e. 2-8um L/S for SWIFT vs           8-15um for traditional chips first FOWLP.

Amkor 6


In summary depending on the requirements of the application, different technologies are available and/or are being developed to meet those requirements.

Click to view full size.

Click to view full size.


For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…


IFTLE 242 Advanced Packaging at the ConFab

By Dr. Phil Garrou, Contributing Editor

At the recent ConFab meeting in Las Vegas, aside from all the talk about consolidation (see IFTLE 241), Bill Chen from ASE and Li Li from Cisco put together a great Advanced Packaging session.

(L to r) Bill Chen (ASE), Ram Viswanath (Intel), Kevin Tran (Hynix), CP Hung (ASE), John Knickerbocker (IBM) and Li Li (Cisco)

(L to r) Bill Chen (ASE), Ram Viswanath (Intel), Kevin Tran (Hynix), CP Hung (ASE), John Knickerbocker (IBM) and Li Li (Cisco)

CP Hung, VP of R&D for ASE discussed “Integrating 3D IC into the IC Packaging DNA” Hung proposed that 2.5D IC significantly extends FCBGA technology as shown in the fig below.

Fig 2


Kevin Tran of Hynix announced that HBM (high bandwidth memory) has completed the qualification for mass production in March 2015. Each application has different memory requirements, but most common are high bandwidth and density. He indicated that packaging technology has become a key enabler for high performance, small form factor, low cost memory solutions.

Fig 3


Hynix is readying HBM 2 which will be applied for HPC, graphics, servers and network computing. High end graphics products have already been announced like Pascal at Nvidia and Greenland at AMD. Can Intel be far behind? IFTLE thinks not.

Fig 4


Ram Viswanath of Intel pointed out that “…the ability to monolithically integrate diverse functionality on the die has become impractical due to technology complexity and affordability” and that “on package integration is playing a key role in bringing diverse functionality into smaller form factor.” Key focus is on delivering

– performance for servers

– form factor for wearable products

– cost/form factor for client products

-low cost for future IoT products

Intel’s evolution of dense interconnect is shown below. The Xenon Phi for HPC uses memory stacks on an interposer (reportedly Micron HMC).

Fig 5


Intel compares  side-by-side multichip packaging to 2.5D interposers to 3D stacking in the table below. (note – IFTLE cannot support some of the conclusions on EMIB without seeing the actual data first).


Multichip                  side-by-side

2.5D Interposers

3D stack

Si interposer


IO/mm/layer 30-50 180-250 180-250 NA
IO/mm2 85-120 330-625 330 625
Elect perform (IO)        
Elect Perform (Power)        
Perform (Watt)        
Manuf complex (Yield)        
Thermal limits        

*2.5D designs are comparable

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 241 Simply Obeying the Laws of Economics

By Dr. Phil Garrou, Contributing Editor

Following up on the recent blog by my comrade, Dick James.

There are laws and then there are laws. “Moore’s Law” to me is more of an observation. Gordon Moore simply noticed what was going on and commented on it.  Powerful laws, to me, are usually laws of physics like Newtons law of gravity or Einsteins Law of relativity.

When we consider the laws of economics, many economists would contend that consolidation is a law,   i.e. a natural process which has happened consistently to all industries since the industrial revolution. Through consolidation a mature industry usually has only a few (2-3) players ( for instance Boeing and Airbus in the aircraft manufacturing business) whereas young industries like the internet may initially have hundreds.

CarvilleSo what does this have to do with microelectronics you might say. Well, just ask the former employees of Altera and Broadcom. If this were the early 1990s James Carville (Clintons spinmeister) would respond “It’s consolidation stupid” [I was not a Carvile fan as you can tell by the picture I picked out !] Consolidation is what happens as industries mature. We are in the midst of it, it’s natural and probably unstoppable.

Lets first take a look at what’s happened in the hard disk drive segment of our industry.

Greater than 200 companies have been in the hard disk drive business since the 1960s. They initially competed on data density and latency and smaller form factors. Most of that industry has vanished through bankruptcy, mergers and acquisitions. Surviving manufacturers are Seagate, Toshiba and Western Digital. Seagate  acquired Samsung’s HDD business in 2011;  Western Digital (WD) merged with Hitachi’s HDD business in 2011. This gave Seagate 40% of the HDD market and WD ~ 48%. The remaining ~ 12% was owned by Toshiba who acquired Fujitsu’s HDD business in 2009. Thus by 2012 what was several hundred players had been whittled down to 3 by, I contend, the laws of economics.


Now let’s look at DRAM.


In 1980 there were 40+ DRAM fabricators but by 2015 we are down to Samsung, Hynix and Micron. See the trend?

The best description of whats happening, that I have seen is the 2002 Harvard Business Review article “The Consolidation Curve” by G K Deans et. al. Their main point is that all industries have similar life cycles and knowing where your company stands in the process can help you plot a winning strategy.

They divide up the stages of all industries as follows:

Stage 1: the combined market share of the three largest companies is between 10% and 30%. Companies in stage 1 industries aggressively defend their first-in advantage by building scale, creating a global footprint and establishing barriers to entry, i.e. protecting proprietary technology or ideas. Stage 1 companies focus more on revenue than profit, working to amass market share.

Stage 2: Stage 2 is all about scaling. Major players begin to emerge and buy up competitors.  The top three players in a stage 2 industry will own 15% – 45% of their market, as the industry consolidates. The companies that reach stage 3 must be among the first players in the industry to capture the most important markets and expand their global reach.

Stage 3: companies focus on expanding  core business and continuing to aggressively outgrow the competition. The top three industry players will control between 35% and 70% of the market with five to 12 major players remaining. This is a period of large-scale consolidation plays. Companies in stage 3 industries focus on profitability, and pare weak businesses units. The well entrenched in this phase will attack underperformers. Recognizing start-up competitors early on allows market leaders to decide whether to crush or acquire them. Stage 3 companies should also identify other major players that will likely survive into the next, and final, stage and avoid all-out assaults on them which could leave both players injured.

Stage 4: In stage 4 the top three companies claim as much as 70% to 90% of the market. Large companies may form alliances with their peers because growth is now more challenging. Companies in stage 4 must defend their leading positions. They must be alert to the danger of being lulled into complacency by their own dominance. Stage 4 companies must create growth by spinning off new businesses or buying into aligned fields to broaden their market presence.

When you understand this then headlines like the recent “The next three chip firms to be acquired: Atmel, Lattice and Cavium are the top take out candidates for the rest of 2015”[link]

As most of the segments of our industry enter late stage 3 or early stage 4 the only question is whether you will acquire or be acquired, or as Carville said “ It’s the economy stupid!”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 240 AMD introduces High Bandwidth Memory (HBM) on Fiji R9 390X GPU

By Dr. Phil Garrou, Contributing Editor

AMD announces HBM in 2015 High End Graphics Module “FIJI”

For over two years now, IFTLE has been saying that memory stacks will soon be seen in high end graphics processor modules. Nvidia was the first to announce the use of stacked memory with GPUs [see IFTLE 145 “GPU Roadmap….” (April 2013)]. Nvidia’s Volta GPU module was scheduled for 2015 release and was supposed to use the Micron Hybrid Memory Cube (HMC). Rumors are that after HMC’s development fell behind the proposed roadmap timing, Nvidia moved the Volta introduction out to > 2016 after the Pascal module, which will be based on Hynix HBM 2 and is scheduled to be commercial in 2016.

So now the first commercial graphics products to feature HBM clearly will be AMD’s R9 390X series Fiji GPU in 2015. The Rx 300 series will also reportedly be the first to feature TSMC’s 20nm technology and the first to be equipped with HBM. There are 4 HBM stacks packed on the same interposer as Fiji. Each HBM stack has a capacity of 1GB of memory.

Recent rumors from Taiwan indicate that production is being slowed by issues concerning delivery of the silicon interposers from their primary supplier. Reports are that AMD is having to rely more heavily on the secondary supplier to try to keep production on track.

AMD graphics module


The first generation of HBM promises to deliver 4.5X the bandwidth of GDDR5 and 16X the bandwidth of DDR3 as shown below.

HBM vs other DRAMS


The second generation HBM is well underway and promises to double the bandwidth by doubling the speed from 1Gbps to 2Gbps. It will also quadruple the memory capacity for 4-Hi stacks from 1GB to 4GB.

HBM 1 & 2 specs


Reportedly HBM2 is scheduled to be featured in AMD’s upcoming “Greenland” GPU [link]. It’s rumored that the new graphics family will be manufactured at Globalfoundries on their 14nm FinFET process node which would be a major loss for TSMC.

A summary of AMD graphics processor modules is shown below.

AMD GPU summary


There are also reports that AMD is working on multicore APUs that will use similar interposer / HBM memory technology [link].

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 239 Omnivision Acquired for $1.9B; Retinal Recognition; 2015 RTI ASIP

By Dr. Phil Garrou, Contributing Editor

Omnivision sold to Chinese Consortium

OmniVision, a supplier of CMOS imaging chips has entered into an agreement to be acquired by a Chinese consortium, which includes Hua Capital Management Co. for ca. $1.9 billion. The transaction is expected to close in the 3Q or 4Q 2016, if it receives necessary regulatory approvals including antitrust review in the U.S. and review and clearance by the Committee on Foreign Investment in the U.S. In order to obtain clearance or approval in Taiwan, OmniVision will divest certain of its investments, including certain of its interests in a Taiwan joint venture.

Speaking of players in the CMOS imaging sensor market, Yole recently updated their market look at these devices as shown below. While smartphones are still the main driver, there are a lot of other applications for these devices.


Giving your smartphone “the eye”

If you’re getting tired of using the fingerprint sensor or typing in a password to access your smartphone like I am, it looks like a selfie will soon become the access method of choice.

EyeVerify has developed Eyeprint ID – a highly accurate biometric technology for smart devices that delivers the ultimate in secure, private authentication. This patented solution uses existing cameras on mobile devices to image and pattern-match the blood vessels in the whites of the eye. Check it out at

Currently, a Fujitsu smartphone is using iris-recognition technology. The phone recognizes the unique pattern of the iris, which remains constant after the age of two and is difficult to forge [link]. That pattern is read by shining an infrared LED light on the eyes and taking an image of them with an infrared camera to acquire the iris pattern, which is registered and used to verify matches.

retnal scan

Fujitsu claims the technology will be faster and more accurate than face recognition. Because this uses ActiveIRIS from Delta ID, this system can be used at a normal smartphone viewing distance, rather than within the 10cm range that most existing iris recognition systems require. In standard photobiological safety testing, the infrared LED light was verified to be safe for the eyes.

Fujitsu is not the only company working on iris-recognition technology. Chinese smartphone manufacturer ZTE included the iris recognition software in a new smartphone earlier this year. Samsung has also recently filed patents for iris recognition.

RTI 3D ASIP scheduled for December 2015

Patti, McCray, ArifThe RTI (Research Triangle Institute) 3D ASIP (Architectures for Semiconductor Integration & Packaging) Conference is the longest running 3D conference in the world. The 2015 conference will be the 13th in succession. There will be some important changes that I want to bring you all up to date on.

The General Chair for the last 12 meetings has been RTI employee Matt Mecray (see 2012 photo of Bob Patti, Matt and Arif Rahman) who a lot of you have gotten to know through the years. Many thanks to Matt for his efforts. Unknown to many of you is that Matt does not live at the RTI headquarters site in Research Triangle Park NC, but rather in Portland Maine. Yes that is the East coast town that received over 100 inches of snow this past winter. (talk to me about global warming sometime). Anyway, after leading us for 12+ years Matt is moving on to other activities at RTI and they have asked me to take over his general chair duties for this years conference which will be held Dec 15-17th. The conference will once again be held near the SF airport (site to be chosen soon).

What in the past has been called “the preconference symposium” will now be known reserved for special topic  tutorials, one AM and one PM which will cover two 3D related topics that I hope will be of interest to our attendees.  The conference will be on the 16th & 17th of December. We are in the process of developing the program so if you have any thoughts on what you’d like to see included send them to me ASAP.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 238 ASE & the Apple watch, ASE / TDK JV; China: the Wild Card

By Dr. Phil Garrou, Contributing Editor

ASE rumored to get Apple watch SiP order

Rumors are that ASE has won the contract to package the S1 processors for Apple Watch using SiP packaging to reduce overall dimensions achieving the required compactness necessary in the watch [link]. Apple appears sold on the technology after implementing it last year in Apple WiFi chips and fingerprint recognition chips also packaged by ASE. Apple indicates they are “…quite optimistic about the commercial potential of SiP” and “…plan to build SiP devices into half its iPhone 6S in the second half of 2015 and all  iPhone 7, which reportedly will go on sale in the 3Q 2015.

In related activity, ASE announced that it will be spending $3-6B to double its SiP production capacity over the next 3 years. [link]

ASE and TDK form JV to Address SESUB Embedded Packaging

ASE and TDK have announced an agreement for a JV (ASE Embedded Electronics Inc.), based in Kaohsiung, to manufacture IC embedded substrates using TDK’s SESUB (Semiconductor Embedded Substrate) technology [link].

TDK has been producing SESUBs internally for a little over a year, but has entered into this JV “…to meet the anticipated increase in demand”…and take advantage of ASE skills in the area of “…assembly of IC packages, and … a world-class performance record in product testing.”

SESUB is a high-end substrate technology where thinned semiconductor chips are embedded in laminate substrate with copper interconnection down to 20µm minimum L/S. The thickness of the substrate including the integrated semiconductor chips is just 300 µm.

Multiple chips can be embedded side by side to produce MCP /SiP products. Discrete components can be mounted on the top of the substrate. Since the copper layers that form the interconnect are defined by photolithography, their dimensions can be controlled to enhance thermal performance of the modules.

Below are examples of (A) Maxim Power Management Unit (PMU) Module and (B) Bluetooth module.



China: The Wild Card

When we look at what’s going to happen in the Semiconductor industry in terms of consolidation the wild card is always China. It has been well publicized that China national policy is to acquire and grow in this area. China represents about one-third of the approximately $330 billion global IC market, however, domestic production supplies only 10 present or so of its demand.

China’s government policy “National Guidelines for Development and Promotion of the IC Industry,” which was released in June of 2014 calls for expansion and vertical integration of the domestic semiconductor value chain.  The Ministry of Finance, the Ministry of Information Industry (MII) and the National Development and Reform Commission support the targets of achieving domestic sales revenue of $56B by 2020 and reaching the technology level of international “tier 1” companies by 2030 [link].

Initially, the government investment fund has about $20B. Over the next decade, however, most expect to see $100B  stimulation across the Chinese semiconductor ecosystem.

According to John Pitzer, managing director at Credit Suisse, speaking at the “Wafers to Wall Street” SEMI forum in San Jose, China’s intention to increase domestic semiconductor production represents the single most significant risk factor to U.S. semiconductor industry dominance [link].  He believes that significant intellectual property and R&D barriers will constrain China’s domestic technology development and mitigate some of the intensity of its domestic growth ambitions.  However, the accelerated policy-backed Chinese merger and acquisition activity and an active Chinese R&D university agenda presents a longer-term risk in the industry. Recall in IFTLE 222 we have discussed Chinese intent to become an acquisition “predator” in microelectronics.

china aquisitions


Pitzer noted that China is planning semiconductor industry investment of $170B in an attempt to reduce dependence on semiconductor imports.  Potential M&A of U.S. companies appears to be a near-term theme. Consequently, he expects to see more Chinese companies collaborating with leading U.S. companies and more overseas M&A from China.

For all he latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 237 ETERIS NO MORE; Samsung Invests Big ; Comparing Systems & Chip Growth

By Dr. Phil Garrou, Contributing Editor


Eighteen months after announcing a deal to Tokyo Electron, Applied Materials has announced that the $7B deal will not go through due to regulatory concerns [link]. The two companies said the decision for terminating the deal came after the U.S. Department of Justice told the companies that their proposals for a combined business were not good enough to replace the competition lost from a merger.

The Korea Times has also reported that “the Korea Fair Trade Commission (FTC) disapproved the proposed merger between Tokyo Electron and Applied Materials in line with the latest objections by Washington.”

As IFTLE has mentioned many times in the past few years, the decline in the number of semiconductor firms that can afford to have their own chip fabrication plants has reduced the customer base for the industry.

The termination of AMAT-TEL merger will affect AMAT’s position in the etch and deposition equipment segments. Although Applied has a larger  deposition market share (47%) than TEL (~12%), the new company, preliminarily named ETERIS, had opportunities to fill out its product portfolio by the merger. Applied is clearly behind in the deposition segment after LAM merged with Novellus in 2012 to gain a substantial presence in the segment. The Applied / TEL merger was expected to close the gap with LAM but now that will not happen.

2013 semi equipment market share leaders are shown below.

semi equipt mkt share


Samsung Invests Big
Samsung has announced a $14.7B plan to build a new wafer fab south of Seoul.  Slated to begin production in 2H17, will add to Samsung’s current fabs (listed below) [link].

Samsung has spent at least $10 billion per year on semiconductor capital since 2010 and has accounted for 17-21% of total industry capital expenditures each year since then.



Samsung did not identify what type of chips will be manufactured at the new fab.
Samsung is expected to give strong consideration to foundry operations at the new fab.  Despite losing the Apple A8 processor business to TSMC (a $2 billion foundry customer), Samsung reportedly is committed to growing their foundry business.  Its leading-edge manufacturing capabilities make it an attractive option for several fabless and fab-lite logic IC companies.

IC Insights Compares Market Sizes and Forecasted Growth Rates for Systems, ICs

IC Insights reports that total production value of electronic systems increased 5% in 2014 to $1,488B. Cellphones expanded their lead over PCs (desktops and notebooks) as the largest electronic systems market in 2014 after overtaking standard PCs for the first time in 2013.



Cellular handsets accounted for 25% of IC sales in 2014, while standard PCs represented about 21% of the total.  IC revenues generated by these 11 end-use systems categories represented nearly 80% of total integrated circuit sales worldwide in 2014.



For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 236 IMAPS DPC Part 3: Yole Update on FOWLP and Embedded Packaging

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS Device Packaging Conference:

Yole Developpement

Based on his new Yole report “Fan out and Embedded Die: Technology and Market Trends,” Jerome Alzemer updated the IMAPS audience on the Fan Out and Embedded die marketplace.

Embedded Packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infrastructure such as FOWLP and (2) those based on a PWB/PCB laminate panel infrastructure.

Fan-out WLP are “re-configured” by placing known good ICs active face down on a foil and by over-molding them. These wafers are then flipped and processed in the wafer fab with RDL / ball placing and diced.

For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs. These generic process flows are contrasted in the figure below.

FO & embbedded process flows



Unlike Fan In WLP which has been commercial since the late 1990’s, FOWLP is not constrained by die size, and thus can offer an unlimited number of interconnects for maximum connection density. One can also achieve  finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

Commercialization of the Infineon e-WLB (embedded wafer level BGA) technology started in 2009 with single die packages for cell phone baseband chips.   The Infineon technology was later licensed to OSATS Nanium, STATSChipPAC and ASE thus creating a multi sourced infrastructure.

A similar process called Redistributed Chip Packaging (RCP) was developed by Freescale during the same time period. It was subsequently licensed to NEPES but has not yet reached HVM. Other developing FOWLP  technologies including those of  TSMC (called InFO), SPIL and J- Devices are approaching commercialization but will initially lack the multi-sourcing available with eWLB.

The second generation of FOWLP are multichip packages including PoP and SiP configurations. These are generating increased interest in this packaging approach.

2nd gen FOWLP2014 FOWLP market share

Technical Challenges, such as warpage, die shift, chip-to-mold non planarity and topography, remain significant limitations. FOWLP requires specific re-design vs  FC-CSP solutions which are more flexible and mature.

The sweet spot for FOWLP application is restricted to die that need more  I/O at a given pitch than can be accommodated by the the chip dimensions otherwise fan-in will meet the requirements.

Laminate Embedded Die

Laminate Embedded die packages are not widespread yet. They are currently limited to low I/O count die. AT&S and TDK/Epcos have a DC-DC converter in production for TI since 2010 but no other HVM products have appeared since then. Such laminate embedded die packages are currently a niche technology in the wireless and mobile markets.

AT&S and TDK-EPCOS are collaborating on standardization of products, which they see as necessary to obtain better acceptance of this packaging format.

Other players such as Taiyo-Yuden, Unimicron and DNP have proposed products such as camera modules, MEMS, DC-DC convertors, RF modules, etc.  Few production products have appeared reportedly due to the absence of standards, lack of multiple sources, and high prices due to low yield.

As of 2014, Yole estimates a market of around $14MM driven by AT&S with TDK having a minor market share.

2014 embedded laminate mkt

Initial commercialization of Embedded Die Package technology has started but is currently limited to low pin-counts, small die-size, low-cost, power, RF and mixed signal chip applications.

Potential exists for entering the power, RF and mixed signal chip applications but standardization and multiple sources are lacking. Yole does not expect the technology to near HVM before 2016 at the earliest and this will require the appearance of standardized, more complex integrated SiP modules from multiple sources.

Challenges for Laminate Embedded Die Packaging

Supply chain evolution and process standardization are the main challenges for Embedded Die package technologies.

– Total accessible market is currently limited by current poor pad pitch performance

– It is not yet clear whether improving resolution to produce better pad pitch will require moving to higher cost manufacturing tools which would negate the attempt to use laminates  mature manufacturing flow to achieve low costs.

– Without a defined supply chain and an accepted process flow, multi-sourcing and cost reduction are not possible

– HVM is required to reduce costs to acceptable levels

FOWLP and Laminate Embedded Die are complementary technologies. That situation might change if Embedded Die achieve higher resolution, but that currently is not the case. They are compared in the figure below.



A complete outline of the Yole report can be found here [link]

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