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IFTLE 365 Altera FPGA with HMB2 and EMIB; IWLPC 2017 Part 2

By Dr. Phil Garrou, Contributing Editor

Merry Christmas and Happy New Year to One and All


Intel Altera release Stratix 10 FPGA with HBM2 memory and EMIB connections

Before we continue our coverage of the 2017 IWLPC, I need to make sure everyone has seen the announcement from Intel (Altera) on the availability of the Intel Stratix 10 MX FPGA, their FPGA (field programmable gate array) with integrated HBM2 (High Bandwidth Memory). [link]

Intel 1

The Intel Stratix 10 MX FPGAs, utilizing Intel’s 14 nm FinFET process, reportedly offer up to 10X the memory bandwidth as compared to standard DDR 2400 DIMM standalone memory solutions. In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can reportedly compress and accelerate larger data movements compared with stand-alone FPGAs.

The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512 Gb per second through the integrated HBM2. The Intel Stratix 10 MX FPGA family utilizes Intel’s EMIB technology (Embedded Multi-Die Interconnect Bridge) for high density connections. IFTLE thinks this is the first commercial implementation of EMIB technology in the industry.

intel 2

IWLPC part 2


Brubaker and Strothman of KNS discussed the “Application of Infrared Inspection to Thermo-compression bonding and die placement”.

In die placement processes, accurate die placements are required to ensure the formation of functional and reliable electrical interconnections. Verification of accurate die placement can be a challenge for standard flip chip products where there are no patterned features on the backside of die. Cross-sectioning or X-ray inspection can be done, but cross-section inspection requires that samples be epoxy under-filled, ground, polished, and inspected using a microscope. X-ray inspections typically require offline processing with dedicated equipment.

In situ measurement within the die placement equipment itself would be preferable. Typically, die placement machines are equipped with a camera which is utilized for target alignment operating within the visible spectrum. The addition of infrared inspection capability to die placement equipment resolves the limitations presented for in situ visible inspection. Because silicon is transparent to infrared light, an infrared inspection system is able to see through the blank backside of die to detect internal metal patterns. Silicon wafers and die which have been back thinned using a fine grind or polishing process are excellent candidates for infrared inspection. Wafers which were back thinned using coarser mechanical grinding (2000 grit and 1200 grit) yielded lower quality infrared images. The impact of this limitation is believed to be minimal, since most high-end die which require high accuracy placement are evolving to thinner packages which already require fine surface finish to prevent die cracking and wafer warping.

In addition to surface finish, die designs must include features which can be used to generate images with sufficient quality to measure die offsets. In many cases, no special considerations are required in terms of die design. If the absolute best possible placement capability is desired, it is noted that dies which include features optimized for infrared inspection will maximize measurement capability.


Bellman and co-workers from Corning Glass discussed “Temporary Bonding for High Temp Processing of Thin Glass”.

Their “Advanced Lift-off Technology (ALOT)”, is a temporary wafer bonding method for thin glass which reportedly permits subsequent processing over 400C. Fluorocarbon plasmas modify the surface of the glass permitting subsequent controllable van der Waals bonding between a thin glass plates at room temperature. This modification can withstand the vacuum, thermal, wet processing steps of BEOL processing. However, the bond energy between the pair remains low-enough after the thermal processing steps that renders the pair fully detachable.

The ALOT process involves treating a clean hydroxylated glass carrier surface in low-pressure plasma containing CHF3 (or C4F8) and CF4 gases. The CHF3 gas acts as a polymerizing agent and deposits organic fluorocarbon species on the glass carrier while CF4 acts as an etchant and tends to etch away both glass and the organic polymer deposited by CHF3.

In the figure below they plot the bond energy as function of annealing temperature for glass to glass carrier without ALOT treatment (marked as “glass on glass”) and for thin glass bonded to ALOT treated glass carrier corresponding to three initial surface energies (40 mJ/m2, 55 mJ/m2, 72 mJ/m2). The bond energy of untreated glass to glass pair increases exponentially after 200 °C rendering the pair permanently bonded due to covalent bonding. On the other hand, the bond energy of thin glass and ALOT-treated glass carrier pair remains fairly constant at a moderate value up to 400 °C irrespective of the initial surface energy of the glass carrier. This renders the thin glass- glass carrier pair de-bondable after ay post processing which experiences a maximum temperature excursion of ~350-400.

corning 1


Barker and co-workers at SPTS discussed “RC Management for Next Gen PVD UBM/RDL Metallization Schemes”.

Organic materials such as PI or PBO dielectric passivation, epoxy mold compound (EMC), or adhesives for bonded wafers with 2.5D and 3D TSV) have the potential to contaminate under bump metal (UBM) or redistribution layers (RDL) producing a potentially undesirable increase in electrical contact resistance (Rc). With the reduction of UBM/RDL via dimensions in line with device shrinks, contamination effects become more critical.

When placed under vacuum and heated, organics will outgas moisture significantly more than traditional ‘front-end’ dielectrics such as SiN and SiO2. When those same organics are sputter-etched during the subsequent UBM/RDL pre-clean step to remove native oxide from exposed metal contacts, they release volatile carbon by-products from their surfaces. Both moisture and carbon by-product contaminants can react with the cleaned exposed metal pad contacts, forming a layer that increases the contact resistance of overall metallization interconnect scheme produced. The problem is particularly acute with advanced node devices with small contact area dimensions where the contaminant has a proportionally larger impact.

New package schemes such as FOWLP can include wafers that feature singulated die embedded in epoxy mold compound (EMC), and have organic dielectrics surrounding the RDL. These materials present challenges, including moisture absorption, excessive outgassing and a limited tolerance to elevated temperatures. Whereas conventional circuits built on silicon can withstand heat up > 400C and can be degassed rapidly without impacting system throughput, the presence of any EMC, organic dielectrics, or bonding adhesives introduces a lower heat tolerance which can be as low as 120C. Temperatures exceeding these lower thresholds can cause decomposition of the organic based materials, in EMC case; it can lead to excessive wafer warping. Degassing wafers at such low temperatures naturally takes a longer amount of time.

Multi-wafer degas (MWD) technology has emerged as a solution to this problem, enabling many wafers to be degassed at 120C in parallel before being individually transferred to subsequent process steps, without breaking vacuum. Each wafer can spend up to 30 minutes inside the MWD, but because they are processed in parallel, a “dry” wafer is outputted for metal deposition every 60 to 90 seconds, at a rate of between 30 to 50 wafers per hour. This approach increases PVD system throughput by 2-3 times.

If a wafer with organics present isn’t degassed sufficiently prior to pre-clean it can produce high levels of outgassing that affect plasma stability during etch, and film quality (Rc) during subsequent sputter deposition. As the surface of the wafer is etched during the pre-clean step, native oxide is removed from the exposed metal contact, but the ion bombardment damages the surface of the organic passivation, releasing volatile carbon species, which, re-contaminates the metal contacts.

spts 1

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IFTLE 364 2017 IWLPC Part 1: Advances in Packaging Polymers

By Dr. Phil Garrou, Contributing Editor

Let me start by saying this year’s IWLPC presented what I consider to be the best program in their history. Congrats to the organizing committee for upgrading the technical content of this conference. Collecting and sharing both the presentations and the papers was an added benefit to attendees.

We will first take a look at presentations that described new polymer dielectric advancements.

HD Micro

Matsukawa of HD Micro described their “Low temp curable PI/PBO for Wafer Level Pkging”.

For next generation advanced packaging technologies, the most important requirements for dielectric materials are low temperature curability, high lithographic performance, high chemical resistance, and low warpage. They report on new low temperature (<200⁰C) curable PI and PBO.

Conventional photosensitive PIs and PBOs have required curing temperatures greater than 300ºC to complete cyclization as well as advance polymerization. To formulate low temperature curable materials, they re-designed the polymer backbone in order to enhance cyclization and changed the cross-linker to form a strong network structure even when cured <200⁰C. They presented the following table comparing “conventional PI” (what ever that is ??) to the new generation PI as shown below.

HD 1

Generally positive tone photo-definable materials are composed of a PBO precursor, a photo acid generator, cross-linker etc. Regarding the new positive tone PBO, a suitable photo acid generator and cross-linker combination was selected to increase the resolution while also improving the adhesion to Cu, which has been a significant problem for past generation products. Properties are shown below.

HD 2


Araki of Toray discussed their “Novel Low Temp curable positive tone photo dielectric material with high elongation for panel processing”.

Dielectric materials for redistribution layers (RDL) are one of the most important materials for fan out panel level processing (FOPLP). Toray introduces a low-temperature curable positive-tone photosensitive dielectric material with the high elongation property for fabricating RDL on FOPLP. The high elongation property was achieved by the introduction of flexible molecular skeleton in the base polymer backbone to increase the entanglement of each polymer chain. Cured films showed elongation up to 80%. This positive-tone photosensitive material offers fine pattern (3 um trench and 5 um line and space) with good sensitivity (300 mJ/cm2 (i-line)) and shows high chemical resistance toward resist strippers. Properties of their new PI are shown below.

toray 1

Hitachi Chemical (HC)

Fukuhara of Hitachi Chemical described their “Photo-sensitive Insulation Film for Encapsulation and Embedding” Conventional PoP with flip chips mounted on BGA like substrates is shown below compared to a fan out PoP.

hitachi chem 1-2

In order to make a high density connection between upper and lower packages, it is necessary to form fine pitch through holes on the bottom package. These through hole vias can be formed by laser drilling. HC has developed a laminate photo film which allows encapsulation of the die and subsequent photo formation of the required vias through the film as shown in the process below.

hitachi chem 2-2


Reliability results are show below.

hitachi chem 3

Onozeki of Hitachi Chemical discussed “Wafer Level Packaging Materials and Processes” where he examined the influences of the material properties of temp bond adhesives (TBA) and epoxy mold cmpds (EMC) on the warpage of FO-WLP during the fabrication process by both of the experiments and finite element analysis.

For TBA, it was found that “the deformation of TBA results in relatively free shrinkage of EMC on the support, and Young’s modulus of TBA influences on the warpage most significantly. The small Young’s modulus TBA suppressed the warpage regardless of the support materials”. As for the EMC, “…the low Young’s modulus, low CTE and low Tg are effective to reduce the warpage after post mold curing. The warpage after grinding EMC was smaller than those after post mold cure and there was no big difference in the influence of the mechanical properties”. As for FO-WLP structure, the wide die pitch, thin EMC and thick die are effective to reduce warpage. Especially, the wide die pitch contributes to reduce the warpage. 4 layers re-distribution layer with line and space of 2 and 2 μm was successfully fabricated. The layers were interconnected with small diameter filled Cu vias of 5 μm. The vias were formed in the photosensitive dielectric material. A bias HAST test revealed that this material had enough insulation reliability.


Okamoto from JSR discussed “Fine Pitch Plating Resist for High Density FOWLP”.

For the next generation of high density FO-WLP, RDLs as low as 2um are reportedly required to support more I/O’s and multiple RDL layers. In this situation, RDL plating resists have to provide higher resolution with a wider common depth of focus margin than conventional resists because there are often large topographic gaps between the chip and the mold substrate. The plating resists must also be applicable for various plating solutions under each recommended process condition. JSR describes the development of a resist that has resolution to 0.7um L/S at 5um film thickness and has excellent resistance to various plating solutions.

For all he latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 363 IMAPS 2017 Part 4: DARPA SHIELD; Shinko embedded die for PoP; Rf Interposers

By Dr. Phil Garrou, Contributing Editor

Hope all my readers in the USA had a great Thanksgiving. For those of you around the world, this holiday occurs in late November in the US when families get together for a 4-day weekend. I was with my two sons and my granddaughters Hannah and Madeline (who you have watched growing up ) in Houston and it was great to spend some time together. Younger son Christopher, who is a Chef in Maine, joined us and helped with the cooking activities.



Now let’s finish our look at the 2017 IMAPS Conference.

Northrup Grumman

Under the DARPA/MTO SHIELD program Northrup Grumman led a team of GaTech, Sandia, Kilopass and RFID Global solutions have developed a supply chain traceability and authentication method to protect against counterfeit electronic parts. The solution consists of the incorporation of a 100 x 100 x 20um “chiplet” (they call dielet) fabricated in 14nm CMOS. Authenticity is verified using an Rf probe to energize and communicate with the chiplet. Putting the size of the chiplet into perspective, the pic below shows the chiplet on the head of Lincoln on the back of a penny.

NG 1

The chiplets are manufactured using GlobalFoundries 14nm FinFet technology. The 300mm wafers are thinned and the 20um dicing streets result in ~ 4MM chiplets per wafer. Pick and place of these tiny chiplets is “challenging” but they have developed a technique to insert them into the host packages. Process flow is shown below:

NG 2


Kyozuka of Shinko discussed the “Development of Thinner PoP Base Packages by Die Embedded and RDL Structure.”

PoP structures can achieve thinness by embedding a die (or dies) into a package thus achieing height reduction for devices like APS (application processors). Their “die embedded with RDL” structures are shown in the fig below with design specs.

shinko 1

The process flow is shown in the fig below.

shinko 2

The FC process is done by TCB (thermos-compression bonding) followed by capillary underfill . After die mounting the cover layer of laminate is vacuum laminated and vias are laser drilled to make connection between the substrate and the top RDL. Expected issues with warpage were controlled by controlling layer thicknesses and copper density on the layers.

Via formation included laser drilling, desmear, electroless and electrolytic copper plating. Vias were tested under condition B (-55 to 125◦C) with 75 and 100um visa passed such testing.


Bart Vereecke of IMEC discussed “Investigation of wafer level packaging schemes for 3D Rf interposer multi-chip module”. The fig below schematically shows the structure with a GaAs MMIC mounted on the silicon interposer. The interposer consists of two metal levels sandwiched around a MIM cap layer. A Cu/Ni/Sn seal ring is designed in for bonding Si cap layer. The interposer is made of high resistivity Si to minimize Rf losses.


They examined different wafer level packaging approaches for fabricating the interposer and populating them using either D2D or D2W bonding of the MMIC components followed by wafer level encapsulation. These are compared in the table below. All of the process flows appear to have issues.

imec 2

Axus Technology

Bob Roberts of Axus presentation “Technology transfer for MEMS and Adv Packaging” was a nicely written review of the use of CMP and the thinning of silicon wafers which I can recommend to those wanting a refresher on the technology.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 362 Broadcom Continues Consolidation; IMAPS 2017 Part 3

By Dr. Phil Garrou, Contributing Editor

Before we get back to the IMAPS 2017 conference, a few important items:

Consolidation – and the beat goes on

We have talked a lot about consolidation and why it is happening. [see IFTLE 255 “Consolidation continues …” and IFTLE 241 “Simply Obeying the Laws of Economics” ]

On November 6th Broadcom announced its intention to buy its rival, Qualcomm, for ~ $130B, including debt. If successful, it would be the largest deal in the history of the technology acquisitions. Following the consolidation trail, NXP acquired Freescale and Qualcomm is trying to acquire NXP and Broadcom is trying to acquire Qualcomm. Certainly a sequence that no one could have predicted a few years ago. If Broadcom successfully acquires Qualcomm, the combined group would become the world’s third-largest chipmaker, behind Intel and Samsung. If they combine, with no divestments, Qualcomm and Broadcom would control between 50%-60% of the market for Wi-Fi chips and 27% of radio-frequency chips for mobile devices.

The Economist offered the following table listing mega mergers (consummated and in process) [link]

economist 1

The Economist also offers the comment that “with Qualcomm’s pending purchase of NXP and Broadcom’s of Brocade, what looks at first glance like a merger between two giants is actually a four-sided deal. It would be difficult to unite so many different divisions and business units all at once” It certainly will be interesting to see what happens here!

Continuing our look at IMAPS 2017

InFO like FOWLP from ASM Pacific & partners

John Lau representing ASM coauthored the presentation “Fan out Wafer Level Packaging of Large Chips with Multiple Redistribution Layers” with a long list of co-workers. The design is a chips first face up process looking a lot like the TSMC InFO. The detailed descriptions of the processing are much appreciated. The overall process flow is shown below.

asm 1


As is the case for InFO the key processing sequence is plating up the contact pads on the wafer (30um), molding the wafer and hen grinding back the mold cmpd to expose the copper pads much like you would a TSV. Their mold compound is Nagase R4507 a liquid EMC with 85% filler content and an average filler particle size of 8um.

Subsequent processing of the RDL layers is shown below. The smallest L/S features on the bottom RDL layer is 5/5.



From this groups 2nd paper “Characterization of fan-out WLP” we learn that

– die attach accuracy and pitch compensation are the key issues that need to be controlled for accuracy in the RDL process

– die tilt is an important factor that affects the contact pad reveal so the die bonder should be optimized to control leveling

– molding concerns include die shift, warpage and voids. Mold cmpd choice will affect warpage results.

Namics & Hitachi Chemical

The presentation “Development of Liquid Compression Molding (LCM) Materials for Low Warpage” by Namics and Hitachi Chemical detailed the properties required for a low warpage LCM. They were able to substantially reduce LCM warpage by using aliphatic, flexible epoxy resins with low modulus and low cross link density.

Hitachi Chemical

Hitachi Chemical also detailed their studies on “Highly Reliable Cu Wiring Layer for 1/1um L/S using newly Designed Insulation Barrier Film.”

It is generally agreed upon that organic substrates fabricated by the semi additive plating process is limited to 8um L/S . To achieve finer interconnect pitch required by future FOWLP Hitachi Chem has studied trench wiring to create such high density structures. This sequence is typically laser ablation of the trenches in the dielectric, copper plating and subsequent planarization by CMP. Barrier metal is required to minimize copper migration so the seed layer for plating is generally 50nm of Ti followed by 100nm of sputtered Cu. The processes are compared below. For reliable HAST testing of 2/2 L/S they have found that covering exposed Cu with a Ni barrier layer is required.

Hitachi chem 1

They have also examined chemically amplified, negative tone, photosensitive dielectrics to achieve below 2/2 L/S. This processing includes the use of an insulation barrier film which shows low moisture absorption, low anionic impurities and high hydrolysis resistance. Using this combination they were able to achieve 1/1 L/S.

hitachi chem 2

For all the latest in advanced packaging, stay linked to IFTLE…

ITLE 361 2017 IMAPS Part 1: Xilinx HMB Integration Challenges and More

By Dr. Phil Garrou, Contributing Editor

Let’s start looking at some of the key presentations at IMAPS 2017.


Gandhi of Xilinx gave an interesting presentation on “2.5D FPGA-HBM Integration Challenges.”

Heterogeneous integration of HBM (high bandwith memory stacks) with ASIC, GPU, CPU and FPGA is real and progressing quickly. Xilinx is the frst company to attempt HM integration with partitioned FPGAs in a 2.5D format.

Xilinx 1Xilinx recently announced HBM enabled 16nm Ultrascale FPGAs which are shown below. They are built using 3rd gen CoWoS technology jointly developed by Xilinx and TSMC. The claim is that these heterogeneously integrated packages are delivering 10X the bandwidth per HBM stack and 4X lower power than DDR-4 . These packages are 55 x 55mm2.


Interposer Design – µbump pitch on the memory stacks are set by JEDEC standards. There is no std for µbump pitch on FPGAs. For ease of interposer routing, pitches across the two die need to match so that an integer number of inter die signal lines can be routed in a uniform fashion between a pair of micro bumps. This is also required from a signal timing point of view.

Package Design and Process –

xilinx 2HBM-FPGA integration for the current 16nm product required changes to bump structure and lid type. The packages moved from eutectic solder bumps to copper pillar bumps with lead free solder and a change from a copper lid to a stainless steel stiffener ring was also required. This is shown in fig below. Precise control of bare die parallelism and flatness is required to enable heat sink attachment. In the shown figure, modeling shows that co-planarity is reduced by wider ring width and/or thicker stiffener ring. They were also required to change the BGA substrate to a lower CTE core to lower the co-planarity.

Challenges in bump assembly

Addition of the HBM stacks results in open area around the HBM stacks in the layout as seen in the above pic. This results in higher warpage. Bump size and underfill type must be optimized.

ETRI (Electronics and Telecom Research Institute) Korea

ETRI has examined the “Development and Stacking Process for 3D TSV Structures using Laser.”

As part of their 3D studies they have compared bonding results between using TC (thermocompression) and laser. The bonding procedure is shown below.


The max temp of the compression bonding was 240 °C for 200 sec at a force of 1 Newton. At a laser power of 200W the max temp reached was 260 °C at a process time of 10 sec.

They concluded that there was no difference in the solder joint morphology and the electrical resistances of bonded daisy chains for both assembly technologies was the same.


Kobus presented a “Alternative Deposition Solution for Cost Reduction of TSV Integration.” Use of TSV requires isolation, barrier and copper seed deposition into the etched vias. For low AR TSV one uses PECVD and PVD techniques for the depositions. For high AR vias ALD is sometimes required. PECVD offers the highest dep rate but poor conformality. ALD results in near 100% conformality irregardless of AR, but the thickness is limited and he dep time is very slow.

FAST (Fast Atomic Sequential Technology) combines CVD and ALD to reportedly rapidly give thick, conformal depositions.

Oxide liner dep from TEOS is compared below.

Kobus 1

Electrical properties of the deposition are reportedly enhanced with 150 °C deposition resulting in BV or 9MV/cm.

TiN barrier layer is from TDEAT (tetrakisdiethylamidotitanium) and copper seed from Cupraselect™. Copper seed dep comparing FAST with PVD are shown below. They report that the field thickness (on top), resulting from copper deposition to get 200nm of copper at the bottom of a 10:1 AR via, is reduced by 2X which effects the subsequent CMP time to remove it.

kobus 2

Claims of a 24% reduction on TSV processing cost are claimed.

For all the latest on Advanced Packaging, stay linked to IFTLE…


IFTLE 360 IMAPS 2017 – 50 Years and Counting

By Dr. Phil Garrou, Contributing Editor

IMAPS 50th

IMAPS (the Int Microelectronics Assembly and Packaging Society) 2017 was held this year near their Research Triangle Park headquarters, in Raleigh, NC, certainly a convenient location for IFTLE. Having started operations in 1967 as ISHM (Int Society for Hybrid Microelectronics), they changed their name and focus during my Presidential year of 1998 to IMAPS. This is the 50th year of existence for this nonprofit society. I emphasize the term nonprofit intentionally. This is important to me since the conferences we all attend request we give our free time to serve as presenters or session chairs or organizers and I want to be sure that the profits from such enterprises are going to a nonprofit and not into someone’s personal bank account, as is the case for so many of these conferences you and I attend. Basically, I don’t work for free unless it is a non profit, only seems right to me, so conferences that I give my limited time to, tend to be organized by IEEE and IMAPS.

My first IMAPS conference was in 1985 as my professional focus in Dow Chemical shifted from R&D on organometallic catalysts to the electronics industry. I was 35 but only a rookie in the electronics industry with lots to learn. This was the first electronics conference of my career (which I then followed up with the ECTC conference in the spring of 1986) and as importantly, it introduced me to many of the contacts and long term friends that I was able to develop in this industry through the years.

Fig 1

I recently took a look at the Proceedings (which I still have in my professional library) and during this trip down memory lane thought you might be interested in what was considered groundbreaking 32 years ago.

In the mid 1980s the industry was just getting comfortable with surface mount components and Harry Charles of Johns Hopkins was talking about “Design Optimization and Reliability Testing of Surface Mount Solder Joints”.

In the computer aided design session authors from Tektronix were sharing their thoughts on “Just-in-time Manufacturing – An essential technique for Process Control”.

In the Polymer Applications session, Englehard (that’s right Englehard the precious metals company) was showing us how to spin coat polyimide in their paper “Multi-layering with PI dielectric and metallo-organic conductors.” This paper had a significant influence on my personal career since, working for Dow Chemical at the time, I went back home wondering whether I could find a Dow polymer material that could be used for similar thin film polymer IC applications. This eventually led me to the discovery (it existed in the bowels of Dow R&D without a clear application need) and commercialization of BCB dielectric which by the mid 190s led to the commercialization of low cost bumping and WLP at FCT and Unitive and subsequently all the key bumping houses in Taiwan as they licensed the technology. By the early 2000s, BCB was being used in components put into nearly every cell phone being manufactured in the world!

The interconnect technologies session contained the paper “Recent advances in Die Attach Adhesives for Microelectronics” given by epoxy legend Dick Estes from Epoxy Tech. At the time polymeric die attach were not allowed in high rel military applications. He described the issues of thermal stability, outgassing and most importantly halide contamination of devices.

Kohji Nihei of Oki , later to become infamous as the photographer of the generation that proceeded me, gave the first paper I had ever seen describing the use of “LEDs for the electrographic, non impact printing of text and images” entitled “Development of High Quality LED Print Head” (shown below) Think that’s a technology with a commercial future?

Fig 2

For those of you that don’t remember Kohji, you should, both as a wonderful person and a technologist. Below he is shown a few years later in Japan with the American contingent at an IEEE VLSI workshop.

(l-r) Kohji Nihei (Oki), Len Schaper (AT&T, Alcoa, U. Arkansas), Garrou, Jan Vardaman (TechSearch), George Harman (NIST “Mr. Wirebonding”)

(l-r) Kohji Nihei (Oki), Len Schaper (AT&T, Alcoa, U. Arkansas), Garrou, Jan Vardaman (TechSearch), George Harman (NIST “Mr. Wirebonding”)

That’s enough of the past. Next week, we will begin our look at the 2017 IMAPS Conference content, I promise.

For all the latest on advanced packaging and nostalgia, stay linked to IFTLE…

IFTLE 359 ARM on IoT; SEMICON Taiwan Part 4

By Dr. Phil Garrou, Contributing Editor

Will IoT require “dirt cheap” packaging?

Those of you following IFTLE’s position on IoT know that while I certainly see a future where the wireless collection of data proliferates, I see this, in general, for extreme low cost packaging solutions, certainly not, as some have said in the past, an IoT using 2.5/3D solutions.

In seeming agreement with that conclusion, Rick Merritt of EE Times describing the recent ARMTechCon reports that the panel discussion on “Breakthrough Technologies enabling the future of IoT” concluded that the future of IOT could depend on a chip that sells for less than 50 cents, that SoCs will need new kinds of memories, connectivity and sensors to scale to dimensions the IoT will demand, and that the path to get there is still unclear. [link]

He reports that SRAM and flash memories, Bluetooth interfaces and sensors consume too much power to serve volume IoT nodes in 2027 where ideally, ARM reports, an end node SoC would consume just 10 microwatts/MHz and send and transmit data on a radio drawing only 1 or 2 mW. In terms of transmission, radios need to ultimately scale to power levels of a tenth the power of today’s Bluetooth Low Energy which perhaps will require a new radio maybe on new frequency bands which might take a 10-year effort to execute. Sensors will also need to explore new materials and design techniques to lower power, shrink size and add features. Sensors will need heterogeneous integration packaging technologies to integrate them into modules. “ … so the package becomes the sensor with silicon inside it”. Bottom line seems to be, as we have stated before, that the packaging solutions for IoT will have to be “dirt cheap”

SEMICON Taiwan continued…

Brewer Science

In his presentation on “New Materials for Fan-out WLP,” Tony Flaim of Brewer proposed an interesting new fan out concept where cavities are laser drilled into a laminated sheet, chips are inserted face up into the cavities and thin film RDL is created over the chips as shown below.

Brewer 1



IFTLE is not a big fan of making technology decisions based on cost modeling. My past experience has shown that he cost models that I have used are generally very accurate when all the inputs are well known and not very accurate when the inputs are being “guestimated”. Having said that, I do like the slide presented by Chet Palesko of SavanSys Solutions on the general comparison of embedded die vs FOWLP vs TSV solutions shown below…

Savansys 1


ITRI always gives us a nice update on activities in Taiwan. Below we see that Taiwan foundry services currently account for 70% of the world wide market and the Taiwanese IC packaging and test services account for 55% of the world wide SATS market.


Global Foundries

Dave McCann of GF showed a nice process flow for their 2.5D production where the interposer fab, logic fab, memory fab and OSATS must work together to deliver the finished product.


Next week, we will begin our look at IMAPS 2017. For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 358 SEMICON Taiwan Part 3: ASE & Powertech Fan Out Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at 2017 SEMICON Taiwan.


John Hunt of ASE discussed his thoughts on “Fan Out Packaging – Simple to Complex”.

An interesting slide was his chronology of wafer Level (WL) packaging sine the adoption of bumping and RDL (the advent of Taiwan licensing the FCT technologies).

ASE 1-2

Hunt divides fan out (FO) categories into low density and high density options:

  • Low Density fan out

– Less than 500-600 I/O

– L/S > 8µm

  • High Density fan out

– Greater than 500-600 I/O

– L/S < 8µm

Early applications for low density FO include baseband and Rf transceivers. New opportunities include:


Early high density fan out opportunities include PoP and SiP

New Opportunities include:

– APU + memory

– GPU + memory

– Network applications

– SiP/Modules

Note the GPU and Network apps begin to intrude into the space carved out by Silicon 2.5D. Such a product is described below:


Hunt showed the following ASE fan out package platform:



David Fang, CTO of Powertech discussed PTI panel level processing developments.

– Packaging for more than Moore modules is usually larger than 10x10mm and thus panel level processing provides 3-5X the efficiency of wafer level even at 300mm.

– They have found that the initial investment per module is 30-40% higher for panel level fan out modules than for fan in WLP.

Continuing challenges for panel processing include:

– No worldwide standards

– Tool and accessory readiness

– Process difficulties, i.e. panel warpage, chip shift, fine line patterning

An interesting slide details their thoughts on panel equipment selection based on technology from the Wafer, LCD and PWB industries.

powertech 1

Powertech fan out solutions are shown below.

powertech 2

For all the latest on Advanced packaging, stay linked to IFTLE…

IFTLE 357 SEMICON Taiwan Part 2: Laser Processing

By Dr. Phil Garrou, Contributing Editor

Continuing our look at SEMICON Taiwan 2017, we’ll look at some of the papers dealing with laser processing for advanced packaging.


Habib Hichri examined the reliability of ultra fine line redistribution. Redistribution, developed in the 1990s to facilitate bumping or chips designed for peripheral interconnect, is now indispensable for WLCSP, fan out WLP and Embedded IC packaging.

The claim he best process is a dual damascene process flow creating the trenches and vias by laser ablation as shown below.

Suss 1


  • Excimer laser ablation patterning does not require photosensitive materials

–allowing wider choice of dielectric materials

  • Ablation patterning is performed after cure
  • Significant reduction in lithography-related steps

–No photoresist application, develop or strip required


YE Yeh of ASE described their “Laser Technologies In Advanced Packaging and SiP Process” They offered the following use of lasers for their advanced packaging technologies.


Trumpf Lasers GmbH

Michael Lang of Trumpf Lasers discussed Laser application development for advanced packaging.

Ultra short pulse lasers enable extremely precise, cold ablation of different materials as shown below in the comparison of ns and ps lasers. Typical materials used in Advanced Packaging can be machined without heat-affected zone.

trumpf 1



Nimrod Bar-Yaakov of Orbotech discussed laser via formation for Advanced Packaging.

They offered the following as key advantages of laser drilling for Advanced Packaging applications:

  • Cost and process reduction: Direct material ablation saves photo-litho processes
  • “Digital Patterning”: adjusts the drilling pattern according to the actual location of the die
  • Same tool and process suites various substrate compositions
  • Laser processing tools are panel format ready

They offered the following process flow for PoP laser ablation of TMV:

Orbotech 1

Pattern-based registration

  • Die placement and process variation can cause misalignment between fiducials and pattern
  • Using actual pads pattern as registration targets can overcome this issue

orbotech 2

They offered further visual evidence that thermal effects are reduced by using short pulsed lasers.

orbotech 3

For all the latest in advanced packaging, stay linked to IFTLE…

ITLE 356 SEMI Taiwan Part 1: Fan-out Packaging Players, Applications and Market Growth

By Dr. Phil Garrou, Contributing Editor


Although threatened by Typhoon Talim, SEMICON Taiwan went forward Sept 13-15 in Taipei. Over the next few weeks IFTLE will be covering Interesting advanced packaging disclosures and topics with relevance to advanced packaging. Our thanks to Semi’s Debra Geiger, Jamie Liao and Grace Wang for linking IFTLE to the relevant materials.

CP Hung of ASE chaired the SiP forum “3D IC, 3D interconnection for AI & High-End Computing” and Albert Lan of Applied Materials chaired the forum “Innovative “Embedded Substrate” and “Fan-Out” Technology to Enable 3D-SiP Devices.”

albert Lan

Albert Lan – Applied Materials

CP Hung - ASE

CP Hung – ASE

Let’s first take a look at the embedded and fan-out forum


Jan Vardaman presented the following list of Fan-out WLP suppliers

TechSearch 1

TechSearch lists the following as why Apple chose this TSMC packaging format for their A10 processor

  • Improved electrical and thermal performance of InFO vs. FC-­‐CSP

– InFO PoP Power Noise Reduction and Signal Integrity Improvement

  • Thinner than flip chip package (no substrate)

– InFO-­‐PoP is 20% thinner than FC-­‐PoP

– Can enable a low-­‐profile PoP solution as large as 15x15mm

TechSearch 2

An interesting comparison of Amkor’s SWIFT vs ASE’s FOCoS vs TSMC’s InFO.

techsearch 3

Lastly, the TechSearch list of fan-out WLP evolving applications:

  • Baseband processors
  • Application processors
  • RF transceivers, switches, etc.
  • Power management integrated circuits (PMIC)
  • ConnecDvity modules
  • Radar modules (77GHz) for automotive plus other ADAS applications
  • Audio CODECs
  • Microcontrollers
  • Logic + memory for data centers and cloud servers
  • Power devices
  • Fingerprint sensors

Yole Developpement

Jérôme Azémar of Yole gave their take on “Fan-Out Packaging Technologies and Markets”.

Long time IFTLE readers know that we dislike the term fan out since all packages except fan-in WLP are fan out packages. To add to this Yole has added the following:

yole 1

Their take on applications is show below plotting package size vs IO count.

yole 2

Yole sees significant future growth initiated by the Apple adoption of the TSMC InFO package.

yole 3

For all the latest on advanced packaging, stay linked to IFTLE…