Author Archives: sdavis

IFTLE 194 More on IBM / GF ; SEMI Singapore part 3: Nanium, Fujitsu, EVG

By Dr. Phil Garrou, Contributing Editor

The Latest on IBM and GF

Craig Wolf of the  Poughkeepsie Journal reports confirmation from Global Foundries that 150 to 200 IBM’ers will move from IBM’s East Fishkill chip plant to GlobalFoundries’ plant in upstate Saratoga County. GF has confirmed a contract with IBM in which “technical workers” based at the East Fishkill will work for eight months at GF’s Fab8 chip plant. IBM refused comment on the deal.

While one cannot conclude that his confirms the imminent sale of the IBM Semiconductor division to GF (which IFTLE has predicted for several years) , it certainly indicates that things are slow in the IBM plant.

Continuing our look at the recent 2.5/3DIC Forum at SEMI Singapore.

Nanium

Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology and that eWLB offers an alternative with sufficient capability for many applications in high volume at reasonable cost.

PoP structures such as those shown below are being readied for portable applications where less than 1mm thickness is required.

Nanium 1

Nanium is working with AT&S to develop technology for reconstitution in laminate vs traditional eWLB which forms a wafer out of molding compound.

nanium 2

Fujitsu

Fujitsu presented on “Highly reliable chip to chip Cu wiring technologies for 3D/2.5D interconnection.” Their premise is that as interconnect gets finer and finer traces will need full barrier layer protection similar to what is done on chip with dual damascene, especially when the interposer is a high density PCB. This is shown by HAST failures as shown below.

Fujitsu 1

Their proposed failure mechanism is:

- Halide ions and organic acid accumulate around the anode Cu

- Anode Cu dissolves and Cu ions are formed

- Cu ions diffuse and drift into insulating materials

- Cu dendrite growth on cathode surface triggers dielectric breakdown

fujitsu 2

A barrier layer is needed to prevent Cu corrosion. SiN failure is due to cracking due to the CTE mismatch.

fujitsu 3

EVG

Thorsten Matthias reviewed EVG solutions for interposer manufacturing.

EVG 1

Of special interest was his review of the work of GaTech and Zeon looking at the insulation of interposer TSVs with polymers instead of oxide. Oxide liner is usually less than 1μm thickness and the cost scales with thickness whereas polymer liners can be much thicker and the cost is independent of thickness. The GaTech simulations show the polymer liners will give superior electrical performance. FEA shows the polymer liners should show a Reduction of thermal induced mechanical stress.

EVG proposes spray coating as the technique to get the TSV insulated with polymer as shown below. EVG wafers were processed on an EVG NanoSpray coater with JSR Micro WPR 5100 positive resist and BCB for polymer insulation.

IFTLE notes that cross sections were shown for 40um dia TSV but not for the more common 10 x 100um TSV.

EVG 2

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 193 SEMI Singapore Part 2: SPTS and STATSChipPAC

By Dr. Phil Garrou

At the recent 2.5/3DIC Forum at SEMI Singapore Dr. Surya Bhattacharya, Director of Industry Development (TSV) at, A*STAR Institute of Microelectronics chaired the day long session looking at the state of TSV technology. Let’s take a look at some of these presentations.

SPTS

SPTS updated attendees on their endpoint controlled “via reveal” etch process. As we know, via reveal involves the following process sequence:

SPTS 1

The SPTS Rapier module has their “ReViaTM” in-situ end-point detection technology which they claim increases throughput and yield.

SPTS 2

STATSChipPAC (SCP)

The SCP presentation looked at “2.5/3D Integration: Moores Law and Beyond.” One message here is that 2.5/3D is not a cure all. As we have seen SCP present in the past, they conclude (and IFTLE concurs) that the right packaging solution must be chosen based on the requirements of the unique opportunity. We have seen the figure below before, but it is worth showing it again.

SCP 1

For instance, comparing 2.5D to an eWLB solution:

SCP 2

SCP reiterated that they see their position in the infrastructure as mid end and back end of line.

SCP 3

Their work with UMC which was initiated in 2012 has taken structures such as wide IO memory on Aps processors through reliability with positive results.

SCP 4

SCP has demonstrated MEOL (mid end of line) and BEOL process capability for 2.5/3D TSV with hand-off between foundry and OSATs.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 192 Semi Singapore: Review of SEMI 3DIC Standards Activities

By Phil Garrou

IFTLE has said many times that it will be impossible for a complicated technology like 3DIC to ever become commercial without standardization. SEMI has been working on this now for 3+ years . Lets take a look at their recent update from their SEMICON Singapore presentation.

Semi 3DIC standard Activities

Semi updated their 3DIC standards activities in late 2010 with the following structure:

semi 1

So far, they have published the following standards:

SEMI 3D1-0912, Terminology for Through Silicon via Geometrical Metrology

– Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services.

– The purpose of this Document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).

SEMI 3D2-1113, Specification for Glass Carrier Wafers for 3DS-IC

– This Specification describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state;

– Methods of measurements suitable for determining the characteristics in the specifications indicated.

SEMI 3D3-0613, Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames

–Address the methods for shipping thin wafers on tape frames.

SEMI 3D4-0613, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks

– Control of bonded wafer stack (BWS) thickness, total thickness variation (TTV), bow, warp/sori, and flatness metrology, is essential to successful implementation of a wafer bonding process.

– This std provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.

SEMI 3D5-0314, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through- Silicon Vias (TSVs) in 3DS-IC Structures

– This std assists in the selection and use of tools for performing measurements of geometrical parameters of an individual TSV (through-silicon via), or of an array of TSVs.

SEMI 3D6-0913, New Standard: Guide for CMP and Micro-bump Processes for Frontside Through Silicon Via (TSV) Integration

– This std provides a generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump.

SEMI 3D7-0913, New Standard: Guide for Alignment Mark for 3DS-IC Process

– Photo alignment mark configuration is the key to ensure consistent and precise alignment of layers, chips and wafers.

– This std provides an alignment mark strategy for chip to chip, chip to wafer, and wafer to wafer stacking.

NA Task Force Overview

Bonded Wafer Stacks -– Create and/or modify specifications that reflect bonded wafer stacks parameters and the wafer bonding process.

Inspection & Metrology –  Develop standards for metrology and inspection methods to be used for measuring TSV properties, bonded wafer stacks, and dies used in the 3DIC manufacturing process.

Thin Wafer Handling – Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro-pillar Grid array -MPGA) used in 3DIC high-volume manufacturing (HVM).

Taiwan 3DS IC Testing Task Force

• Design for Test (DfT) such as test structures and placement

• Test methodologies such as contact method and test procedures

• Test fixtures such as probe card and probe interfaces

Taiwan 3DIC Middle End Process Task Force

• Develop criteria for micro-bump dimensions, planarization and related. Dimensions can be determined into wafer-to-wafer level (WWL), die-to-wafer level (DWL), and die-to-die level (DDL).

• Develop criteria for TSV CMP process and related. (Via size, via surface roughness, post CMP Cu step height, and post CMP Cu bump planarization uniformity)

• Develop standard for photo alignment mark and overlay mark. Alignment marks for patterning TSVs and stacking devices/wafers would be standardized for recognition.

• Suggest wafer or die thickness variation and warpage before and after MEOL and identify thickness variation, void size, overall void percentage of temporary bonding glue layer, warpage control after temporary bonding and corresponding measure method.

• Develop TSV quality criteria such as thickness uniformity, TSV depth variation, void, pattern density, TSV metal extrusion.

Japan Thin Chip Handling Task Force

The Thin Chip Handling TF aims to develop standards for carriers such as chip trays for reliable handling and shipping of thin chips and dies used in high-volume 3DIC manufacturing.

• Test Method for Measurement of Chip (Die) Strength by Mean of Cantilever Bending was submitted

For more information, please visit the SEMI 3DS-IC Google Site: https://sites.google.com/a/semi.org/3dsic/

More from SEMI Singapore in next weeks IFTLE.

For all the latest in 3DIC and Advanced packaging, stay linked to IFTLE…

IFTLE 191 ITRS Echoes Dylan “The Times They are a-Changin’ ”

By Dr. Phil Garrou

For several years now through PFTLE (in Semiconductor Int) and IFTLE  (in Solid State Technology) I have been mimicking Kareem Abdul Jabbar’s role as the street preacher in Stephen King’s “The Stand.” For those of you who have not seen the movie (or read the novel) he marches through Times Square ringing a big cow bell and wearing a sign reading “The End is Near.”  He is predicting the end of the world as we know it due to a plague released by a secret Government lab. No one believes him, but soon, as they all begin die, we become aware that he was correct.

Homer Simpson mimicking the Jabbar scene in The Stand.

Homer Simpson mimicking the Jabbar scene in The Stand.

I have not been predicting the end of the world, but rather the end of electronics as we know it, i.e relying on CMOS scaling. Similar to my economic prediction that the stock market will “soon” fall, sooner or later I will be right.   Therefore, it was with great anticipation that I perused the 2013 ITRS roadmap that was released a few weeks ago. Would they try to ignore what is happening or would they face the issue head on like the poet of my generation Bob Dylan who in 1964 released “The times they are a-changin”. I am happy to tell you they are facing the challenges head on although the ultimate solutions are, as we might expect, not yet crystal clear.

The 2013 ITRS Roadmap

The ITRS for those of you not familiar with the group  is jointly sponsored by the US, Taiwan, European and Korean SIA and the Japanese JEITA (Japan Electronics and Information Tech Industry Assoc)  so they are certainly “mainstream.” Hundreds of technologists from around the world staff the dozens of committees that every few years update where the semiconductor industry is going.

A quick look at the Exec Summary gives us a good understanding of the theme for this update “The ever changing environment.” They contend that the Semiconductor Industry, born in the 70s, had two main goals: (1) providing cost effective memory devices with pin-out and functionality standardization and (2) application specific integrated circuits (ASICS) that required specific functionalities to realize novel products.

Classical Scaling

In the 80s system specifications were in the hands of the system integrators. Through scaling, semiconductor technologies were introduced every three years by memory devices and were subsequently adopted by makers of logic devices. In the 90s continued scaling allowed logic and memory IC manufacturers introduced new technologies every two years and substantial part of the control of system performance and profits moved into the hands of IC manufacturers. This period of ~25 years can be called the Era of “Classical Scaling.”

Equivalent Scaling

In the late 1990’s we began to see technologies such as strained silicon, high- κ /metal-gate and multigate transistors be used to further improve device performance. This second Era known as the Era of  “Equivalent Scaling” That can be seen in the figure below [ this is not in the ITRS roadmap, IFTLE added it to strengthen the point]

191-fig 2

3D Power Scaling

Because 2D scaling will eventually reach fundamental limits, both logic and memory are now exploring the use of the vertical dimension (3D). Increase in the number of transistors per unit area will eventually be accomplished by stacking multiple layers of transistors. The combination of 3D device architecture and low power device will usher the (Third) Era of Scaling, “3D Power Scaling.”

System integration has shifted from a computational, PC centric approach to a mobile communication approach.

The heterogeneous integration of multiple technologies in a limited space (e.g., GPS, phone, tablet, mobile phones, etc.) is now the main goal of any design from a performance driven and reduced power driven approach. In the past performance was the only goal; today power consumption drives IC design.

The foundation of heterogeneous integration relies on “More Moore” (scaling) devices with “More than Moore” elements that add new non CMOS functionalities that do not typically scale or behave according to “Moore’s Law.”

Unfortunately the sections of the report that are of the most interest to IFTLE namely back-of-the-line “Interconnect” and “Assembly & Packaging”  are evidently not completed (or cleared for publication) yet. So discussion of those sections will have to wait. We have been given a glimpse of the packaging and assembly challenges in the table shown below.

packaging challenges

The full report (all that has been released thus far) can be found here [link]

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 190 TSMC Focus on Packaging; Samsung Licenses “3D” to GF; More on IBM and the Cloud

TSMC Packaging Plans

Digitimes reports that  TSMC plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016 [link] . Based on this roadmap, TSMC would  become the 3rd leading  packaging company in Taiwan by 2016, trailing  only ASE and SPIL.

At the TSMC NA Technology Symposium April 222nd in San Jose,  TSMC described a wide range of  packaging offerings including  an integrated fan-out wafer level packaging (InFO-WLP) process which will start production by the end of the year and  an InFO PoP configuration which will enable stacking a wire-bonded multi-die package on top of an InFO-WLP. They also have a more standard WLCSP ( Wafer-level Chip Scale Package) that  will support devices with up to 800 pins.

Samsung licenses 3D chip manufacturing tech to GlobalFoundries

As I headed out of town to spend Easter with the grandkids last week, my phone pinged me with the following Reuters headline. “Samsung licenses 3D chip manufacturing tech to GlobalFoundries to win more orders” [link]

“Wow that’s great” I thought as I boarded the plane. A few hours later, now in Houston, I turned on my phone and quickly found the article. Down in paragraph three we find that they call their 3D technology “finFET.” Nothing in this article was incorrect and it’s not like we are the only community who are allowed to use the term 3D, but it sure does make things confusing. Recall the EE Times headline in 2011 “TSMC May Beat Intel to 3D Chips” where 3DIC was unknowingly being compared to FinFet. [See IFTLE 62, “3D and Interposers – Nomenclature confusion; Equipment Market Shift to Pkging Continues”]

Glad to report that EE Times learned its lesson and this time came out with a more appropriate headline than Reuters namely “Samsung, Globalfoundries Prep 14nm Process” [link]

 

More Info on IBM and the Cloud

IBM just reported its lowest quarterly revenue in 5 years on Wednesday as Reuters reports “…the company struggles with falling demand for its storage and server products.”[link]

We have recently discussed IBM semi business being for sale and their proactive move into the “cloud” space [ see “IBM Continues to evolve: Semi business up for sale, moving into the clouds”]

Revenue from their hardware business, which includes servers and systems storage, felled 23 percent to $2.4 billion. IBM warned that the hardware business may continue to face issues with their CFO commenting, “As we look to the balance of 2014, …our overall revenue growth will be impacted by the challenges in our hardware business.”

IBM has also lost its position as number two software make behind Microsoft Corp. with Oracle recently claiming that position.

IBM

As IFTLE has told you, IBM looks like they are betting the farm on cloud computing which allows their customers to stop using (and replacing) servers by moving to remote data centers run by 3rd party companies. They have recently bought two companies to expand their cloud business, Silverpop, a developer of cloud-based marketing software, and cloud-based database software startup Cloudant.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 189 IMAPS DPC Part 3: FCI, GF/Amkor; Corning; Namics

By Dr. Phil Garrou, Contributing Editor

Flip Chip Int (FCI)

FCI and Suss Microtec examined the use of lasers in the manufacturing of WLP.

Commercial dielectric via formation today used in WLCSP, RDL and flip-chip products typically rely on standard photolithography processing using stepper and 1x aligner equipment and processes.  Interest in using laser via drilling (ablation) centers on the following reasons.

- Reduced via dimensions

-  Simplified process flow

- Reduced process time

- Cost reduction

- Enable a broader range of  dielectric materials (i.e., non photo dielectrics and mold compound)

- Eliminate organic solvents used in many pholithography process

FCI 1With PBO via dimensions as small as 7.3um are demonstrated on PBO with an application desired sidewall angle around 60 degrees. Sidewall angles can be adjusted by changing the laser fluence and other settings.

- Higher fluence: Steeper wall-angle

- Lower fluence: Shallow wall-angle

Underlying metals (> ~1µm) can be used as a laser stop for via formation. By controlling the fluence and other settings the process has the ability to also stop at a certain depth in the dielectric without a metal backstop.

Since laser via ablation can produce smaller via dimensions compared to standard photolithography methods, using a laser via ablation technology can improve the design rules for next generation RDL layouts.  In addition, the ability to utilize non-photosensitive organic dielectrics can enable better mechanical and thermal properties as the bump diameter and pitch shrink, improving end product reliability.

Global Foundries / Amkor / Open SIlicon

GF, Amkor and Open Silicon described their 2.5D ARM dual core product demonstrator which consists of 2 ARM die on a high density  silicon interposer. A schematic of the module and he process flow are shown below . It was noted that “…extensive UF material development was needed”  for the u-bump pitches that were used. A cumulative yield of 93.7% was achieved.

GF 1-1

They used the following assembly flow:

GF 2

Corning

Corning is beginning to show results of the multiple glass interposer programs they have instituted at sites such as RTI in RTP NC, GaTech and ITRI. One interesting proposal from Corning is that starting with 100um glass substrates should eliminate the need for backside grinding  for via reveal . The 100um “Willow glass” with TSV is temp bonded to another glass layer  and the TSV are filled . The interposer “panel” or wafer is then removed from the temp bonding substrate.  It will be interesting to learn exactly how that is done (both the metallization and the release).

Work with RTI is showing the filled TGV can survive ( defined as less than 15% increase in initial resistance) greater than  700 thermal cycles of -55 to 125 ˚C and 20 x 20 arrays of TSV on 100um pitch are showing > 99.9% yield.  The RTI team has also begun to show assembly of chip to glass using copper pillar bump technology.

Namics

Namics is developing their underfill products to meet the following roadmap for FC BGA and FC CSP.

Namics 1

Underfill materials can be classified as follows:

namics 3

Their FEA modeling shows that Cu pillar and lead free bumps require a higher Tg underfill to protect from bump fracture during TCT, however low Tg may can assist with warpage, delamination and failure.

Modeling also showed that stress on low K of the IC is increased when using fillers that show filler separation (settling).

Underfill void elimination can be reduced by either using  vacuum assisted CUF  or curing in pressure oven.

namics 3 Untitled

For all the latest in 3DIC and advanced packaging technology, stay linked to IFTLE…

 

 

IFTLE 188 IMAPS Device Packaging Conf Part 2: AMD, SCP

Continuing our look at the recent IMAPS DPC with several key presentations.

AMD

AMD’s keynote presentation by Bryan Black updated us on their thoughts about “Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!”

As we have discussed on IFTLE many times, Black agrees that future nodes will NO LONGER bring down transistor costs which has been a longstanding premise of Moore’s Law.

AMD 1

Die Stacking Motivation

  • Process complexity is increasing and yield is dropping as mask count increases
  • Large die sizes will continue to have yield challenges

AMD 2

Black adds that die partitioning is challenging and there is significant microarchitectural research to be done since the buss to connect partitioned chips is very complex.

As we heard from Hynix at the RTI ASIP conference in December 2013 [see “AMD and Hynix announce joint development of HBM memory stacks,” the first generation of Hynix high bandwidth memory is now sampling.]

AMD 3

This results in a 3X improvement in bandwidth per Watt.

AMD 4

Black envisions silicon interposers replacing SoC for high end platforms in the future.

AMD 5

Black announced that AMD AND Hynix were looking for partners to begin immediate development of such products.

STATSChipPAC (SCP)

In an attempt to expand the usage of their eWLB technology, SCP announced FlexLineTM as a “breakthrough manufacturing method for Wafer level packaging”.

Tom Strothmann of SCP pointed out that OSATS have traditionally been forced to use wafer processing equipment sets for both 200 and 300mm wafers, that typically have higher cost and capability than needed.

Currently, separate equipment sets are required to manufacture WLCSP from 200 or 300mm wafers whereas the FlexLine process allows them to be manufactured on the same equipment set.

The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process [ see IFTLE 124, “Status and the Future of eWLB…”]. Single and multi die fan-out package solutions have been in HVM since 2009 with more than 500MM units shipped. SCP eWLB have passed all standard component and board level reliability tests.

FlexLine uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.

fig 2 SCP

The following 2D/2.5D products can be fabricated on the same FlexLine using a  standard process flow.

fig 3 SCP

Process Flow:

- Dice the wafer to dimensions slightly larger than nominal die size

- Process through reconstitution, redistribution and ball drop

- singulate removing the mold compound from the side of the die and reducing the die size back to the nominal size

To create an encapsulated WLCSP (eWLCSP):

- Dice the wafer at nominal die size

- Process through reconstitution, redistribution and ball drop

-Final singulation is done larger than the die size, leaving a protective layer of mold compound on the sides of the die

- The end product here  is a e-WLCSP that cannot be made with conventional WLCSP processes

Strothmann indicates that SCP COO studies conclude that the added cost of reconstitution is offset by the larger panel size that is processed. CTO BJ Han adds “…with FlexLine we are able to help our customers achieve at least a 15-30% cost reduction using the optimum design requirements for their WLCSP devices.”

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

 

IFTLE 187 More IBM rumors; Altera FPGAs, IBS Addresses Transistor Costs, ASE / Inotera 3DIC JV

IBM Semiconductor

According to the Wall Street Journal GlobalFoundries (GF) “…has emerged as the leading candidate to buy IBMs semiconductor operations.” [link]  According to these reports IBM who initially asked for $2B has met with TSMC, Intel and GF. The reports continues that  and that TSMC has dropped out of the bidding which exceeded $1B but appears contingent on how much intellectual property IBM includes.

IFTLE readers already knew that GF was the lead candidate [ see “IBM Continues to evolve: Semi business up for sale, moving into the clouds”]. Maybe the WSJ is reading IFTLE ??

Intel / Altera / TSMC

Recent reports indicate that Altera had expanded their foundry deal with Intel to include “multi-die” devices that combine Altera’s Stratix 10 FPGAs and SoCs with DRAM, SRAM, ASICs, processors, and analog chips in a single package.” [link]

This announcement left some in the industry confused.

Let’s review some background…

Recall in March 2012 Altera announced that they were working with TSMC on 2.5D FPGA program (much like their already commercial competitor Xilinx). [“Altera and TSMC Jointly Develop World’s First Heterogeneous 3D IC Test Vehicle Using CoWoSTM Process”]

Then in Feb 2013 Altera announced a foundry agreement with Intel to access their 14nm technology for FPGA production, probably meaning no need for 2.5D.

[see IFTLE 170, “GIT Workshop Debates Substrate Impact on 2.5/3DIC Costs; Altera 2.5D” ]

…but then, in Feb 2014, Intel announced the 14nm technology program was being postponed to 4Q2014/1Q215  [“Intel postponed Broadwell availability to 4Q14”].

…and then there were reports March 5th 2014 that Altera was “… expected to have TSMC fabricate its next-generation FPGA chips using TSMC’s 16nm FinFET+ process, instead of producing the chips using Intel’s 14nm tri-gate transistor technology”

So, I hope that is now clear (tongue-in-cheek) …

IBS

Those of you that stay linked to IFTLE know that I have been quoting Handel Jones of IBS for years (literally since 2009) since his analysis of what is happening to the economic infrastructure Re: Moore’s Law makes the most sense of anyone out there. The article he just wrote for EE Times, “FinFETs Not the Best Silicon Road” should be of interest to us all.

His premise is that semiconductor industry growth has historically depended on a reduction in cost per transistor but next-generation chips will not deliver this cost reduction. While next-generation 20nm bulk CMOS and 14nm FinFET process will deliver smaller transistors they will have a higher cost per gate than today’s 28nm bulk CMOS.

IBS 1

Cost will remain higher even as the processes mature.  IBS predicts that the traditional cross-over point for the newer generation technology will not happen  (point at which newer not becomes cheaper, per transistor, than older node. The cost per gate for 28nm bulk CMOS will be much lower than FinFETs even in the fourth quarter of 2017. A similar pattern will occur for 20nm bulk CMOS in 2018 or 2019 when depreciation costs decline.

IBS 2

Jones indicates that the 20nm node issues include:

- difficulty achieving low leakage due to challenges in controlling doping uniformity

- line edge roughness

- the need for double patterning

The 16/14nm FinFET node:

- uses the same interconnect structure as 20nm, so the chip area is only 8-10% smaller than 20nm

- faces yield issues related to stress control, overlay, and factors related to the step coverage and process uniformity of 3D structures.

Jones concludes that “..FinFETs can be used for high-performance or ultra-dense designs but are not cost effective in mainstream semiconductors “

ASE, Inotera reportedly to set up 3D IC packaging joint venture

Digitimes has reported that ASE and Inotera are reportedly setting up 3D IC packaging joint venture for handling TSV 3D IC packaging. ASE and Inotera are expected to finalize the deal soon, said the sources, adding that the joint venture is likely to be set up either at a Inotera’s idle plant or at a ASE plant in Chungli, Taiwan.

Initial production goals are reportedly 10,000 3D IC chips a month,  and should include Aps (application processors) and mobile RAM chips.

DIgitimes sources add that they expect the JV  to compete with TSMC in the 3DIC packaging sector.

Inotera, incorporated in 2003, is a joint venture between Nanya Tech (an affiliate of the Formosa Plastics Group) and Micron.

Inotera has two 300mm fabs with a combined capacity of approximately 120 thousand wafer starts per month providing 300mm DRAM foundry services. According to the supply agreement between Inotera and Micron Technology, Inotera sells substantially all of its manufacturing output to Micron.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 186 IMAPS Device Pkging Conf: Qualcomm, Prismark

This year’s IMPAS Device Packaging Conference in Ft McDowell, AZ had a series of excellent keynote talks. We’ll first take a look at some of those and then look at several key presentations from the conference.

Qualcomm

Steve Bezuk, Sr. Dir. of Package Engineering for Qualcomm discussed “challenges and directions in mobile device packaging”. Qualcomm expects 7 billion smartphone units to be shipped between 2012 and 2017.

Handset thickness continues to be reduced and is now approaching 6mm. Since the battery and the screen are not shrinking chip packaging and the substrate board must make up the difference. Most of these packages are FC and WLP. Bezuk commented that 5 years ago very few of the packages were WLP but now this category accounts for near 50% of the packages IC.

Molded FC die on thin core or coreless substrates are approaching 750um thick and warpage issues are becoming significant.  Warpage is dependent on :

- core thickness, CTE and modulus

- EMC thickness over die

-  die thickness (ratio of Si/EMC).

Solder balls have become a significant fraction of the total package height.

qualcomm 3

Tighter pitch requirements ( < 140um) have necessitated  a move to copper pillar connections which in turn need thermocompression bonding to overcome warpage/flatness issues in such structures.

Thinner packages require thinner EMC above the die which results in increased warpage and requires EMC with higher mold shrinkage and higher modulus.

qualcomm 4

Bezuk reports that typical HVM substrate properties in 2014 are as follows:

Current 2014 HVM

Patterning Method (µm)

SAP (15/15)

Min FC pitch (µm)

40/80

Core material CTYE (ppm)

3

Decouling solution

Embedded caps

Buildup dielectric

Prepreg, ABF

Having reached a core CTE of 3, reduction in substrate core CTE is no longer an option so the industry is turning to develop materials of increased modulus.

Bezuk proposed that the next move (time undefined) will be from today’s FC PoP structures to 2.5/3D moving first to wide IO DRAM on logic and next to logic-on-logic. Although he added that there was no clear infrastructure answer for where interposers will be coming from.

Prismark

Brandon Prior of Prismark continued on the theme of “Mobile packaging and Interconnect trends.” Their analysis of the Apple 5S smartphone confirms the Qualcomm comments about increased use of WLP as can be seen in the fig below.

prismark 1

Despite all the talk about high density laminate technology approaching < 5um L/S, Prior indicated that the Apple 5S was the first device to use 50um L/S and CSPs on a 0.4mm pitch. It is also interesting that caps continue to shrink. 01005 is 0.4 x 0.2 x 0.13mm which is extremely hard to assemble.

The Apple A7 processor is packages in PoP with the memory package being 1Gb of LPDDR3. The substrate has 27um L/S and 150/170um bump pitch. Memory chips are Ag WB which is a lower force assembly process than Cu WB. While these memory chips are still WB, Prismark stated that they expect performance DDR to go FC at the big 3 memory suppliers and expect 5B units shipped by 2018.

prismark 2

Prior showed the following application processor roadmap for phone/tablet low end vs high end products.

prismark 3

Transition to 0.4mm packages

FBGA and WLP are in high volume production at 0,4 and 0.35mm pitch. Wafer CSP moving to 0.3mm and below. Prismark forecasts > 28% of CSP/WLCSP to be 0.4mm or less by 2018.

prismark 4

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IFTLE 185 Lecturing the Packaging Community on Nomenclature

The word “lecture” is one of those wonderful English words with multiple meanings. Lecture can mean “a talk or speech given to a group of people to teach them about a particular subject,” but it can also mean “a talk that criticizes someone’s behavior in an angry or serious way.” In IFTLE 185, lecturing means both!

Those of you that are regular followers of IFTLE know that every once-in-awhile, I’ll stop reviewing the latest technology presentations to try to bring home a point. The latter is necessary right now.

Some may call this one of my “rants” but the online dictionary defines a rant as “…an argument fueled by passion and not shaped by facts.”  I can assure you this rant will be shaped by both passion and facts.

What triggered IFTLE 185 was a panel session held at the recent IMAPS Device Packaging Conference in Ft McDowell AZ. A good panel session experts discuss controversial topics but that is not exactly what happened here.  This panel session degraded into a school yard verbal battle (panel members and audience) over what certain terms mean. If you really want to follow the chronology of the discussion you can here [Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel].

It is simply amazing that the assembled group of technical practitioners could not agree on what certain packaging terms mean but….they couldn’t. At first I chose to sit quietly in the audience amused at the miss speak…but then… my good friend Bob Patti, a panel member,  spotted me in the corner of the room and called me out …” Phil what do you think “…it was at that point , no longer able to hold back, that I unleashed my tirade […a long angry speech of scorn and criticism…]

Let me attempt to articulate my position on several of the topics that came up that night …

INTERPOSER – for some reason, be it ignorance, youth or a combination of both, some in the audience continue to believe that the term interposer was invented for 2.5D.

All 1st level packages are interposers, The purpose of an interposer is to spread a connection to a wider pitch. Interposer comes from the Latin, interpōnere, meaning “to put up between.” A BGA substrate is an interposer ! This is clearly shown in the Infineon slide that they have been showing for nearly 20 years.

infineon 2

SYSTEM-in-PACKAGE – there was mass confusion on what this meant and what is included in this definition. Several experts felt that 2.5/3D were NOT included in the definition of SiP. I think some of these disagreements come from the fact that corporations do not divide things up in their business units based on definitions so all things SiP may not be in the same business unit and this influences their thinking.

In the 1990s multiple chip packages, MCMs as they became known, were sets of chips that were connected on high density Si, laminate or ceramic substrates by WB or C4. In the early 2000’s it became vogue to call these system-in-package as industry focus became delivering functions for portable devices in separate modules. Need more history on MCMs try the Multichip Module Technology Handbook [link] which Iwona Turlik and I edited in 1998.

Let’s look at another Infineon slide, below. Whether its side by side, stacked, through hole or embedded, these multiple chip solutions are all versions or categories of SiP.

Infineon 1

2.5D, 2.1D and 5.5D: Please stop the madness!

3D packaging defines the various ways of stacking chips in the z direction whether it be WB them to a common substrate, package-on-package stacking, embedded chip stacking (in laminate or EMC ) or direct connection with TSV.

The term 2.5D is usually credited to ASE’s Ho Ming Tong who ~ 2009 (or even earlier)  declared  that we might need an intermediate step towards 3DIC since the infrastructure and standards were not ready for 3DIC stacking yet.  Tong felt the silicon interposer would get us a major part of the way there, and could be ready sooner than 3DIC technology.  He used the term 2.5D, which immediately caught on with other practitioners. Tong was not trying to create a new nomenclature, he was making a joke that we were not ready for 3D but this silicon interposer with TSV would get us close. He actually got laughs when he called it 2.5D at the RTI ASIP conference fall of 2009.

We are now starting to hear the laminate community use the term 2.1D for high density laminate and some in the silicon interposer community using the term 5.5D  for a 3D memory stack on an interposer. To all this, all I can say is “STOP – Enough-is- enough…it’s no longer funny..”

At one point during Bryan Black’s AMD talk at the conference he said “3D” and the audience interrupted him to ask whether he meant 2.5D. His response was something like “Oh yeah…well they both mean the same thing to me..” meaning we are talking about stacking technology with TSV.  Bryan is correct!

LARGE AREA PROCESSING (LAP)

LAP is being held out as the solution to everything that is not economical these days. FOWLP not low enough cost to break into commodity applications ? …don’t worry we’ll use LAP and the price will come down. Glass interposers not looking like the price will be low enough for mobile products?…don’t worry we can manufacture on LAP lines and the price will come way down.

Certainly our microelectronics educations have taught us that larger usually means cheaper, i.e. chips from 300mm lines ARE cheaper than the same chips from 200mm lines. This is true as long as the equipment and technology is available to give you high yields, i.e. see the current 450mm situation.

My point to the audience was that PCB are made in large panels because they can be…higher density BGA substrates are made in much smaller strips because they have to be!

I actually have hands on experience at what we called LAP back in 1995-1997, as we had a major DARPA contract to try to manufacture MCM substrates  on a sq 400mm format. Check out my chapter “High Density, Large Area Processing (LAP) in the Multichip Module Technology Handbook [link]. By the way our program with MMS and others to manufacture high density MCM substrates made for a great magazine cover (see below)…too bad it didn’t yield!

LAP

Do I think that pursuing high density LAP is a worthy R and D goal ?…certainly, lets just not act like it will be easily accomplished.

Other problems with today’s nomenclature?? Let me know …

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE !