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IFTLE 344 ECTC 4: Reliability Studies of 2.5/3DIC – Cisco, Infineon, Siliconware

By Dr. Phil Garrou, Contributing Editor

Continuing our look at presentations from ECTC 2017.

Cisco – Challenges of 2.5/3D

Li Li of Cisco gave a nice presentation concerning “Reliability Challenges in 2.5D and 3D Integration”

Compared with traditional 2D IC packaging, the emerging 2.5D and 3D IC integration involves several new elements in design, manufacturing and supply chain processes. These new elements include:

cisco 1


Let’s focus on one area that Li discusses that has for the most part gone under the radar since it is usually not addressed by back end practitioners – gettering. For further info on this topic IFTLE refers you to the work of Koyanagi and c0- workers at Tohoku Univ who have studied the impact of copper contamination on memory retention.

The devices formed from the thinned silicon wafer are more easily affected by metal impurity contamination and crystal defects. Because the Intrinsic Gettering (IG) region and the Extrinsic Gettering (EG) layer in the silicon substrate for gettering metallic contaminants are removed during the wafer-thinning process for the 3D IC fabrication. Potential Cu contamination from Cu TSVs is another concern that can further degrade the device reliability if the barrier for the Cu TSV is not designed and fabricated correctly.

Fig. 2 shows schematically the effect of IG layer and the potential risk of metal (Cu, Au, etc.) contaminants diffusing into the active region and cause device degradation.

cisco 2

Intel has reported Cu contamination from die backside causing high pin leakage after Unbiased Highly Accelerated Stress Testing and High Temperature Storage testing. To prevent Cu contamination from backside, an Ar ion implantation for Cu gettering and a SiN barrier was proposed.

Infineon & Nanyang Univ – Reliability of Copper TSV

Infineon and Nanyang reported on the “Reliability Evaluation of Cu TSV Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis”

The integrity of Ti barrier and SiO2 dielectric liner were evaluated via electrical characterization after being subjected to different stress tests such as high temperature storage, temperature cycling and electrical biasing to detect barrier and dielectric liner degradation in a the structure.

TC -65/150 °C up to 2000 cycles was performed on the structures to study the extent of barrier degradation by thermomechanical stress induced by TC. After electrical biasing, an increase in the inversion capacitance was observed in the C-V curve indicating Cu ions presence in the dielectric liner. It is suggested that the cracks formed after TC stress may have propagated within the Ti barrier. This can eventually lead to the drift of Cu ions into the dielectric liner under a sufficiently high E-field which acts as an external driving force for Cu ions to drift through the degraded barrier and cracks.

Siliconware – Warpage in 2.5D Modules

Siliconware described their “Warpage Study of Large 2.5D IC Chip Module”

SPIL lists four processes for 2.5D IC modules: Chip on Chip, Chip on Substrate, Chip on Wafer first (CoW-first), and Chip on Wafer Last (CoW-last). In this study, CoW-last was studied. CoW_last means the die are stacked on interposer wafer after the interposer is fully processed including frond side u-bump and backside via revealing (BVR), backside re-distribution layer (RDL) and C4 or Cu pillar bumping.

They found that for some specific designs, the area of multiple top dies are smaller than interposer, which produces empty area on interposer. This makes for unbalanced chip module stress and worsens chip module warpage.

Therefore, they propose a dummy die (DAF) structure(s) to fill up empty area on interposer. In this study, two dies are attached on interposer, as shown in the fig below. The thickness is the same as top die thickness.

spil 1

Underfill and molding compound

They found that a method for warpage improvement is to decrease the underfill volume by the design of lower bump/cu pillar height. Generally, high bump height provides the tolerance for warpage compensation because of more solder volume, and also enhance bump stiffness by low modulus underfill.

Assuming there is no reliability effects to low bump height, the underfill during cooling process acts a buffer material for stress releasing, but induces higher chip module warpage. From experimental results, when UF volume reduces 31%, the warpage between chip module and substrate can be reduce 10% at room and high temperature. “To decrease the volume of high CTE underfill really can improve the chip module warpage”. IFTLE reads this as meaning don’t make the bump/copper pillar higher than necessary to achieve the required reliability or it will negatively affect the warpage.

In terms of molding compound, the module with molding compound successfully negates the effects of CTE mismatch and leads to warpage reduction of 87% at high temperature.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 343 ECTC 3: Materials and Processes: Tohoku, Hotachi Chem, Samsung

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2017 ECTC.

Tohoku Univ – Low CTE Underfill

Kino and coworkers at Tohoku Univ presented their data on the “Remarkable suppression of local stress in 3DIC by MnN based filler with large negative CTE”.

Generally, CTE of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips, as shown in Fig. 2 below. Such local bending stress would affect transistor performance in thinned IC chips. Kino found that they could suppress the local bending stress by decreasing the CTE difference between the underfill material and the microbumps.

tohoku 1

In general, silica, is usually used in underfill material to reduce the CTE of underfill material. A high concentration of filler is required to reduce CTE as low as metal microbumps. However, it is difficult to use the conventional filler for 3D IC with fine pitch microbumps since a high concentration of filler in underfill material increases the viscosity. They propose to use negative-CTE material as the underfill filler to suppress the local bending stress. They used manganese nitride-based material which has large negative-CTE of -45 ppm/K at the temperature from 65 to 100°C. Results indicate that negative-CTE filler can suppress the thinned Si chip bending more than 50% compared with SiO2 filler. 

Hitachi Chemical – Expanding Film for WLP Sidewall Protection

Honda and co-workers from Hitachi Chemical discussed “Expanding film and process for high efficiency 5 sides protection and FO-WLP fabrication.”

WLP is well suited to mobile devices which require small, thin and light bodies. Fan in WLP (FIWLP) is fabricated by building up redistribution dielectric and metal layer on device wafer and attaching ball, and then it is diced to singulated packages. Device semiconductor die sides are exposed in such a FIWLP. The FIWLP fabrication process needs a wide die gap between die for molding compound and to dice, while leaving the molding compound on the die side wall for the protection.

To get the greater productivity and enhance the usage of the device area in the wafer, an expandable film and a novel process have been developedas shown below in fig 2. The film / process can also be applied to a die first type FO-WLP fabrication. Elimination of the die re-placement step can make the FO-WLP fabrication process simpler and less costly.

hitachi 1

The 5 sides protection fabrication process is composed of 7 steps as illustrated in Fig. 2. The

expanding film with diced-wafer was put on the expander and the film expanded. After that the film is fixed to the grip ring , the film is cut out along the outer rim of the ring. After the singulated dice were transferred to the carrier with keeping the expanded die gap, the grip ring was removed. Then the expanding film was removed from the carrier. After over-molding, the molded wafer was singulated by dicing and 5 side protected packages were obtained.

The stress-strain curve of the film was optimized so that the die gap becomes large. Moreover, the die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap after expansion, the standard deviation was about 0.05 mm. Furthermore, the film was applicable to die sizes 1 mm × 1 mm, 5 mm × 5 mm and 10 mm × 10 mm.

Samsung – Compression Molding Encapsulants for FOWLP

Kwon and co-workers discussed “Compression molding encapsulants for wafer-level embedded active devices”. Challenges that FOWLP packaging technology is confronted with include wafer warpage, die shift/protrusion, and board level reliability. A solution to wafer warpage is considered crucial for successful subsequent wafer processing.

They propose to use a bilayer test structure with silicon wafer and epoxy molding compound as a standardized evaluation vehicle. Each layer is 300 μm thick. To further standardize testing, the molding conditions are fixed at 135 °C x 600 sec with a post mold cure of 150°C x 2 hrs. By standardizing the test vehicle and processing conditions, warpage behavior between mold compounds can be directly compared, and any observed differences are solely caused by the EMC.

Various parameters influencing wafer warpage were screened by the simulated calculation. Among all these parameters, Young’s modulus, CTE, and Tg have a significant effect on the controlling warpage. Generally, wafer warpage is reduced by lowering the Young’s modulus and CTE, and increasing the Tg. Although concurrent optimization of Young’s modulus, CTE, and Tg of a mold compound’s properties is very difficult because of tradeoffs for modifying each component, they developed new compression molding compounds with both low Young’s modulus and CTE, with relatively high Tg.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 342 2017 ECTC part 2: Chip Embedding at Infineon; UCLA SuperCHIPS

By Dr. Phil Garrou, Contributing Editor

So, before we start updating on the latest technologies at 2017 ECTC a quick update on granddaughter Hannah. Long-time readers of IFTLE may recall her early pic from Halloween 2010…


I know this isn’t a sports blog, but be patient with the proud grandpa. This spring, as she approached her 13th birthday and decided to start running track in Jr High. She quickly performed to the point of taking over school records, but really that’s just a little Jr High in Houston the 5th largest city in the USA.

hannah 2

She soon got a call from Track Houston. For those of you who understand USA sports, consider this one of the USAs best AAU track teams. Historically, Houston has won 40 AAU National Junior Olympic championships with Track Houston winning 16 of those. This IS the big time for runners. You can read about them here [link].

Hannah made the 13/14 yr old team and started running against real competition around Easter in the 100m and 400m events. They say a picture is worth a thousand words, so I will leave you with this link to a 24 second YouTube video someone loaded of one of her best races. That’s her in lane 7. If I recall correctly this was run at the Rice Univ track in Houston.

For a guy who grew up playing stickball in the streets of Hell’s Kitchen, all I can say is “You’ve come a long way baby…” 

CHIP Embedding at Infineon

As we said in IFTLE 236 Embedded Packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infrastructure such as FOWLP and (2) those based on a PWB/PCB laminate panel infrastructure.

For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs.

Embedding chips into laminate is a technology that has not quite caught on yet although recent announcements like ASE and TDK’s 2015 agreement for a JV (ASE Embedded Electronics Inc.), based in Kaohsiung, to manufacture IC embedded substrates using TDK’s SESUB (Semiconductor Embedded Substrate) technology are making it look much more commercially likely[link]. SESUB is a high-end substrate technology where thinned semiconductor chips are embedded in laminate substrate with copper interconnection down to 20µm minimum L/S.

At the recent ECTC in Orlando Infineon Regensburg reported on “Laminate Chip Embedding Technology – Impact of Materials Choice and Processing for very Thin Die Packaging”. The laminate embedding process consists of elements from conventional packaging technology followed by PCB process steps and dedicated chip embedding process steps. The process flow shown below is a chips first embedding technology.

Infineon 1

The process starts with die attach on a structured or unstructured copper leadframe. After die attach the copper lead frame is roughened to ensure adhesion of the laminate to the leadframe. Any process induced reduction of copper thickness must be compensated for by providing sufficient layer thickness allowance. Die positions are measured before the lamination process ( die shift compensation), leadframe strips are formed into a panel, laminated with pregreg and terminated with roughened copper sheet . Vias are defined by structuring the outer copper foils (drilling or photolith) . The via filling process consists of > 10 wet chemical process steps (desmear, activation, plating etc.).

Both unfilled resin coated copper (RCC) and highly filled prepreg were tested as laminate. Temp cycling (-55 to 150C) and HTT (150 C) show degredation of the RCC built structures, due both to cracking at the RDL corners and high leakage current.


For previous discussions of this technology see IFTLE 301 “Are Silicon Circuit Boards in our Future?”

In their latest presentation at ECTC, “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme” Subu Iyer and his group at UCLA describe the performance and power benefits of their fine pitch integration scheme on a Silicon Interconnect Fabric (Si IF). They propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet (chiplet) to interconnect fabric assembly. They show dramatic improvements in bandwidth, latency, and power are achievable through such a integration scheme where small chiplets (1-25 mm2) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 µm) and short inter-die distance (50-500 µm) using solderless metal-to-metal thermal compression bonding (TCB).

With fine interconnect pitches (<10 µm), their scheme reportedly can achieve > 5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore they claim the protocol is simple and non-proprietary. They apply the scheme to heterogeneous system integration using a chiplet based assembly method and show significant reduction in design and validation cost.

ucla 1

They see the technology as offering a platform for system scaling. The technology aims at elimination of the use of solder by direct metal-to-metal thermal compression bonding between metal pillars on substrate, to metal pads on the chiplets. This allows them to scale down the interconnect pitch down to 2 -10 μm as the solder extrusion is no longer a limitation. They also remove the packaging of individual chiplets and place the dies directly on the Si IF with inter-dielet spacing of less than 100 μm. Thus, their data links can be much shorter (i.e. 50- 500 μm).

Analysis were done for 2 μm and 10 μm interconnect pitch with pillar diameter being half the pitch and trace width of 1 μm. SuperCHIPS provided a protocol based on fine pitch fine integration of system where the inter-dielet spacing is ~10-20x smaller than the conventional packaged systems on PCB. The fine pitch interconnects provide ~15-80x more number of I/O pins compared to BGA interconnects and ~2- 10x more compared to copper micro-bumps. Table III is presented to show comparison of SuperCHIPS vs conventional packaging:

ucla 2

Their design approach is to partition the system into chiplets that can be heterogeneously integrated on the Si-IF. This chiplet assembly approach allows them to choose heterogeneous chiplets from different technologies, nodes and materials leading to a high probability of chiplet and IP reuse.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 341 Topics from ECTC 2017: Thin Die Handling; IPD on Glass

By Dr. Phil Garrou, Contributing Editor

This week, we will begin looking at key presentations from the 2017 ECTC in Orlando.

General Comments:

There were a total of 335 presentations in 36 oral sessions at this year’s ECTC. Since 2012 attendance is up ~ 50% to 1438 and professional development course attendance is up from 83 to 203! IFTLE feels this follows the trends that we have been sharing with you for years, i.e. scaling is slowing down and more and more front end practitioners are moving to the back end to develop customized products.

This in turn necessitates attendance at packaging conferences such as ECTC and necessitates front end engineers taking the development courses available at ECTC.

I am personally tired of going to Orlando, that probably just a personal preference since I have been attending since 1985. As an aside, if the meeting gets much larger it will have to move to convention sites since current hotels will not be able to fit the group into their ball rooms for lunch.

In terms of technical content, “fan out WLP” has moved into the forefront in terms of the number of papers addressing this topic, but there were still lots of papers addressing 2.5D, interposers, copper pillars, WLP and bumping, thinning, dicing and molding.

BESI – Thin Die Handling

The importance of high yield thin die handling is getting more and more crucial for advanced packaging options. This applies for stacking with wire bonds/die attach film (DAF), and also for TSV ). Besi Switzerland and IMEC addressed this issue in their paper “Key Properties for Successful Ultra Thin Die Pickup”.

Die stress levels during peeling can still be significantly high, and can lead to die cracking or pickup failure. Avoiding high stress levels involves an understanding of the dynamic interaction of die, wafer tape and the die ejection system. From die bonding point-of-view, four key properties are most important for a successful pickup of thin dies, as shown below : bending stress during pickup, die strength, edge peel force and bulk peel force.

besi 1

Starting the peel process at the die edges is the most critical moment during peeling. Dicing should be done in a way, that the heat-sensitive die attach film on the die backside is not affected. Otherwise, an increased adhesion can occur at the die edges.

Besi concludes that multi stage, multi disc or multi pin ejectors are required for proper handling. These are shown in the fig below. Ejectors with finer mechanical structures like the multi disc ejector result in the lowest stress values.

besi 2

For ultra thin dies, UV curing of the adhesive layer after dicing is very common. This method enables high adhesion during dicing (5 – 20 N/25mm), and reducing adhesion for pickup (< 0.2 N/25mm). In general, the bulk peel force is smaller than the edge peel force. In other words, once the die edges have started to peel off, the rest of the die will peel off quite easily.

The speed of moving ejector parts (needles, discs, stages) that activate the peeling process has to be adapted to the wafer foil properties and die thickness. The higher the required peel energy, and the thinner the die, the lower the process speed must be adjusted.

ASE / Marvell – Is it Time for IPD?

As mobile devices become more functional, they are required to accommodate more frequency bands and meet ever smaller form factor requirements. IPD technology (integrated passive devices). IPD offer smaller for factor and higher performance for RF solutions. For filters, high Q inductors are the key. Glass is a good candidate for substrate because of its low dielectric loss, high thermal stability, high resistivity, and adjustable CTE. Glass also provides the advantage for potential cost effective solutions.

ASE Kaohsiung working with Marvell Santa Clara addressed “Glass Based 3D-IPD Integrated RF ASIC in WLP.”

In a glass base 3D-IPD integrated with RF ASIC the glass wafer acts as a bottom wafer, while the ASIC die is flip chip attached to the frontside of the glass wafer. The ASIC wafer comes with the Cu pillar bump.

The process starts with TGV metallization and filling processes, then, carry on the standard wafer level IPD process to complete the frontside structure. The frontside structure consists of capacitor, re-distribution layer (RDL), and under bump metal (UBM). Then, the wafer is shipped to assembly site for wafer level assembly. Wafer level assembly processes are the chip-to- wafer, for the RF ASIC to attach to bottom glass wafer, and wafer level molding process. After assembly, follows by the backside process to form the 3D inductor and ball pad. Backside process includes glass wafer thinning, and backside RDL and passivation processes. Next step is ball mount and singulation to form the WLCSP. The process flow is shown below:

Marvell 1

Reliability tests confirm that results of SAT and open/short are good, and destructive analysis also show no disconnection issue between TGV and double side metal traces. The high-Q 3D inductor performance was verified through measurement results with two port S-parameter measurement methods with the demonstrated Q factor measured above 60 at 1 GHz for a 3.5nH inductor. 

What’s the Required Size for a Real Industry Driver ?

Recent blogs like IFTLE 322 “…A Period of Uncertainty” have led to questions about what would a really big industry driver look like?

As many of you know, I really don’t consult about the size of markets that currently don’t exist simply because I know, as an ex supplier, that no one, and I really mean no one, knows those answers. I could overwhelm you with example after example of markets being projected too large and too early (It always seems to go in that direction…wonder why??)

When we look at our industry and try to anticipate what will come next we are really always comparing to the two big boys …semiconductors and displays. Those are gigantic, albeit mature, electronic industry segments. I would think these would be the benchmark. I obtained some recent numbers from my friends at Prismark for these two segments, just so we could keep things in perspective, and they are:

Total Semiconductor value in 2016 – $339Bn

Total Wafer Fabrication Value 2016 (excludes chip design, test, package, and profit): $129Bn

Total area processed – 8.2M m2

Total Display 2016: $135Bn (The display market is the panel market, not finished TVs, monitors, etc.)

Total area processed – 185M m2

A few years ago many were betting on Solar to join this group but it did not happen. Ask AMAT how that bet worked out for them. My IFTLE take was that any segment that needed to be propped up by Govt support and needed to have its rivals (coal, nuclear, oil) persecuted by the Govt to get their foot in the door, just was not going to make it long term. Don’t get me wrong, solar works, but just no where near the 11cents/KW hr that I buy electricity at now in NC. We all know that in the end “price is king”.

Next in line was / is IoT (the internet of things). Projections for this market have also bordered on astronomical. In 2010, Ericsson estimated that there would be 50B connected devices by 2020. Cisco soon agreed and then Intel been touting the 50B number since 2014.

Recently Ericsson has revised its estimates down to 28B connected devices by 2021, McKinsey believes will be between 20 – 30B devices by 2020 and Gartner says 21B connected devices by 2020. [link]

These numbers are certainly still large enough to be a major driver, but IFTLE is still doubtful of such huge numbers, how quickly we will reach them and more so of IoT’s overall impact on the advanced packaging market specifically.

I can recall being at meetings where 2.5 / 3DIC were being predicted to be instrumental for implementation of IoT. Now that’s when I really knew that exaggeration had gotten out of hand. As IFTLE has said before, maybe some medical applications will allow for high end packaging solutions, but NOT the everyday sensing that most techies are envisioning will generate the massive IoT data in the future. Those will be low cost solutions with the ultimate low cost packaging for sure.

Fear not, electronics isn’t going away, a new driver WILL eventually appear on the horizon and our industry will continue unabated into the future. That I can promise you…

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 340 Can Unity Help Advanced Packaging Progress?

By Dr. Phil Garrou, Contributing Editor

Most would agree that in order for advanced packaging solutions to lead the industry and fill the role previously held by semiconductor scaling it must see advances in infrastructure building and significant focus by all players to lower costs. For sure, this will take total industry unity. With this cheap play on words we are led to todays topic…

A few blogs ago (see IFTLE 332: “Wither Goest the Toshiba NAND business; Unity SC”) we mentioned that Fogale’s semiconductor division had become UnitySC. This week, we’d like to take a closer look at what this means to the advanced packaging industry.

UnitySC launched at SEMICON West 2016

GillesCEO, Gilles Fresques explained through Development and acquisitions the former Fogale has built a solid foundation in both metrology and inspection for the semiconductor and related industries. Fogale metrology technology for advanced packaging applications began with R&D efforts in 2000, followed by commercialization in 2006. They acquired the assets of Altatech Semiconductor from Soitec in 2016, to combine with their 2D and 3D inspection capabilities and metrology offerings, and thus have created a process control package for advanced packaging solutions such as fan-out wafer level packaging (FOWLP), 2.5D interposers, 3D TSV technology, MEMS, and more. UnitySC launched in July 2016, combining FOGALE nanotech Group’s acquired Altatech assets with the former FOGALE Semicon division. Their headquarters are in Grenoble FR and they currently employ > 110 staff, 80% of which are engineers..

For those who wonder about company names, Fresquet, noted that the name UnitySC was inspired by the Unified Yield Equation, which takes parametric data and defect density data to predict yield.

They currently have over 130 systems in the field broken down as follows:

Unity 1

Their technology is basically optical based covering the following:

unity 2

For instance they report that their “shown below TMAP Series” has the following attributes:

unity 3

The slide below shows “nail height deviation across a wafer for 3DIC structures.

unity 4

The following slide shows thickness and TTV measurement across individual layers of a FOWLP stack. The Measurement is performed by TMap Series (Time domain IR Interferometry).

unity 5

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 339 Will 450mm Equipment Keep Si the Fine Feature WLCSP Solution?

By Dr. Phil Garrou, Contributing Editor

On the eve of the formal ECTC presentations, the conference held a panel session pitting wafer processing vs panel processing for the low cost production of “high density” fan out WLP.

“In the left corner representing wafer processing are TSMC’s Doug Yu and Nanium’s (Amkor’s) Stefan Krohnert and in the right corner representing panel processing are Deca’s Tim Olsen and IZM Fraunhoffer’s Rolf Aschenbrenner …the referee for this match, representing user groups, is Qualcomm’s Steve Bezuk……Let’s get ready to rumble…”


Wafers vs panels


Basically the question is: if and when will panel processing tools be fully developed and capable of manufacturing and testing fine L&S (i.e 2um) fan out packages produced in yields similar to silicon wafer lines. If/when this happens, how will silicon foundries counter such results.

Let’s look at some of the key points made by the above parties during this hour plus discussion.

Wafer Processing

– [Yu] InFO leverages his companies core business – i.e Si wafer processing

– [Krohnert] capital for FOWLP is already depreciated whereas there are no panel level processing in place so new capital will have to be expended on newly developed equipment.

– [Yu] Inspection of wafers is a well known process whereas panel inspection has to be developed

– [Yu] technology must be face down so you can package chips of different heights (polish) Face up panel tech cannot do this. …also passives cannot be thinned like chips can be.

– [krohnert] “..a fully loaded high yield wafer line might be cheaper than a partially loaded low yield panel line” he went on to explain that if panel processes FOWLP only reached required yields for low-medium I/O devices there are other ways to manufacture such packages and the remaining “sweet spot” panel business may not be enough to fill panel lines.

– [Yu] landed a solid right to the jaw of his opponents when asked about what the silicon foundry response will be if indeed panel processing is developed and is yielding fine L&S. His response was that TSMC is part of the 450mm development team and although the equipment already developed and purchased by TSMC does not look like it will be processing leading edge node wafers any time soon, such tools and processes could easily be applied for 1-2um features. “This would be low hanging fruit for such tools and processes.” Yu then indicated that a possible plan is to make such a move when they feel the panel processing is ready. He cautioned, though, that this will produce a major oversupply of capacity.

The Referee:

– [Bezuk] the main volume for WLFO is currently for 3-5mm pkgs

– [Bezuk] InFO is currently the thinnest package you can buy today

– [Bezuk] equipment for panels is being developed but having problems like shedding particles during startup which is affecting yield

– [Bezuk] simple FOWLP like codec chips use a single layer of RDL, if multi layer RDL is required FOWLP becomes too costly

– [Bezuk] materials costs for both technologies are ~ 50% of the total.

Panel Processing:

– [Aschenbrenner] panel level processing shows a sweet spot for small-medium I/O devices

– [Olsen] projects a 30% cost advantage for large panel processing

– [Olsen] working with ASE on 300mm round today and panels in the future

– [Aschenbrenner] agreed that panel processing cost reduction will only be achieved when yields are close to the same as for wafers

– [Aschenbrenner] panels appear to need class 100 clean area to achieve yield on fine lines

– [Olsen] agreed that panel equipment is taking a long time to “get clean”

IFTLE concludes that panel processing is still about the “promise” of lower costs. As such it certainly is worthwhile to do the work to find out if this can be put in place.

The major new news item from this panel was certainly TSMC bringing up the potential use of 450mm wafer equipment which would continue to leverage their core business/technologies, if and when it is economically required. Was this shared insight or a clever bluff?

Bar Cohen term

As a point of clarification, Dr. Avi Bar Cohens term of President of the IEEE Electronics Packaging Soc. (EPS) will begin Jan 2018.

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 338 Bar Cohen to Take Over IEEE EPS (CPMT); Ho and Tu Win IEEE Packaging Field Award

By Dr. Phil Garrou, Contributing Editor

As we noted in IFTLE 336, the IEEE packaging society, which has been known as IEEE Components, Packaging and Manufacturing Technology society since 1993 is about to be renamed the IEEE Electronics Packaging Society (EPS).

Bar-Cohen takes over IEEE CPMT

At the Board of Governors meeting just held in conjunction with the 2017 ECTC conference, Avram Bar Cohen was elected as the first President of the newly named society.

Bar CohenDr. Bar-Cohen is currently a Principal Engineering Fellow at Raytheon Corporation – Space and Airborne Systems. Bar-Cohen recently completed six years as a Program Manager in the Microsystem Technology Office at the US Defense Advanced Projects Agency (DARPA). Before that he held several University positions including Chair of Mechanical Engineering at the University of Maryland and Director of the University of Minnesota Center for the Development of Technological Leadership.

He is an internationally recognized leader in thermal science and technology. His current efforts focus on embedded cooling, including on-chip thermoelectric and two-phase microchannel coolers for high heat flux electronic components, thermal control of directed energy systems, and studies of wireless power beaming.

Bar Cohen is a Fellow of IEEE, and is a past Editor-in-Chief of the CPMT Transactions (1995-2005). In 2014 he was honored by the IEEE with the prestigious CPMT Field Award and had earlier been recognized with the CPMT Society’s Outstanding Sustained Technical Contributions Award (2002), the ITHERM Achievement Award (1998) and the THERMI Award (1997and ASME’s Heat Transfer Memorial Award (1999), Edwin F. Church Medal (1994), and Worcester Reed Warner Medal (1990).

Ho and Tu win IEEE Electronic Packaging Field Award

The IEEE CPMT field award was established in 2002 and is presented yearly for “…meritorious contributions to the advancement of all aspects of device and system packaging including microelectronics, optioelectronics, Rf/wireless and MEMS. This is the highest level packaging award in all of IEEE. To view a complete list of past recipients see

This year Paul Ho, Director of the Interconenct and Packaging Laboratory of the University of Texas and King-Ning Tu professor at National Chio Tung Univ of Taiwan have received this award for “contributions to the materials science of packaging and its impact on reliability, specifically in the science of electromigration” . The patented innovations of Ho and Tun, while at IBM earlier in their careers, overcame the roadblocks caused by electromigration that limited high performance chip reliability. Addressing Al and Cu wire connections and solder bumps their work provided the foundation to understand the science of observed failure mechanisms and guided high volume chip designs and manufacturing processes. They also addressed reliability issues of low-k dielectrics and tin whiskers.

Ho (center) and Tu (right) receive field award from current IEEE CPMT President Jean Trewhella

Ho (center) and Tu (right) receive field award from current IEEE CPMT President Jean Trewhella

For all the latest in advanced packaging, stay linked to IFTLE…


IFTLE 337 Will Samsung displace Intel in 2017?; Foundry Samsung – A reality; I-Cube

By Dr. Phil Garrou, Contributing Editor

Samsung will soon displace Intel

IC insights has announced that if memory market prices continue to hold through 2Q17 Samsung could displace Intel, which has held the #1 semiconductor sales ranking since 1993.

“Using the mid range sales guidance set by Intel for 2Q17, and a modest, yet typical, 2Q sales increase of 7.5% for Samsung, the South Korean supplier would unseat Intel as the world’s leading semiconductor supplier in 2Q17 (see below). [link]

IC insights 1

As we have discussed in IFTLE 332 “Wither Goest the Toshiba NAND Business…” Toshiba is in the process of selling off their memory business to raise cash. At that point all 6 of the 1993 top 10 semiconductor suppliers from Japan will be out of the top 10.

IC insights 2

Samsung Foundry Separates

Late last fall reports from Korea indicated that Samsung would likely spin off a foundry business unit. [link]. “Samsung Electronics’ System LSI business division is largely divided into four segments; system on chip (SoC) team which develops mobile APs, LSI development team which designs display driver chips and camera sensors, foundry business team and support team. According to many officials in the industry, Samsung Electronics is now considering forming the fabless division by uniting the SoC and LSI development teams and separating from the foundry business.”

IFTLE has commented many times over the past 5 years that if Samsung ever focused on a foundry business they would immediately become the #2 foundry supplier and could soon compete with TSMC for the number one spot.

On May 12th Samsung finally announced it will spin off its foundry operation from the System LSI division to create an independent business unit [link]

If Samsung really wants to run this is a seperate entity and compete head on with TSMC, IFTLE recommends they take their packaging capabilities withthem to the foundry because that’s the only way to compete with CoWoS and InFO etc.

Samsung 14nm Network Processor uses 2.5D “I-Cube”

Samsung reported that they have taped out their 14nm Network Processor close collaboration with eSilicon and Rambus [link]. This is based on Samsung’s 14LPP (Low-Power Plus) 3D FinFET process eSilicon’s ASIC and 2.5D design capability and IP solutions, and Rambus’ 28G SerDes solution.

Samsung announced that they will “…keep developing (our) network foundry solution to be a ….total network solution provider aligned with (our) process roadmap from 14nm to 10nm to 7nm.”

On the packaging front, they report that they have named their newly developed full 2.5D turnkey solution, which connects a logic chip and HBM2 memory on an interposer, as I-CubeTM (Interposer-Cube) solution. This 14LPP network process chip is the first product that Samsung applied I-CubeTM solution together with Samsung’s HBM2 memory. The I-CubeTM solution will be essential to network applications for high-speed signaling, and it is expected to be adopted into other applications such as computing, server and AI in the near future.

e-Silicon aded “Our HBM Gen2 PHY, custom flip-chip package design and custom memory designs also helped to optimize the power, performance and area for the project.”

HBM2 Interposer with Silicon or Laminate?

At the Hot Chips conference late last summer Samsung in a proposal for low-cost HBM, Samsung outlined plans to lower the complexity and thus cost of HBM technology.

The savings will come from solutions to the listed challenges.

– fewer TSV will make the stacks easier to manufacture and interconnect

– removing the buffer die will make the stack simpler, but the buffer die customization was one of the original tenants for the memory stacking concept so this is confusing.

– moving from a silicon to a laminate interposer on first glance should reduce costs, and the rest of the industry has certainly listed this as an option, but it is still unclear the impact this will have on performance.

Samsung 1


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Dr. Phil Garrou gives his insight into leading edge developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more.

This week, I’d like to give you the IFTLE historical perspective on the two major name changes of our key International Microelecronic Packaging & Interconnect Societies. One occurred 20 years ago and one that is occurring as we speak.

So as Paul Harvey would say …here is the rest of the story …

Paul Harvey “The Rest of the Story” was a radio program that originated during the WW2 and later as a radio series on the ABC radio networks . The Rest of the Story consisted of stories of little-known or forgotten facts on a variety of subjects. The broadcasts always ended with Paul Harvey saying  “….and now you know the rest of the story.”

ISHM becomes IMAPS

The International Society for Hybrid Microelectronics (ISHM) was conceived in 1967 with a focus on thick film hybrid circuit technology, as he name clearly indicates. You see, in 1967 the microelectronics industry was in its infancy, there were no ICs, there was no consumer microelectronics industry unless you’re talking about the early radio and telephone industries which were built around the vacuum tubes (the first calculators didn’t hit the consumer market till the early 1970s if I’m remembering correctly). As IBM began to develop “computers” the circuits were manufactured using thick film hybrid technology. The System 360 (1964-1971) used ferrite core memories with small ceramic hybrid circuits providing the core drive and sense functions. [for a great perspective of this technology as it stood in 1972 read “Thick Film Hybrid Microcircuit Technology” by JV Biggers, Penn State, ISBN 0-89874-455-5 ]


These hybrid circuits used metal conductor and ceramic insulator pastes and screen printing technology to build up circuit patterns.

As time passed silicon IC’s went mainstream, as did printed wiring boards, DIP plastic packages and wirebonding (1970s). Looking at the ISHM Anaheim proceedings in 1985 (my first ISHM meeting) the bulk of the program was still focused on thick film technology and applications.

IFTLE concludes that the turning point for ISHM was 1992 and the inception of the Int. Conference on Multi Chip Modules which was held, over the next decade, every spring in Denver CO. MCMS were THE advanced packaging technology of the 1990s.  In 1992 it was unclear what technologies would be used for MCM manufacturing since there were ceramic, silicon and laminate options available. ISHM and IEPS (the International Electronic Packaging Society) got together to sponsor this major international meeting. (As an aside, IEEE CPMT was invited but chose to have their own MCM conference which in hindsight was a mistake because their more academic focused IEEE meeting crashed and burned after two years). The Denver MCM conference became a huge international success with a large exhibition and several thousand global attendees each year. If you were a player in advanced packaging you were at the Denver MCM conference. What became very clear to everyone, who wasn’t already convinced, was that new packaging technologies were taking over and the field was no longer being driven by ceramic / hybrid thick film technology.

If we look at the IMAPS leadership structure in the 1990s, Harry Charles (Johns Hopkins Applied Physics Labs) was President in 1994 followed by George Harman (NIST) in 1995, Rao Tummala (IBM, GaTech) in 1996, Jim Drehle (HP) in 1997 and myself (Dow Chemical) in 1998 . This string of Presidents had a shared vision for ISHM to be a broad multidisciplinary packaging society. Not to eliminate hybrid thick film technology, but rather to be inclusive of whatever new packaging technologies that came along.  The inside joke between Tummala, who’s degree was in ceramics and who made his name at IBM developing ceramic technology for IBM super computers and myself at the time was “remember the graduate”. This referred to the Dustin Hoffman movie “The Graduate” (1967) wherein advice was given to newly graduated Hoffman about where to focus his career “Ben I want to say just one word to you….just one word…plastics!”) .

So…when IEPS approached ISHM with a proposed merger in 1996 this group clearly saw an opportunity to have the new name reflect what we wanted ISHM to become. The new acronym of IMAPS (International Microelectronics and Packaging Society, was chosen over the strong objections of some long time ISHM members and corporate sponsors who were still focused on thick film technology, but in the end the advanced packaging theme prevailed.

To IFTLE the inclusion of “and” in the name never made sense, but there was concern about being called IMPS (An imp is a mythological being similar to a fairy or goblin, frequently described in folklore and superstition).



In 1978 IEEE formed the “Components, Hybrids, and Manufacturing Technology Society” (CHMT).” As you can tell from the society name, hybrids were still a driving technology in the late 1970s.

Under the guidance of Presidents Ron Gedney (IBM, 1993) , CP Wong (AT&T Princeton, 1994) and Dennis Olsen (Motorola, 1995) the Society changed its name to “Components, Packaging, and Manufacturing Technology Society” in 1994 replacing the specific “hybrids” with the more generic “packaging”.

In 2015, after leadership meetings to discuss where packaging is going and whether IEEE CPMT was structured to take advantage of any changes, President Jie Xue (Cisco) commissioned a study group of myself, Rolf Aschenbrenner (Fraunhoffer IZM) and Subu Iyer (IBM now UCLA) to examine CPMT branding and come back with any recommended changes.

Discussions with general membership revealed that while the ECTC conference name was well known, few outside the inner circle understood what CPMT stood for let alone that it was the IEEE society that actually owned ECTC.

In 2016 the committee came back to the Board of Governors with the following observations

  • Our society is highly multidisciplinary
  • Any new name should be inclusive not exclusive
  • A new society name should NOT focus on trendy buzz words of the day like nano, 3D, IoT (like hybrids was years ago) but rather fundamental basic descriptions that do not change over the decades

A motion was made to change the Society name to the simple and clear “IEEE Electronics Packaging Society” or  IEEE EPS .

The board passed this motion and following Society bylaws the general membership was informed and asked for their opinion. There were 10 objections to the proposed change from the 2400 members.  Hopefully, when full approval is received by the IEEE Technical Activities Board and the IEEE Board of Directors, in the June 2017 timeframe, we will become the

IEEE Electronics Packaging Society (EPS)

Your 2016 IEEE CPMT International BOG (board of governors) is shown below with Jean Trewhella (GlobalFoundries) serving as President .  For those who do not follow society leadership goings-on, your board member representatives are voted on for 3 year terms by the membership in either the Americas, Europe or Asian areas. Members vote only for the representatives for their area. The number of representatives for an area is determined by the number of members in that area.

2016 CPMT board

So, now you know the rest of the story………………

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IFTLE 335 Catching Up on China and the Wait for the New Industry Driver

By Dr. Phil Garrou, Contributing Editor

Catching up on some recent stories of great importance to our electronics industry… and thus packaging. 

SMIC urges Taiwan chipmakers to partner with China-based peers

IFTLE readers are well aware that China is in a “no holds barred” battle to become a major player on the IC fab scene. [See for example IFTLE 316 “YMTC and China’s desire for 3D NAND production”; IFTLE 296 “…China the wild card…”]

Digitimes, quoting Tzu-Yin Chiu, CEO of SMIC, now reports that SMIC is urging Tiwanese chip makers and the Taiwan government to collaborate with mainland China electronics peers. [link]

Chiu indicated that “The IC industries in China and Taiwan could team up as a powerful IC industry supply chain globally”, adding that the Taiwan government should enable China based enterprises to cooperate with their Taiwanese peers.” Taiwan IC fabs including TSMC, UMC and Powerchip have indeed taken China government support to set up production on the mainland.

Chiu also disclosed that SMIC has been developing 14nm FinFET chips and will be starting R&D on 7nm s technology in late 2017.

US Dept. of Commerce – “China Poses Threat to US Dominance in Semiconductor Industry”

In a related story, South China Morning Post is reporting that US Commerce Secretary Wilbur Ross sees the US semiconductor industry as still dominant globally but said he is worried that it will be threatened by China’s planned investment binge to build up its own chip making industry. [link]

Ross said that the Commerce Department is considering a national security review of semiconductors because of their defense implications in military hardware and their general proliferation in devices throughout the economy. Ross reportedly called China’s plans for massive state-directed investments in semiconductor manufacturing capacity under its “Made in China 2025” program, which aims to replace mostly imported semiconductors with domestic products, “scary”.

Commerce Department trade data shows that the “Semiconductors and related device manufacturing” category showed a trade deficit of $2.4B in 2016, with exports of $34.1B and imports of $45.6B which includes non-semiconductor devices such as solar cells and LEDs.

Waiting for the New Driver…Impatiently

Bloomberg is reporting Qualcomm Inc. and MediaTek are both showing slowing sales and declining margins as shown below [link].

bloomberg 1

They point out that this is due to a maturing of the mobile phone industry segment and look to “IoT and automotive” to save things, but are impatient for this new drivers arrival “the IoT should be the next big thing for chipmakers. The problem is that this era has yet to fully arrive, leaving them supplying a smartphone market that’s peaked

For a read on Yole”s take on potential IoT applications before Rozalia Beica”s departure, see IFTLE 227 “Yole’s Beica examines Internet of Things …”

IFTLE is a believer in the general concept of IoT, i.e. Rf transfer of data from inanimate objects, but as we have mentioned before we do not see this as a general boon to advanced packaging since such applications will require the absolute lowest priced packaging solutions, not typical of advanced packaging.

IFTLE considers automotive similarly. Certainly there is no question that there will be more and more electronics built into automobiles, but, based on my career at a major chemical company which had other divisions supplying plastics to the automotive industry, I can tell you that supplying the automotive industry is the antithesis of a high margin business for suppliers. Typically automotive business is used to fill he plant (in the industry this is called loading the plant) which in turn generates lower cost per unit volume which can be used to meet the lowball pricing required to get the automotive business while also increasing margins in other applications using the same materials but accepting a higher profit margin for the supplier.

If anyone out there thinks electronics is a tough industry to play in, try automotive!

Hope to see you all in a few weeks at the ECTC in Orlando.


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