Author Archives: sdavis

IFTLE 301 Are Silicon Circuit Boards in our Future?

By Dr. Phil Garrou, Contributing Editor

In IFTLE 300, we commented that the imminent end to scaling will force changes in how we approach the development of new integrated circuits and systems.

IyerSubramanian Iyer, ex IBM fellow, retired from IBM when the chip business was sold off to Global Foundries. He is now the Distinguished Chancellor’s Professor in the EE Dept. at UCLA and Director of the Center of Heterogeneous Integration and Performance Scaling (or CHIPS for short). The CHIPS mission is to interpret and implement Moore’s Law to include all aspects of heterogeneous systems and develop architectures, methodologies, designs, components, materials and manufacturable integration schemes that will shrink system footprint and improve power and performance. Let’s look at his concept of for where the industry should be going.

In the July 2016 issue of IEEE Trans on CPMT, Iyer put pen to paper ( or should we say “fingers to keyboard”) and has laid out the master plan for CHIPS in his article “Heterogeneous Integration for Performance and Scaling.”

Iyer contends that Moore’s law has so far relied on the aggressive scaling of CMOS silicon features. This in turn resulted in a dynamic system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. While scaling on chip has increased >1000X, the integration of multiple dies on packages and boards has scaled by a factor of 3 – 5X. The current slowing of semiconductor scaling [discussed in IFTLE 300] will bring a focus on heterogeneous integration and system-level scaling. This transformation is already under way with 3-D stacking of dies and will evolve to make heterogeneous integration the backbone of sustaining Moore’s law in the years ahead.

While the SoC approach has moved us forwards, a single chip does not make a system. In order to build a system, multiple chips such as processors, memory chips, field programmable gate arrays (FPGAs), transceivers, power regulators, and so on need to be interconnected. Traditionally, this has been done using a printed circuit board (PCB).

Chips are typically packaged before being mounted on the board. While it is true that the package connects the chip to the rest of the system, it does so very inefficiently. For instance, contacted gate pitches in the 14-nm node are about 40 nm, through the hierarchical wiring system, we increase that pitch up step-by-step until, at the upper most wiring level, it is a few micrometers. The C4 bumps then increase this pitch to about 150 μm. The BGA connections to the board take this further to 400 – 600 μm. In essence, to connect two chips the interconnections of chip 1 must fan out to a PCB board pitch and then fan back in to chip 2 pitch , thus causing the inefficiency . Silicon has scaled by over a factor of 1000 in the last 50 years, while packages and boards have scaled by at most a factor of 5.

Iyer contends that with increasing demands on the BW between the chips and the inability to increase the number of physical connections between the chips, serial links need to operate individually at higher and higher data rates. These higher rates mean higher frequency signals carried by the traces on the board and significantly larger noise levels and cross talk between adjacent channels. Consequences of this include:

1) The power to transmit higher frequency signals through SerDes goes up exponentially with data rate.

2) The SerDes circuits themselves become more complex to design and take up more area. modern SoCs may sometime devote almost 25% of their area to SerDes, and in some cases, an even greater fraction of chip power is allocated to SerDes function.

Approaches to System Scaling and Heterogeneous Integration

Iyer proposes Eliminating the Package and directly bonding multiple bare dies to an interconnect fabric (IF) made of silicon. He notes that the first steps in this direction have been silicon interposers but argues that this is not the ultimate solution since an interposer adds cost and complexity by adding an extra level to the overall package. What Iyer is proposing is “to go a step further and transform the interposer into the board”.

He proposes replacing the current epoxy glass PWB board with silicon. This silicon board would be a wafer on which have been processed several levels of fine pitch wiring with the top-most wiring level matching the top chip wire levels with landing pads of similar dimensions that can connect to other die that have been attached with precision alignment (0.5-μm overlay). He calls this wafer the silicon interconnect fabric (Si-IF). Electrical connections between the rigid flat die and the Si-IF will be made by thermal compression bonding. While technology at this fine scale is not available today, Iyer believes it possible in the near future. He believes that two features of this approach make it feasible:

1) the use of small die (a few millimeters on a side)

2) the fact that both the die and IF are made of relatively thick silicon, are flat and have matched CTEs.

Iyer contends that computing is evolving to a more heterogeneous architecture with a combination of special purpose processors, accelerators, and FPGAs which make this Si-IF integration scheme very attractive, since one can synthesize such systems from a variety of off-the-shelf components. In the case of mobile systems and the so-called IoT, heterogeneity is the key requirement. One can integrate analog components, sensors, MEMS, batteries, supercapacitors, and so on as needed. Overall, they expect that this approach will allow significant reduction in overall board footprint.

Iyer has listed the following requirements for such technology to come to pass.

1) Integrated Design System: Today, chips, packages, and boards are all designed separately and almost independently. This will need to become a lot more integrated. In addition, while, today, we do electrical, thermal, and mechanical design more or less independently, these three views of the system will also have been integrated.

Such a system will require significantly more understanding of the interactions between these 3 views and the development of a significantly more sophisticated set of tools.

2) New Design for Test and Repair Methodologies: As rework is no longer an option, and die-level testing will be limited in scope, the component chips will have to test themselves to a large extent. While technologies to do this exist, they will need to be adapted to bare die.

3) Interface Standardization: Our approach allows us to have a large number of inter die connections and this allows us to parallelize the connections and have simpler interfaces. However, this approach needs to be adopted universally. We believe that the standardization of slower and easier to build parallel interfaces is more easily achieved than serial interfaces.

4) Power Delivery and Thermal Management: In the case of high-end systems, one would need to deliver ∼1 kW of power at different voltages. This will require integrated power management techniques, and the use of features, such as Hi-Q inductors, buck convertors, and power switches, than can either be components attached to the IF or integrated into the Si-IF. Removing the generated heat is another challenge. One mitigating factor in the use of the Si-IF is that the silicon itself is a good thermal conductor and can be an integral part of the heat-sinking solution. The die themselves may have integrated heat sinks made, for example, with silicon fluidic channels or micro machined fins.

5) Structural Properties of Silicon: While the ability to process silicon as an IF is second to none, care must be exercised in wafer handling. Fortunately, silicon-processing equipment has evolved to accommodate this

6) Cost: It has been argued that silicon is expensive and organic materials would be more cost effective. If we need fine pitch interconnects, then in practice, material cost will be about 10% of the finished product cost. Processing the fine pitch interconnects dominates the cost. In fact, it will be very expensive to fabricate fine pitch (sub-10-μm pitch) interconnects on organic

substrates; while fully depreciated silicon fabs can do this easily and more cost effectively on silicon. There are additional benefits of silicon, such as integrated passives and active IFs. The silicon solar cell substrate suppliers have developed the so-called metallurgical grade Si that is cost competitive.

While the challenges are enormous, so too are the payoffs. When compared with the challenges and costs of continuing to shrink minimum features on a die, he believes “… the value proposition of what we have proposed here is solid”.


For all the latest in Advanced IC Packaging, stay linked to IFTLE…

IFTLE 300: ITRS 2.0 – It’s the End of the World As We Know It

By Dr. Phil Garrou, Contributing Editor

The 2015 ITRS Roadmap

The 2015 International Technology Roadmap, was released earlier this summer by the SIA (Semiconductor Industry Association). It can be accessed here [link].

If there were any practitioners left who were still denying that scaling has come to an end, this report drove a stake into their heart. No longer snickering at the “conspiracy theory”, all major organizations have now accepted the reality of a future without scaling. Even Popular Mechanics is reporting this as a major event [link].

Christopher Lee

As REM would say :

“It’s the end of the world as we know it
It’s the end of the world as we know it
It’s the end of the world as we know it, and I feel fine”

Some will still argue that the discussion has been about Moore’s Law, not scaling. They will argue that Moore’s law simply predicts a doubling of transistor density within a given integrated circuit, not the size or performance of those transistors. To me this is just semantics. First of all More’s Law is not a Law. It is an observation. Secondly, we all know that Moore’s Law and scaling, to most in our industry had become synonymous over the years.

In the recent IEEE Spectrum article “Transistors Will Stop Shrinking in 2021, Moore’s Law Roadmap Predicts” the authors note “After 2021, the report forecasts, it will no longer be economically desirable for companies to continue to shrink the dimensions of transistors in microprocessors. Instead, chip manufacturers will turn to other means of boosting density, namely turning the transistor from a horizontal to a vertical geometry and building multiple layers of circuitry, one on top of another.” [link]

In fact the ITRS changed its predictions from their 2014 report, when they said that miniaturization would continue until at least 2028. The following figure (from the IEEE Spectrum article) very clearly points out the new ITRS conclusion.

end to scaling

This will be the last ITRS roadmap put together by the Semiconductor Industry Association, which ends a 20+ year effort that began in the US and expanded to include the rest of the world. Citing “waning industry participation” which was to be expected as one after another major players stopped building fabs for the latest nodes. The technical difficulty and costs associated with leading edge fabs has resulted in significant consolidation as all readers of IFTLE are well aware. Today, there are basically just four major players left: Intel, TSMC, Samsung, and GlobalFoundries.

To some the shocker was probably IBM getting out of semi production. Back in 2009 I gave a presentation to a group of Govt officials who told me not to worry about on shore procurement because “IBM will always be around.” My response was “No, that’s incorrect; they will be out of the IC business soon because a $1B chip fab business cannot support building $5B factories.” They laughed it off and ignored the comment. I’m sure they are not laughing now!

Paolo Gargini, chair of the ITRS, astutely commented that chip buyers and designers—companies such as Apple, Google, and Qualcomm—are the ones now dictating the requirements for future chip generations, not the IDM’s that we all grew up with.

IFTLE readers know that this issue has been out there for quite awhile now, for instance at the 2015 IEEE ISSCC (International Solid-State Circuits Conference) Intel detailed results for its future 10nm manufacturing process. They stated that “10nm looks like the end of silicon scaling, to achieve 7nm, a III/V material will be required.”

Intel 1

So, where does this leave us?

The ITRS report predicts the industry will move away from FinFET ~ 2019, towards “gate-all-around transistor” technology. A few years later, transistors will use nanowires and become vertical devices. By 2024 they predict we will be facing a thermal limit which will usher in microfluidic channels to increase the effective surface area for heat transfer.

Is this all come to pass? As Yogi Berra used to say “The hardest things to predict are those that have not happened yet.”

It is clear that solutions being predicted by the ITRS front end experts are certainly front end solutions. As a reader of IFTLE you know that I have been predicting a period of increased focus in packaging. The heretofore front end equipment companies and IC fabs like TSMC, UMC and Global have certainly bought into this theory as 2.5D, 3D, fan in and fan out have become their new buzz words.

So this explains why the REM song fits how I feel now. It may be the end of the world as we have known it…but I feel fine because packaging is now, assuming it’s new position on the forefront or microelectronics. Now that manpower and emphasis have shifted to packaging solutions to customize products, I think we have only seen the tip of the iceberg in terms of technological innovation.

This is IFTLE 300, which means I have been sharing information and thoughts with you for 6 years. Thank you all for your continuing support of this blog.

Now, taking this opportunity to update a few things:

1) Lester the Lightbulb

For those long time readers of IFTLE still interested in my Lester the lightbulb “non scientific” lifetime testing [link] here is where we stand, exactly 5 years (Aug 2011) into our test.

Our LED bulb is still burning, but so is our 25 cent “Lester the lightbulb” incandescent bulb. Yes that is correct, the incandescent is still functioning after 5 years with approx. the same burn time and on/off cycling in the same area of the house. The big looser in all this is the compact florescent (CFL) which has burned out 3 times, that’s right this mercury containing technology (how can anyone call this green ?) is now on bulb #4. A pic of the bulb #3 burnout is shown below. It gave off a puff of white smoke that probably shortened my life due to mercury vapor inhalation. Lucky it didn’t start a fire.


2) Hannah and Maddie

Early on I told you that you would have to put up with pics of my granddaughters every “now and then” because “that’s what grandparents do.” It is now “now and then” once again.



3) The IFTLE Tag Line

Since its inception “Insights from the leading Edge” has intentionally put a lot of emphasis on 2.5 / 3D. It has been obvious that if this technology were to take root, it would be a paradigm shift in how we do packaging. IFTLE felt the community needed constant updates on were things stood. More than a decade has now gone by since the first articles appeared proposing we mainstream 3DIC with TSV. The first real products have now appeared in FPGAs, CMOS image sensors and stacked memory. It has clearly become one of the arrows in the packaging quiver. Will prices come down and its applications proliferate? Only time will tell.

Starting with IFTLE 301, my tag line will simply become “For all the latest in advanced IC packaging, stay linked to IFTLE.” IFTLE will certainly still cover advances in 2.5 / 3D although not with the special emphasis placed on these topics in the past.

How everyone has enjoyed their summer, I need to go off now and decide on content for IFTLE 301.

..…….It’s the end of the world as we know it, but I feel fine!…………….

IFTLE 299 Siliconware’s Ma Discusses Die Stacking Options for 2.5D

By Dr. Phil Garrou, Contributing Editor

Continuing our look at IEEE ECTC 2016:

Siliconware – Die Stacking and Integration Options with TSV Based Si Interposers

At the recent IEEE ECTC Conference in Las Vegas, Mike Ma of Siliconware compared various die stacking and integration options with TSV Si interposers. From his perspective there are four main stacking platforms for 2.5D IC in advanced packaging. They are shown in the figures below.

In the first method known as Chip on Chip (CoC) on substrate the silicon interposer is fully processed and then multiple active chips are stacked on the silicon interposer, followed by assembly of chip module on the substrate.

The interposer is diced and attached to a silicon carrier which is coated with temporary adhesive film. The carrier provides handling and warpage control capability, i.e. the silicon interposer warpage can reportedly be controlled to within 10um during high reflow peak temperature. After that, the top die can be sequentially attached onto interposer with flux and joined together via mass reflow then followed by an underfilling process. Then the silicon carrier is de-bonded and the individual chip module attached onto blue tape film frame and ready for substrate assembly just as usual traditional FCBGA process.

In the second method known as Chip on Substrate (CoS), the silicon interposer is fully processed with TSV, metal layers, u-bumps, Backside Via Reveal (BVR) and C4 bumps. The processed silicon interposer is then assembled on the substrate followed by assembly of the multiple active chips onto the interposer.

In CoS, the interposer, ( ~ 100um thick) is die bonded to an organic substrate followed by assembly of top multiple active chips. If the substrate warpage is opposite the interposer (interposer warped up and substrate warped down is usual) , there are risks of electrically open or short failures happened after die bonding process because C4 bump height can’t overcome the gap change between TSI and substrate during the die bonding thermal excursion. Thermal compression bonding (TCB) is used to keep a stable gap between the interposer and the substrate during the die bonding process. In addition, Non-Conductive Paste (NCP) or Anisotropic Conductive Paste (ACP) are used.

SPIL 3 CoC vs CoS

Chip on Wafer before TSI backside process (CoW_first) involves attaching the top active chips on front side micro-pads of silicon interposer before the silicon interposer backside bumping process.

After micro bump bonding, underfilling and molding the wafers are ground down to expose the chip tops. The wafers are then flipped and temporarily bonded to a support wafer, the interposer vias exposed and bumped. The modules are then de-bonded from the carrier to a tape ring. Finally, the modules are FC BGA assembled on the organic BGA substrates

In the Chip on Wafer after TSI backside process (CoW last) single or multiple top dies are attached to the interposer wafer after the interposer has been fully processed including front side u-bumps process, backside via revealing process, backside re-distribution layer and final C4 or Cu pillar bumping process.

After interposer is prepared to receive chips to top surface, it is flipped and supported on a carrier for backside reveal, RDL and bumping. It is then flipped onto a second carrier and he chips mounted, underfilled and molded as before.

SPIL 3 CoW first vs last-2

Comparing to the CoW first process with TSV, die bonding assembly portions are the same, but there are differences in the interposer fabrication. Instead of completing micro-bumps process first, RDL and PSV are implemented first and followed by UBM process. Since TSV-less platform has no interposer in its final form, the carrier can be either glass or silicon. After the carrier bonding process, instead of the usual backside reveal process, the TSV-less interposer will be partially removed by mechanical grinding followed by wet etching to completely remove silicon portion and stop on the remaining passivation layers. The passivation layer is then patterned to expose contact areas for further C4 bumps. Further assembly including the chip module on substrate processes are the same as described for CoW first.

Ma compared the chip stacking options in the chart below.

SPIL 3 Comparison of chip stack options

Editorial correction: In IFTLE 298 IFTLE inadvertently assigned credit for the “20um Pitch Thermo Compression Copper Pillar Bonding” work to IMEC instead of rightful authors at IME. This should have been corrected by now, but we did want to offer our apologies for this error.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 298 IME 20um Pitch Thermo Compression Copper Pillar Bonding

By Dr. Phil Garrou, Contributing Editor

Continuing our look at IEEE ECTC 2016:

IME – Thermo Compression Bonding of 20µ Pitch Copper Pillar Bump for 3DIC Stacking

Throughput is limiting the adoption of 3D IC stacking processes although 3D IC has many advantages in shorter communication lines, lower electrical parasitic and lower package footprint. Thermal compression bonding (TCB) of a chip stack done one by one, it takes long cycle time to complete a 300mm wafer. Typical TCB bonding with bump pitch of 50-100μm takes 14-16 sec per chip and more than 22 hours for a 300mm wafer with 1440 dies x 4 layer stacking. A significant improvement on the throughput is needed for high volume manufacturing.

IME has developed a 20μm pitch micro-bump array assembly process with throughput of 1200 UPH (or 3 sec/chip) and bonding accuracy <2um by using two-step C2W bonding. The C2W is carried out in two steps where in the first step chips are temporary tacked on the wafer with planarized wafer level underfill, and in the second step, fully populated tacked chips on wafer are permanently bonded by using pressurized gas in a gang bond process. The gang bonder maintains chuck at constant bonding temperature. This two-step C2W process provides a new approach to solve the major concerns of the two step C2W bonding: (1) chips shifting during gang bonding, (2) pillar height variation causes gang bonding force non-uniform distribution among chips and (3) fine pitch (<30μm) solder bridging causing electrically short.

A traditional gang bonder uses metal piston press on the top wafer but sine copper pillar bump heights are not uniform enough, a soft material layer is added on top of the chips to absorb chip height variations as shown below.


But the soft layer material and Si wafer have different CTEs, thus expanding differently during thermal processing . This non-uniform expansion causes horizontal force on chips resulting in chip misalignment. To overcome the chip shifting issue, a gas pressure bonder is used for gang bonding as shown below.


This solves the pillar height variations without chip shifting.

IBM Zurich – All Copper Interconnect from Nanoparticle Sintering

IBM Zurich continued their reporting on the use of copper nano particles (nps) to form all-Cu flip chip interconnects based on pressureless low temperature sintering (~ 200 C).

It is generally agreed that an increase in current density is required to support the reduction in transistor size and supply voltage as well as 3D integration of integrated circuits. However, the current capacity in solder-based interconnects is limited due to electromigration. It is generally accepted that all-Cu interconnects should result in electrical interconnects with a higher current capacity.

Fully Cu interconnects can be formed by thermocompression bonding (TCB) of two flat Cu surfaces at high temperatures (350 C) and pressures. It is also known that the use of nanoparticles (nPs) at the bonding interface reduces the required temperature and pressure needed to form an interconnect, while also allowing for less stringent requirements for surface roughness.

In the IBM process, a Cu paste is applied between Cu pillars and Cu pads in a standard flip chip bonder. The assembly is performed at room temperature with a controlled low force. The interconnects are subsequently formed by sintering the Cu nPs in the paste at 200 °C in a batch oven under a reducing formic acid atmosphere.


Process sequence to form all-Cu interconnects: a) a Cu paste film is applied onto a carrier; b) the pillar chip is dipped into the Cu paste firm; c) Cu paste is transfered to the tip of every Cu pillar; d) the Cu pillar chip is placed onto the substrate and is sintered in a batch reflow oven at 200 °C in formic acid activated nitrogen

However, large differences in electrical and mechanical properties of the tested sintered Cu foils compared to bulk Cu results as shown below. It is believed this is due to the porosity present in these nano copper interconnects. The shear strength of the nano copper interconnects was also significantly lower than standard Sn/Ag non lead joints [ 19 =/-5 MPa vs 65-75 +/- 10 MPa]


Attempts to use a bi modal distribution of nano and micro copper particles did not materially affect these results.

SK Hynix – Characterization of Stacked Memory

The use of tremendous number of through TSVs and micro-bumps in a stacked package is a major worry to its manufacturers and users. DRAM chips with TSVs are thin and its micro-bump interconnection can be affected by the process conditions and materials selection. Copper, widely used for via filling, may bring about interconnect failures by Cu pop-up due to higher CTE than Si and transistor failures by its contamination into silicon lattices. Micro-bump joints are also of interest in terms of reliability. Thermal-compression bonding (TCB) is a common way to stack up multiple chips with TSVs and micro-bumps but insufficient bonding time can lead abnormal bump joints and various failure modes such as non-wet, brittle intermetallic compound (IMC) formation, bump cracking, head-in-pillar (HiP) joints etc.

Thermal characterization is also important in TSV stacked chip packages. High performance devices such as HBM packages need to be thermally evaluated. Any polymer layers between stacked chips may impede thermal flow and thus raise the junction temperature of each slice.

Fault isolation techniques are required to identify and correct any failure modes present. Options are compared in the table below.

Hynix 1

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…


IFTLE 297 TSMC Describes UBM Free Fan-In WLCSP

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2016 ECTC Conference:


TSMC discussed their UFI (UBM-Free Integration) Fan-In WLCSP technology which they claim enables large die fine pitch packages.

Development of low-cost WLCSP for large die with high I/O count is desired for broadening its applications. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5×5 mm2 with ball pitch smaller than 350 um.

TSMC has discovered that by controlling the maximum strain location and optimizing materials, chip warpage and the stress between Si and the PCB can be reduced which improves both component and board-level reliabilities of WLCSP packages. Packages as large as 10.3×10.3 mm2 with both 400 and 350 um ball pitches have been developed.

UBM is used as an interfacial layer between the metal pad of the integrated circuit and the solder ball. The formation of UBM/solder intermetallic compounds (IMC) limits the board level reliability of the package due to the poor mechanical robustness of IMCs. When the die size is increased, stress increases which promotes cracking at the UBM/solder ball interface.

TSMC claims their UFI WLCSP fabrication cost is lower than conventional WLCSPs due to the elimination of the UBM. Removal of the UBM also reduces the thickness of the package by 30%.

The figure below compares the structures of a standard WLCSP vs the TSMC UFI WLCSP. In the UFI WLCSP, the solder balls are directly mounted to the Cu RDL followed by the polymeric PL (protection layer which secure the balls.


Very similar removal of UBM and subsequent thickening of the copper pad has been reported before by Amkor in 2010 [link]

TSMC simulation results showed the solder joint fatigue life decreases with increasing die sizes for both UFI and the conventional WLCSP. Predicted solder ball fatigue life was found to increases with decreasing die thickness. The authors suggest that decreasing the die thickness not only reduces the thermal expansion difference between the die and the PCB, but also causes the die to bend more under thermal loading. In addition, simulation results imply that solder joint creep strain for solder mask defined (SMD) structures is 72% higher than for non solder mask defined (NSMD) structures because of its reduced flexible solder joint height and the constraint of the solder mask. Thus they concluded that it is better to use NSMD type of PCB for UFI WLCSP. The use of NSMD structures to increase reliability has been known since the work of Bell Labs Ejim [ref]

TI Ejim et. al., “Reliability performance and failure mode of high I/O thermally enhanced ball grid array packages” Electronics Manufacturing Technology Symposium, 1998, p.323 – 332.

The UFI WLCSP passes all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution, respectively. 10mm UFI WLCSP have passed component-level reliability tests suchas TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests. 

To demonstrate the possibility of higher interconnect density, they fabricated UFI- WLCSP with multiple RDL layers. The package with two RDL layers had die size of 10.3 x 10.3 mm2 and ball pitch of 350 um. The structure is shown below. Again such structures passed all component level reliability testing.


Tohoku University – Interconnect Impact on 20um thick DRAM Chips

The effect of thermo-mechanical stress originating from CuSn μ-bumps and Cu TSVs on the retention characteristics of 20- μm-thick, vertically stacked DRAM memory chips. They determine that there is 50% probability that data retention period decreases by 47% for the DRAM chip having thickness value of 20 μm as compared to the retention period of 200 μm-thick DRAM chip.

Back-end-of-line (BEOL) processes on ultra-thin dies/wafers might cause severe degradation to device performance, due to deteriorated mechanical strength and lattice defects, back-side metal contamination, thermo-mechanical stress caused by TSVs and μ-bumps, local mechanical stress

induced on active Si near m-bump region, etc. They the thermos-mechanical stress present in the DRAM dies with thickness values varying from 200 μm down to 20 μm using micro-laser Raman spectroscopic techniques.

Retention time data obtained for a 50 μm-thick DRAM die at two different positions respectively 15.5 μm and 0 μm from the KOZ of TSV. Before annealing the stacked die, we observed similar retention time values for both the macros. While after annealing at 300 °C, irrespective of position they observed reduction in DRAM retention time at the area closer to the KOZ.

Upon reducing down the DRAM chip thicknesses to 20 μm from 200 μm, the retention time is nearly halved at the cumulative probability of 50 %. After annealing at 300 C, a compressive stress value of -200 MPa caused by Cu-TSVs was found as the remnant stress at the periphery of the keep-out-zone, and faded quickly by moving away from the keep–out-zone. Retention time deterioration was found to be influenced by the thermo-mechanical stress caused by TSVs. A large amount of tensile stress was induced on the back-side of DRAM chip at right above the CuSn μ-bump region.

Tohoku 1

Brewer Science – Temporary Bonding Materials

IMEC, Brewer Science and Suss gave a presentation on the status of temporary bonding materials.

The first-generation product was WaferBOND® HT-10.10 thermoplastic bonding material. The debonding approach was based on the re-melt of the bonding material at elevated temperature and mechanical slide-off of the carrier. The technique poses some challenges including:

  • Debonding is usually performed at an elevated temperature, in the range of 200°C or higher, which prevents the integration of low-melting-point solder materials.
  • Shear force increases with the carrier slide-off speed.

The second-generation product ZoneBOND® 5150 is based on a room temperature debonding. A short chemical dissolution of the bonding material on the wafer edge is required before mechanical debonding. The thin wafer is put on dicing tape, ensuring mechanical support throughout the process. The carrier substrate is then removed mechanically in a perpendicular direction as opposed to the thermal slide debonding approach.

To further reduce the process cost, a third generation of materials, BrewerBOND® 305 , has been explored. They have eliminated the need for dual zones on the carrier substrates . Thus debonding no longer requires any chemical treatment reportedly simplifying the process and resulting in a cost reduction of 25%. A summary of the three generations of processes and key challenges can be found in the table below.

Brwer 1

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 296: The 2016 ConFab – China the “Wild Card”; HBM Close Up; Comparing High Density Packaging Technologies

By Dr. Phil Garrou, Contributing Editor

By now every web site from the MIT review to Popular Mechanics (yes, seriously) has picked up the release of the last ITRS roadmap and it’s conclusion that Moore’s Law or more precisely “scaling,” as we have known it, are a thing of the past. I will let the dust settle and dedicate IFTLE 300, my milestone, to discuss this milestone.

But for now, taking a respite from the powerful 2016 ECTC conference, let’s take a look at activities at the ConFab that occurred in June.

IC Insights –IC Industry Status

Bill McClean gave his annual look at the state of our industry. His numbers (shown below) show us coming back to pre 2015 values, although IFTLE’s gut feel is that we will be lucky to surpass 2015 numbers. I base this on the now well accepted data that shows our electronics industry has a 96% correlation factor with the overall GDP. It’s nice to have a rosy outlook, but the GDP just isn’t going anywhere lately and even 2% growth may be overly optimistic.

IC insights 1


Equally as interesting is the role of China in this economy. In past blogs I have called them the “wild card” in any economic outlooks. They are pursuing the microelectronics industry so strongly because they are currently manufacturing only 13% of the ICs they consume (2015). The Govt has poured billions into funds to try to reverse this.

McClean reports the following 3 phase strategy:

IC insights 2

We are clearly in the 3rd phase now where they are attempting to gain share in the electronics industry by mergers and acquisitions.

ic insights 3

Although attempts to buy Micron, WesternDigital/Sandisk and Fairchild have not worked out, many other mergers / acquisitions / JV’s have as shown below.

IC insights 4


TechInsights – Where the money is being made and HBM Close up

Kevin Gibb from TechInsights had an interesting point to make about where the money is being made and some great cross section photos of Hynix HBM memory stacks.

First, looking at where TSMC and UMC generate their sales, we see that TSMC is much more highly invested in the latest nodes, i.e. 28 and 20nm vs UMC. Also interesting that 180 and 130nm are generating more sales for TSMC than 90 and 60nm.

TechInsights 1


We are all aware by now of the infamous Hynix HB memory stacks which have become the mainstay of 2.5D memory products like the AMD R9 Fury. The photos below are some of the better close-up cross sections that I have seen.

TechInsights 2

The 5.5um Cu filled TSVs are on 40um pitch and show a 9um KOZ (keep out zone)


Intel – Enabling IC Scaling, Miniaturization and System Integration through Adv Packaging

Islam Salama of Intel joined the bandwagon that some of us reached years ago when it became clear that Moore’s Law WAS coming to an end. That is – future product advances / differentiation will come from advanced packaging technologies.

He offered the following slide to support his premise that packaging substrates are becoming an integral part of product performance.

Intel 1

Even more interesting was this comparison of the densities achievable with some of today’s more popular high density packaging technologies. He concludes that panel level technology and die last approaches offer a path for technology scaling and affordability.

Intel 2

For all the latest in 2.5/3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 295 Advances in FO-WLP at 2016 IEEE ECTC

By Dr. Phil Garrou, Contributing Editor

Continuing our look at IEEE ECTC 2016. Let’s examine some of the activity in the FOWLP arena.


At the recent ECTC conference, Bill Chen of ASE proposed categorization of fan out packaging.

While the initial driver for fan-out packaging like the Infineon e-WLB was to increase available IO for niche baseband applications, the main driver now is clearly to achieve multi chip packaging.



Chen now proposes we categorize FOWLP options as follows based on chips first, chips last, multichip or stacked chips (PoP):


DECA – Adaptive patterning for FO WLP

FO-WLP enables size and performance capabilities similar to Wafer-Level Chip- Scale Packaging (WLCSP), while extending the capabilities to include multi-device system-in-packages, with lower costs than 2.5D interposer technologies. But – Adopting these new technologies for single die and multi die system-in-packages requires more advanced design methodologies and tools than traditionally used in traditional WLP.

In a fan-out process the key step is the creation of a reconfigured wafer or panel. First copper studs are formed on the native device wafer over the bond-pads, and then the wafer is singulated. A pick-and-place machine then attaches the dies face-up to a carrier with a temporary adhesive. Then, the carrier and dies are over-molded, the temporary adhesive is removed, and the front of the panel is ground to reveal the copper studs. After this process, called panelization, a first via layer (VIA1), redistribution layer (RDL), second via layer (VIA2), and under-bump metallization (UBM) are formed using processes similar to WLCSP.

Two main challenges prevent widespread adoption of wafer-level fan-out technology are warpage and die shift during processing. Warpage is caused by the mis-matched CTE between mold-compound and silicon and can be addressed using structural approaches, such as the fully molded structure, or by tuning process parameters. Die-shift is the accumulation of die position error from chip-attach tolerances and movement during over-molding. Tuning process parameters such as pick-and-place force can help minimize shift, and movement due to molding is often predictable enough to compensate for during chip-attach. However, the total die shift can still range from 30 μm to 45 μm with rotation up to 0.3°on a high-throughput machine.

The die-shift problem has limited traditional FO-WLP from widespread adoption. In order to meet industry requirements, FO-WLP must be processed with high-throughput chip-attach machines, typically resulting in shift distributions that cannot be handled by traditional processes. Additionally, these processes cannot handle finer pitch connections to the die with wider shift distributions

The DECA technology derived to do this is called “Adaptive Patterning”. In this manufacturing process, an optical scanner is used to measure the true position of each die after molding, and a uniquely generated fan-out design is applied to each package. One design technique, adaptive alignment, shifts and rotates the first via and RDL layer to match the die location. Another technique, adaptive routing, utilizes a fan-out RDL design with sections removed near vias that contact the die. The final RDL connections to the die are generated by an auto-router after the true die locations are known.

In the case of adaptive patterning, the design rules specify the maximum die-shift for which the design can be adjusted. For both cases, a simple approach limits the die-shift to a range of X, Y, and θ values (e.g. −30 μm to 30 μm and -0.3°. The table below shows the magnitude of shift possible from rotation alone on several package sizes.


By adapting to die-shifts that are an order of magnitude larger than can be tolerated by traditional processes, this technology solves the last major industry challenge to adoption of fan-out packaging. The design rules for adaptive patterning are more complicated than traditional rules; however, this may be required for designs with high density interconnects and scarce routing space.

Siliconware – Fine Pitch RDL for High Density 2.5D

The original purpose of the Redistribution Layers (RDL) was to assist in the adaption of metal bumping and flip chip packaging technologies, by the addition of the metal and dielectric layers onto the wafer surface to re-route the legacy designed irregular peripheral I/O layout, into a new area array bond pads layout to facilitate a balanced metal bumps and flip chip bonding. The redistribution layer technology required polymeric thin film (e.g. BCB, Polyimide, PBO) as insulator and a semi-additive metallization scheme (often Cu pattern plating).

RDL technology, has extended its application into advanced packaging technologies, such as fan out wafer level packaging (FO WLP) and various TSV-less, substrate-less multiple chip integration, that to drive the cost effective miniaturization of system-in-package (SiP) application. The Cu RDL that in production, the line width/ spacing are 10 μm/10 μm or pitch of 20 μm .

The capability for fine pitch and multi layer RDL must be established at OSATs because the market is currently driving towards multiple chips integration and SiP applications. Furthermore, it is more difficult for the L/S < 2um due to there is no sufficient process window of lithography process.

While scaling from 10 to 3 μm poses no significant technical difficulties with existing tools, as long as the Cu thickness are proportional shrunk to keep the width/ height aspect ratio, below pitch of 6 μm, it is difficult to make such fine pitch layers on top of other layers, since the topography of multiple RDL with any planarization, that is out of the depth of focus (DoF) range of 2 μm and 1 μm, and such 2 μm / 4 μm pitches, would be limited to the first RDL in the multiple RDL scheme.

Cu dual damascene technology are generally used in ICs manufacturing or silicon interposer fabrication. CVD dielectric films (Si oxide, Si nitride) are commonly used in the modern IC fabrication fab (90nm and beyond), and can be used for up to three levels of 1um Cu RDL .

A comparison between a Cu dual damascene process and traditional organic RDL process are shown below. The Cu dual damascene process can provide a flat surface with excellent topography and we can combine this advantage with traditional RDL process to resolve the surface topography issue for the multiple RDL layers. For example in 3 layers RDL structure, we can use one dual damascene layer and two organic RDL layers to reduce the TTV of surface topography and then satisfy the DoF requirement of photo-resist materials.


Cu dual damascene technology is a challenge for traditional bumping process and tools, especial for the lithography, Reactive-Ion Etching (RIE), Cu electroplating, and Chemical-Mechanical Planarization (CMP) steps. For the lithography process of Cu dual damascene, the key points are the opening dimension and profile of photoresist materials after the lithography process. Current development and research direction focus on the high resolution photo-resist materials and high numerical aperture (NA) exposure tools. The dielectric material of Cu dual damascene is generally silicon oxide (SiO2). In order to increase the oxide etching thickness accuracy, a thin silicon nitride (SiNx) film is deposited as stop layer between the oxide layers.

The figure below shows a silicon interposer structure with TSV and there are 3 dual damascene metal layers with u-pad in frond side of interposer and there is one RDL layer with C4 bumps on the backside of the interposer. The L/S are 1um and thickness 1um also for 3 dual damascene layers. And layers are connected by 0.5um diameter and 0.9um thickness via opening.


Hybrid integration of the fine pitch CVD RDL with polymeric dielectric RDL is shown in the figure below. It is a substrate-less package with 0.4mm pitch BGA balls; the package size is 15mm x 14mm with one CVD dual damascene RDL with 2/2um line L/S combined with two organic RDL with 5/5um and 10/10um line L/S.



The top die jointed with RDL by 40um pitch u-bump and molded by molded underfill (MUF) technology. The CVD oxide and nitride RDL 2/2um line L/S connected to organic RDL 5/5um line L/S by 10um via open which made by deep reactive-ion etching DRIE process. The second RDL contains 10/10um line L/S. This hybrid test vehicle passed open/short test after 96hrs of HAST, 1000 TCB cycles and 1000hrs of HTS.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 294 ECTC 2016: IMEC Discusses Economics of TSV Implementation Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2016 IEEE ECTC conference.

IMEC – Economics of TSV Implementation Options

IMEC discussed their conclusions about the integration cost of TSVs for TSV middle vs TSV last processing. A 3D cost model developed at IMEC was used to analyze the cost of the different TSV integration approaches with different dimensions investigated for each flow.


TSV lithography

The main difference in this step between the TSV middle and TSV last flow is that the TSV middle lithography is processed at a FEOL-fab compatible tool. In the case of TSV last an OSAT-fab compatible lower-cost tool can be used. This difference results in a TSV litho step cost which is approximately 30% more expensive for the TSV middle flow compared to TSV last flow. Furthermore, no difference on the lithography cost is observed due to different TSV dimensions.

Si TSV etch

The processing time for TSV etch depends on the TSV depth and the TSV aspect ratio. Smaller depth TSVs have faster etching times (for example the 5×50 vs. the 10×100 TSV process). In addition, TSVs with more aggressive aspect ratio have slower etching times (the 3×50 TSV middle compared to 5×50 or the 5×50 TSV last compared to 10×50).

TSV liner processing

Following the opening of the TSV hole in silicon, an insulating oxide liner layer is deposited. In the case of TSV middle, different liner deposition approaches are applied, depending on the aspect ratio of the via. In the case of an aspect ratio up to 1:10 a TEOS oxide is deposited. As the TSV aspect ratio becomes more aggressive (for 3×50 and 2×40 TSVs), a more conformal liner layer is required with higher uniformity in the liner thickness along the TSV. Therefore, a PEALD oxide deposition approach is preferred to achieve a liner thickness of 100nm, capped with 30nm SiN layer.

In the case of TSV last, the liner needs to be opened (etched) at the bottom of the via prior to further processing, therefore a highly conformal layer is required. For this reason a PE-ALD oxide deposition is used for all TSV geometries processed with the TSV last approach.

TSV liner opening (for TSV last flow) In the case of TSV last process flow, the oxide liner layer at the bottom of the TSV should be opened after deposition to allow for a conductive path towards the metal layers at the TSV bottom. This is one of the differentiating steps between the TSV middle and TSV last flows. Longer processing times (resulting in smaller tool throughput) are required for the narrower TSV diameter sizes.

TSV Barrier and Cu Seed processing

The first steps towards metallization of a TSV structure are the deposition of a barrier layer to prevent Cu diffusion, followed by a deposition of a Cu seed layer that will allow the Cu filling of the TSV through electroplating. Different deposition options are considered for different TSV sizes . In the case of TSV middle with aspect ratio 1:10 (i.e. 10×100 and 5×50), a PVD Ta barrier layer followed by a PVD Cu seed layer can be applied. As the TSV diameter is scaled further and the TSV aspect ratio becomes more aggressive, alternatives such as ALD processing are required. ALD deposition of 12nm TiN has been demonstrated as a successful barrier layer for a 3×50 TSV middle structure. The barrier and seed layers should be removed by CMP after the TSV processing flow. The cost of the CMP process depends on the thickness of the deposited layers. Therefore, the thin layers deposited by ALD can offer an advantage from a cost perspective when the processing cost of the CMP is also considered.

TSV Cu plating and impact on CMP

Plating time and material cost for the TSV filling depends upon the depth and the diameter of the TSV structure. TSV plating results in an overburden of Cu plated on top of the entire wafer area that needs to be removed by CMP. The Cu CMP process has two stages: (i) bulk Cu polish that is relatively fast and removes most of the plated Cu and (ii) fine Cu polish that is slower and clears the remaining Cu traces from the wafer surface, including the Cu seed layer.

Cost Comparison:

The overall processing flow cost can now be compared for different TSV geometries as shown in the figure below.


In the case of the TSV last processing, the additional costs for the PE-ALD liner, etching the TSV liner within the via, and the backside CMP result in higher processing cost for the TSV last 5×50μm flow by up to 10%.

In the figure below it is demonstrated that scaling the TSV size and the TSV pitch is possible while keeping the processing cost under control. This is achieved by replacing the thicker PVD deposited layers used in the larger TSV geometries with thinner ALD layers for the scaled TSV sizes. Although the processing cost for the ALD layers is higher, the cost for CMP polishing of these thinner layers is lower. This tradeoff helps to control the processing cost as the size and pitch of TSV is scaled from 5×50 down to 3×50 and 2×40 TSV sizes.


Overall it has been shown that main cost contributors for TSV processing are the CMP, the deep Si etch, and the barrier and seed deposition steps.

IMEC – Bumpless Process for 10µm Pitch Assembly

IMEC detailed the use of Damascene processing to achieve a bump-less assembly process for sub 10um pitch interconnects.

Microbumps and high density TSV pitches enable high density interconnects between two or more chip stacks for different applications. However, the mechanical stability of microbumps, bump height uniformity, microbumps under-cut during seed and barrier wet etching, high aspect ratio lithography process, dicing and handling issues and difficulty in thermo-compression bonding (TCB) alignment and stacking for fragile microbumps in 10um pitch range ae serious concerns.

In the IMEC bumpless process UBM in the bottom die is embedded in BEOL dielectric and is fabricated in by damascene processing enabling less bump height variation, smooth UBM surface and thus pitch reduction. Schematic of the bump-less process concept is shown below. The top die which contains UBM and solder, the UBM is plated in dielectric followed by Sn plating in resist. After stripping resist and seed/barrier wet etching, polymer (CA6001B from Hitachi ) is coated and planarized by CMP or surface planer. After Sn plating and seed etch, microbumps were embedded in a spin coated polymer followed by a soft bake step. For planarization, CMP and surface planer tools were used. Polymer acts as support material for planarization and also as underfill material for 3D stacking.


During fast TCB bonding, the polymer starts to reflow and bond to the oxide followed by Sn / Cu reaction and IMC formation and final polymer cure.

Processing is on-going in IMEC with 5um pitch TSV and bump for die to die, die to wafer and wafer to wafer bonding applications.

For all the latest on 3DIC and other advanced packaging applications, stay linked to IFTLE…

IFTLE 293 Sarda Voltage Regulators; ECTC 2016 – Copper Pumping; Copper Pillar on Embedded Trace

By Dr. Phil Garrou, Contributing Editor

Sarda Heterogeneously Integrated Power Stage

Sarda, UTAC and AT&S announced at the recent Int Symp on 3D Power Electronics, Integration and Manufacturing Symposium that they would be using UTAC’s “3D SiP” technology (based on ECP technology from AT&S) to deliver small, fast voltage regulators for use in data centers.

Sarda’s Heterogeneous Integrated Power Stage (HIPS) technology replaces Si switches with GaAs switches in voltage regulators which reportedly increases switching frequency by 10X, improves transient response by 5X and reduces size by 80%. This in turn can reportedly reduce data center power consumption by 30%.


Continuing our look at the 2016 ECC presentations:


Osaka Fine Feature Electrodeposition Res Center – Copper Pumping

Kondo from the Fine Feature Electrodeposition Research Center in Osaka discussed his solutions for copper pumping. We have known for years that the use of silicon vias (TSVs) causes copper extrusion during copper annealing due to the mismatch of the thermal expansion coefficient of Cu and Si. This extrusion can cause damage to the interconnect above it, as shown in the figure below.

Beyne and co-workers at IMEC developed a solution for avoiding this damage by annealing the TSV at >425 °C and then CMP’ing the resultant copper protrusions before building the layers of on chip interconnect.

Kondo 1

The Small Feature Electrodeposition Lab has now reportedly developed an additive “A”, which restricts the copper pumping phenomena and thus eliminates the need for CMP. A comparison of pumping with and without additive A at 450°C is shown below.

Kondo 2

Pumping at 450°C (a) room temp; (b) without additive “A” at 450°C ; (c) room temp ; (d) without additive “A” at 450°C


The resistivity of electrodeposited copper TSV after 450℃ annealing for the wiring is only 1.09x that of conventional electrodeposited copper.

Initial investigations of the mechanism of this reaction point to 100nm carbon deposition into the triple point of the copper grains which causes unit cell contraction upon annealing .

Amkor – Copper Pillar on Embedded Trace

The continuing push toward miniaturization in both planar & stack-up dimensions, has driven the use of chip-scale packages (CSP) in consumer microelectronics.

The state of the art method for joining die and substrate is currently using solder-capped copper pillars. The pillar and solder are previously plated onto the die through wafer level processing. The advantages of copper pillar technology have been well documented and include greater reliability by inhibiting electromigration , as well as enabling fine pitch interconnects.

There have also been advances on the substrate side where thinner packages are the goal. One

enabling technology has been the development and use of Embedded Trace Substrates (ETS), where the top-layer metal is embedded into the dielectric material instead of being deposited on top of it. This results in a near-planarity of the dielectric material and the top-layer of metal as shown in the figure below.

amkor 1

The advantages of ETS include a lower profile, potential layer reduction and reportedly lower cost. Substrate manufacturing costs and stack-up height are both reduced due to the absence of a core material. Layer reduction can take place due to removal of restrictive core-layer design rules.

Warpage is a real concern in the assembly of packages with ETS, but for applications where warpage can be properly managed, the combination of copper pillar bonding on ETS offers low-cost, thin solutions for packaging advanced devices.

While the near-planarity of metal traces with the surface of the substrate in ETS is effective at reducing the risk of bump-to-trace shorting, there is a corresponding increase in the risk of electrical opens especially as L/S shrinks. Amkor has developed a model to test for interconnection reliability between copper pillar bumps and ETS bond pads, based on design parameters and in-process variables. The critical recess depth of the ETS bond pad is identified as a key parameter linked to interconnection success. Reducing the risk of non-wets requires attention to design and processing during substrate manufacturing, bumping, and assembly.

For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…


IFTLE 292 New Fab Construction? Look to China; Rumors from ECTC: InFO — ASE — DECA

By Dr. Phil Garrou, Contributing Editor

Fab Construction Declining, New Construction be mainly in China.

Over the last few years, IFTLE has detailed the slowdown in scaling which is leading to the construction of fewer and fewer latest node fabs. We have also noted that this maturity of our industry has led to the consolidation trend that has been so prevalent the past few years.

Peter Clarke of EE Times Europe recently reported the latest SEMI data on new fab construction [link]. They predict 19 wafer fab starts in 2016 and 2017 and predict that China, will be responsible for more than half of them. This is a low total number by historical standards consistent with our trend of slowdown.

(12) of the fabs are 300mm, (4) are 200mm, and the (3) LED fabs are 150mm, 100mm, and 50mm respectively. Activity in the 3D NAND, 10nm logic, and foundry segments is expected to push equipment spending up 1.5% globally vs 2015. Fab equipment spending declined by 2 percent in 2015. SEMI lists a probability 60% or higher for these predictions but admits that some may be delayed.

fabs 1

The heavy participation by China is also consistent with IFLE noting that China would be the Wild card when it comes to future IC production (see “IFTLE 238 ASE & the Apple watch, ASE / TDK JV; China: the Wild Card” [link]).

SEMI estimates far more manufacturers are looking at fab upgrades or facility conversions as shown in the table below. IFTLE agrees that this is likely the way of the future.

fab 2

Continuing our look at the 2016 ECTC

Wafer Level Integrated Fan Out Packaging (InFO) – TSMC



IFTLE has stated over and over that the front end practitioners are paying more and more attention to packaging because they understand that it is the future way of customizing a circuit and could have more value in the long run than further scaling. (At least till the CMOS replacement is found sometime in the future). This was never made clearer than by the rumors that TSMC had been selected as Apple’s exclusive manufacturer for this year’s A10 chip expected to power the iPhone 7 and new iPad models. “The new chip is expected to use a 16nm process combined with a new InFO packaging, which allows chips to be stacked on top of each other and mounted directly to a circuit board, instead of onto a substrate first, reducing both the thickness and the weight of devices. Apple is rumored to be TSMC’s first customer to use InFo.”[link]

In fact it is likely that this was also a main motivation for Samsung EM’s recent announcement that they would be entering the FO-WLP business by the end of the year.( see IFTLE 291 : “Samsung EM enters FO-WLP Packaging Mkt…” [link] ).

Session 1 paper 1 at the 2016 ECTC was a TSMC paper on InFO by Doug Yu and his team at TSMC. Up until a few years ago, Doug had been the key technology Mgr developing the latest front end copper low K interconnect for each succeeding scaling generation at TSMC. He now runs 2.5D and wafer level packaging like InFO…does that tell you anything ? I think it does.

Since they first indicated that InFO was on their radar , ~ 2012, TSMC has focused on presenting comparative data showing the better performance that InFO would deliver vs other options. This latest paper continues in that venue comparing the form factor and performance advantages of InFO PoP over std FC-PoP. What’s been missing from the InFO presentations has been any detail on the process flow. (see IFTLE 261: “….The info on InFO…” [link].

In IFTLE 261, we reported on a rumored InFO process flow which consists of (1)copper pillar plating on the die,(2) die placed face up on tape, (3)molding to generate reconstituted wafer, (4) polish down to reveal tops of pillars, (5) RDL processing on this polished surface. The capability for finer features than standard fan out packaging comes from the more planar starting surfaces and better control of the photo processes.

A prevalent rumor going around ECTC is that ASE will become the second source of InFO technology for the industry. Does this make sense ? Well ASE is known to be a preferred partner for TSMC packaging and ASE has won its own Apple contracts for supplying SiP for the Apple watch (see IFTLE 238: “ASE & the Apple watch…” [link]). So yes I’d say this is plausible.

In addition ASE and DECA have just announced that ASE has licensed the DECA FO technology and will be putting in a line to manufacture it. [link]

Is it logical that ASE is about to scale up two different fan out packages at the same time ?…..probably not.

It is more logical if the TSMC process and the DECA process are similar enough that this really constitutes only ONE line for both products.

The DECA process flow (as published in the 2013 IWLPC) is shown below.


DECA Process Flow

Enough said…

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