Author Archives: sdavis

IFTLE 288 Consolidation on the Conference Circuit: 2016 IMAPS Polymer Conf

By Dr. Phil Garrou, Contributing Editor

Conference Consolidation under IMAPS

Recently, consolidation has hit the conference circuit, much the same as it has hit the corporate world. The 2016 IMAPS Polymers Conference which we will discuss below focuses, as you might imagine, on the use of polymers in microelectronics. It has been a biennial conference sponsored 15X by DuPont and was held in Wilmington DE. It was acquired by IMAPS and for now continues to operate at the Wilmington location.

IMAPS has also acquired the RTI 3D ASIP Conference. As you may know, 3DASIP is the longest running 2.5 / 3DIC conference focused on commercialization and infrastructure. The IMAPS supported 2016 meeting will be held December 13-15th, at the Marriott San Francisco Airport Hotel in Burlingame, Ca. As in years past, all presentations will be invited.

Continuing in the technical direction that was started last year, 3D ASIP will grow its focus on not only 2.5 and 3D IC, but other competitive high density packaging technologies that are being developed. With the ending of the Ga Tech interposer conference they have asked Corning to join the polymer conference and provide a session on the status of this technology.

The US Technical Chair will be Alan Huffman from RTI, the European Chair will be Mark Scannell of Leti and the Asia Chair will be Mitsu Koyanagi of Tohoku Univ.

There will be two AM tutorials, plenary presentations to start off each day and (8) sessions structured and developed by 8 “topic leaders” who will develop their 3 or 4 paper sessions and serve as session chairs.

IMAPS 17th Symp on Polymers for Microelectronics.

Continuing in the Winterhaven DE site that has held these meeting for many hears, the conference was spearheaded by a 6 person steering committee and a 6 person advisory board.

Yole Developpement

Amandine Pizzagalli of Yole gave a nice presentation on the use of polymers in advanced packaging platforms. The following generic packaging slide first breaks down technology options into leadframe packages vs substrate based and non substrate based packages etc. Another conclusion from this slide which John Hunt made in a later talk was that ALL packages are fan out except wafer level packages.

yole 1

Their wafer count forecast shows that while fan out shows the strongest growth rate, FC based packaging is responsible for > 75% of all adv packaging wafer count through 2020.

yole 2

Yole’s 2015 marketing study shows that PI accounts for ~ 63% of dielectric usage in advanced packaging.

yole 3

ASE – Fan Out Packaging

In the fanout panel packaging session John Hunt of ASE made the point that while fan out today has taken the connotation of “eWLB” packaging, it truly has been around forever since all packaging except wafer level is fan out including all leadframe and substrate packaging. He showed the following chart for ASE fan out package offerings ad noted that ASE like many others were focusing on panel level processing to attempt to cut costs.

yole 4


For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 287 SMIC Ups the Ante on Packaging; IMAPS DPC 2016 part 4; SiP, Sputtered Cu Shielding and Si TF Caps

By Dr. Phil Garrou, Contributing Editor

SMIC Ups Ownership in JCET

Following the lead of global foundry leader TSMC, SMIC, in two separate moves has put an additional $0.5B into JCET (Jiangsu Changjiang Electronics Technology), mainland China’s largest semiconductor packaging assembly and test business, uping their ownership position to $14.25% and making it the biggest shareholder in JCET. [link].

SMIC used a straight cash investment and it’s subsidiary SilTech Shanghai which agreed to sell to JCET its 19.61 per cent equity interest in semiconductor packaging and test services company Stats ChipPac in exchange for JCET shares. SilTech, JCET and the China IC Industry Investment Fund jointly acquired Stats ChipPac in 2014.

With TSMC and SMIC moving into packaging (as IFTLE has predicted for years) it will be interesting to watch for the response from GlobalFoundries and or UMC.

Continuing our look at the IMAPS Device packaging Workshop


Bill Chen’s plenary presentation on SiP contained a nice section on WLP (or WLCSP as it used to be called). IFTLE has recently pointed out that WLP should end up being a very important package for IoT which need very small forma factor and very low cost. [ see IFTLE 268 IMAPS 2015 Part 1: A Comeback for WLP in IoT]

I admit to being very partial to the WLP package since I spent many years in the 1990s working with FCT and Unitive as they created the package and made it an industry standard.

Chen points out that the WLCSP of the 1990s paved the way for may other WL packages as shown below.


Based on Yole data, Chen estimates that todays leading edge smart phones contain ~ 35% WLCSP.

As technology developed to apply WLP to larger and larger die more applications came into reach and more I/O ae available at the same pitch as shown below.



Bunel of IPDIA discussed their “Low profile flip-type or embedded Silicon Capacitors in high speed decoupling and broadband filtering”. Communication applications are requiring compact capacitors with large capacitance and low impedance.

IPDIA silicon capacitor technology is based on the structure shown below which can be built in thin film technology with very low profile.

Ipdia 1

It is compared to a std MCC (multilayer ceramic) cap below.

ipdia 2

The silicon caps are thinner and have a smaller footprint than standard MLCC caps.

The main take away of this paper is that the insertion loss at frequencies above 15GHz is dependent on the environment and the mounting parameters. The comparison between the Silicon capacitor and the MLCC shows that on top of the performances required for the UWBB capacitors, the Silicon capacitors offer a combined solution of low profile, high capacitance and low ESR/ESL to meet the requirements in decoupling applications.


Amkor discussed sputtered copper vs metal can shielding for cell phone components. They contend sputtering is a lower cost smaller footprint solution.



The process flow is shown below.

amkor 2


Excellent shielding effectiveness is achieved, mostly above 30 dB, up to12 GHz for far field and up to 6 GHz for near field, and low frequency from10 MHz-100 MHz. Amkor recommends 3 μm sputtering copper solution for best shielding performance and lowest cost.

Hope to see a lot of you in a few week at the ECTC conference in Las Vegas.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 286 IME Forum; IMAPS DPC 2016 part 3: IMEC Assembly Challenges for 2.5/3D

By Dr. Phil Garrou, Contributing Editor

IME Forum

In late March IME held an industry forum in Singapore to discuss “High Density WLFO WLP for next gen mobile 2.5D/5G Systems” Of special interest was their process flow for PoP package constructed from a FOWLP as shown below. This is a chips last FOWLP assembly with access to the top surface by TMV (through mold vias) and subsequent formation of stacked memory as the upper PoP level.


Continuing our look at the 2016 IMAPS Device Packaging Workshop

IMEC – Assembly and Packaging Challenges for 2.5/3D

IMEC addressed assembly and packaging challenges for 2.5/3D. One the main changes we will see moving from 50um to 10um micro bump pitch will be the move from solder ball reflow to thermo-compression bonding.

imec 1

This will require the use of pre applied underfill to insure:

  • Mechanical connection (adhesion)
  • Protection of joints and chips during operation

Two types of pre-applied underfill are available:

  • No-flow underfill (NUF) – dispensed on bottom die
  • Wafer-level underfill (WLUF) – applied on top wafer

imec 2

If the TCB is done to quickly, heavy voiding results. A comparison of NUF and WLUF (which IFTLE sometimes calls WUF) is given below.

imec 3

The process flows for NUF and WUF are compared below.

imec 4

Amkor moves SWIFT and SLIM into Mass Production

Anyone questioning whether Amkor would move their high density TSV-less packaging technologies SWIFT and SLIM into HVM should question no more following their announcement that they have teamed with Cadence and will be releasing PDK for these technologies.[link]

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 285 2015 Foundry Sales; IMAPS DPC 2016 Part 2: Rumored Chinese takeover targets; Low Cost TCB?

By Dr. Phil Garrou, Contributing Editor

For those of you who haven’t seen the latest IC Insights list of 2015 foundry players, I have reprinted it below. TSMC is the leader with $26.4 billion in sales. TSMC sales were over 5x that of # 2 ranked GlobalFoundries (even with the addition of IBM’s chip business in the second half of 2015) and ~12x the sales of # 5 SMIC.  There are now only two IDM foundries in the ranking namely Samsung and Fujitsu. Without Apple, TSMC’s foundry sales would have declined by 2% last year and without the addition of IBM’s sales in the second half of last year, GlobalFoundries’ sales would also have declined by 2% in 2015. The top 13 players now account for 93%of all foundry sales. As everyone now understands, more consolidation is to come….get ready for it.

IC Insights 1

Continuing our look at presentations form the 2016 IMAPS Device Packaging Conference

In the IMAPS Global Business Council session, Bill McClean of IC Insights updated the attendees on recent IC trends including recent moves by Chinese entities to acquire a position in the global IC Industry. [ see IFTLE 238 ASE & the Apple watch, ASE / TDK JV; China: the Wild Card ]

In addition to the list below, he lists the following as rumored full or partial acquisition targets by Chinese entities: AMD, GlobalFoundries, MediaTek, Micron, Qualcomm, Renesas, SK Hynix, SPIL, TSMC and Toshiba.

IC Insights 2



The STATS presentation on SiP contained the following interesting slide depicting technologies vs applications overlaid on required L/S.



Strothman of K&S gave a presentations covering process options for low cost thermo-compression bonding (TCB). Stacked memory products are the highest volume products assembled today using TCB.

  • Micron HMC assembled on laminate with C2S (chip to substrate)TC bonders
  • Hynix HBM assembled on interposers using C2W (chip to wafer) bonders

Process options are shown below:


The cost of TCB becomes competitive with mass reflow bonding at high UPH.



Thus the question becomes how to achieve high UPH. Two key approaches can improve process UPH

  • Reduce temperature excursions for the bond head
    • Enable higher die transfer temperature
      • TC-CUF flux dip requires lower bondhead temp
      • TC-NCF needs lower transfer temp to prevent film damage
    • Hot touch down for TC-CUF
  • Remove sequential process steps
    • Flux dip process for each die adds time

KNS reports an optimized process through reduced temperature range and higher die transfer temp resulting in TC-NCF process at 2000 UPH and TC-CUF process at 2500 UPH significantly reducing overall costs.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 284 IMAPS DPC 2016: Amkor and Global TSV in Manuf; Leti Stacking of Caps

By Dr. Phil Garrou, Contributing Editor

The IMAPS Device Packaging Conference was once again held in March in Arizona. Here is a look at some of the more interesting papers from the conference.

AMKOR – 2.5/3D Readiness

In Amkor’s presentation on 2.5/3D readiness, the following slide showing product qualifications was of special interest.

amkor 1


2.5D & 3D product qualification data is shown below:

amkor 2 amkor 3


GlobalFoundries TSV Readiness

GlobalFoundries TSV technology is qualified and ready for HVM ramp for all <28nm nodes Fab 8. Std TSV size is typically 5 x 55um.

Thermo-compression bonding is used for assembly.

  • First, thin TSV die bonded chip to substrate (CoS) using non conductive paste (NCP)
  • Top dies then bonded chip to chip (CoC) during 2nd bond on top of first stack
  • TC-NCP process is used to minimize stress on ULK layers during cool down

GF 1

Warpage characterization is critical during design and reliability phase of development along with production yield improvement.

  • 3 different backside passivation layers were assessed in terms of impact of film stress on warpage
  • Backside passivation film stress does not play a big role in overall package warpage
  • Top Die Thickness impact on warpage
  • Package level warpage in the order of 125um was measured at peak temperature for 100um thin top die
  • With 260um thick top die package warpage was reduced to 80um at peak temperature
  • Packages with 100um top die and thus increased stress / warpage clearly showed cracks appearing in the Cu pillar joints. Thus higher warpage clearly leads to degraded electrical performance of copper pillars in the corners of the package

CEA Leti

While most of us were focused on 3D stacking of memory chips, CEA Leti was studying the stacking of capacitor chips. Using the PICS capacitor technology of IPDIA, Leti demonstrated that a smaller thin film cap footprint could be achieved if silicon caps are stacked and connected in parallel.

leti 1

Several attacking technologies are proposed including TSV and more traditional WB.

leti 2

Various packaging solutions are presented including a molded version (shown below) but IFTLE strongly disagrees the inference that such packages can withstand near 400C since IFTLE has expressed many times that thermal stability needs t be determined from isothermal TGAs NOT ramp TGAs like the one show. Ramp TGAs tend to highly exaggerate the thermal stability of the samples in question, for instance epoxy mold compounds are NOT stable at anywhere near 400C.

leti 3

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 283 Will Packaging Make the Difference for TSMC?

By Dr. Phil Garrou, Contributing Editor

The Taipei Times headline on April 18th read “New packaging may spur TSMC growth” adding that despite its weak revenue growth guidance for this quarter, TSMC, might see stronger growth from next quarter thanks to its InFO (integrated fan out) packaging technology [link].

The Times reports that InFO could help TSMC beat rival Samsung and win more A10 application processor orders from Apple, because the technology offers “…lower costs, higher speed and thinner form factor when compared to conventional flip chip packaging”. TSMC is preparing a complete InFO portfolio aimed at different package sizes and applications. In a conference call with investors on last week, TSMC CEO C.C. Wei stated that they have almost completed equipment installation and expect to complete customer product qualification shortly. They plan to ship volume production shortly. Estimates are that the revenue contribution from InFO packaging could total US$300 million this year.

IFTLE has previously reported that TSMC had purchased a facility in Longtan, Taiwan (from Qualcomm for $85MM) and was turning it into a facility devoted to the manufacturing of integrated fan-out wafer-level packaging (InFO-WLP) technology. [see IFTLE 219 “TSMC INFO factory…” [link]

fig 1


Apple is expected to unveil its new iPhone in the second half of this year. Daiwa Capital Markets analysts estimates that Apple’s order split for A9 processors (last generation) was 45% for TSMC and 55% for Samsung, but projects TSMC could take more than 50% of the A10 processor business, due in part to the superior packaging technology now being offered by TSMC. Other smartphone chip vendors are reportedly looking at adopting TSMC InFO packaging technology in the near future.

IFTLE has reported previously that TSMC lost the chance for making Apple A3 processors to Samsung because it lacked the capability to package and test the chips [link].

YSIC (Yuanta Securities Investment Consulting) claims the InFO technology is at least 20 percent cheaper than flip chip packaging. YSIC notes that “… it is becoming more difficult to solely rely on front-end tech node migration to drive better performance and cost” , a statement that should be very familiar to readers of IFTLE.

fig 2


In 2014, IFTLE discussed TSMCs announced ambition of becoming a major player in full back-end packaging services with their plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016 [ See IFTLE 190 “TSMC Focus on Packaging….”] [link] . Based on this roadmap, TSMC would become the 3rd leading packaging company in Taiwan by 2016, trailing only ASE and SPIL.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 282 Unique GaN Packaging Solutions from HRL

By Dr. Phil Garrou, Contributing Editor

Wide band gap semiconductors are extremely attractive for power electronics applications. GaN is a binary III-V wide-band gap ( 3.4 eV) material. Since GaN transistors can operate at much higher temperatures and work at much higher voltages than gallium arsenide (GaAs) transistors, they make ideal power amplifiers at microwave frequencies.

GaN has shown to have applications in optoelectronic, high-power and high-frequency devices. Because GaN offers very high breakdown voltages, high electron mobility, and saturation velocity it is also an ideal candidate for high-power and high-temperature microwave applications like RF power amplifiers at microwave frequencies and high-voltage switching devices for power grids.

GaN devices target both military (ship-board, airborne and ground Radars and high performance space electronics) and commercial applications ( base station transmitters, C-band Satcom, Ku-K band VSAT and broadband satellites, LMDS and digital radio).

There are basically two manufacturing (growth) processes, based on either Silicon or Silicon-Carbide substrates. GaN-on-Si has a significant cost advantage that is driving down the cost curve.

Initially, it seemed GaN-based devices would be affordable only for military applications, such as the development of electronic warfare, radar, and high security communications systems. However, material maturity, improvement in yield, expansion to 4” wafers and lower-cost silicon growth process has reduced GaN-based device costs and therefore an economical option for commercial applications as well.

Growth of the GaN device market has required the development of novel packaging solutions. Since GaN HEMTs are thermally limited significantly below the electrical capability of the devices. The challenge of a GaN HEMT is its heat flux at the gate fingers, which cannot be effectively addressed by conventional packaging and thermal management systems.

The DARPA ICECool program is developing liquid cooling solution for such hot GaN devices. [see IFTLE 119, “ICECool putsThermal Issues Back in Focus”.]

Non liquid cooling solutions are also under development at facilities such as HRL (Hughes Research Labs). While thermal heat spreaders are usually limited by the TIM (thermal interface materials ) used to attach them, The HRL solutions electroplate the heat sink right on the back side of the GaN device or module. For instance see the process sequence below, developed by Herrault and co-workers at the HRL Labs in Malibu CA.

First, GaN dice are temporarily bonded face down onto a carrier wafer using a temporary adhesive layer. The silicon body wafer, which consists of through-wafer cavities, is also bonded face down onto the carrier wafer, as depicted in the figure (a). Next, a Ti/Au seed layer is sputtered over the wafer, and copper is electroplated and subsequently polished down to the surface of the silicon wafer as shown in (b). This step forms the integrated thermal heat spreader. Therefore, there is intimate contact between the high-thermal-conductivity heat spreader and the high-power-density GaN device, which is beneficial for high-performance thermal management. The silicon body wafer was used as a polishing barrier for the copper removal, enabling a flat and smooth backside for additional processing steps. The combination of use of a silicon body wafer, electroplating and chemical mechanical planarization (CMP) process eliminates the need for a bonding layer between the chip and the heat spreader, and therefore reduces the overall thermal resistance from junction to baseplate.

The body wafer with copper-embedded GaN dice is then released from the carrier wafer. Front-side electroplated gold connectors and bond pads are then fabricated using standard microfabrication technologies. The silicon cap with TSV allows connections to the outside of the module.



The technology is compatible with integration of multiple chips (GaN, CMOS, SiGe) from different semiconductor technologies and with different thicknesses since the chip thicknesses are absorbed by the plated copper which is subsequently CMP’ed.


Compared to conventionally mounted GaN power amplifiers (PA) using AuSn solder, an electroformed (called ITAP) X-band PA showed 1.4x improvement in CW Pout (4.4W at 8 GHz) while the ITAP Ku-band showed 1.3x improvement in CW Pout (4W at 12 GHz). Compared to silver epoxy mounted PAs the improvement was 2x and 1.5x, respectively.

The figure below plots Junction temperature vs. dissipated power density using gate resistance test structures. The electroplated heat sinks (ITAP 1 & 2) increase the power handling by 1.45x (for Tj of 150°C) or reduce Tj by 40°C (at 2W/mm dissipated power density).



For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 281 ASE Takeover of SPIL Halted But Not Stopped; After Silicon Scaling Comes…

By Dr. Phil Garrou, Contributing Editor

The Taipei Times is reporting that the Taiwan Fair Trade Commission has suspended its review of ASE’s bid to take over SPIL (link). ASE’s prior acquisition of a 25% stake in SPIL has raised anti-trust concerns and fears that the merger would undermine competition in the market.

The decision means a victory for SPIL who has fought the acquisition. SPIL, which has repeatedly urged the commission to terminate the review of the acquisition welcomed the FTC’s decision.

ASE released a statement saying it will continue with our plan to acquire 100 percent equity interest in SPIL through all legally permissible means and avenues.” ASE will be able to continue raising its ownership in SPIL through open market purchases including intra-day trading, block trades, and acquisition of SPIL’s Nasdaq-listed American depositary receipts. If ASE’s stake in SPIL exceeds the 33% threshold, ASE will need to apply to Taiwan’s Fair Trade Commission (FTC) to merge with SPIL.

Intel Admits Moore’s Law Coming to an End…Predict What Might be Next

The recent issue of MIT technology review noted that “Intel will slow the pace at which it rolls out new chip-making technology, and is searching for the appropriate successor to silicon transistors.” (link)

They note that Intel in their 2015 10K report last month disclosed that it is slowing the timing at which it moves to the next scaling node. Intel has already pushed back the debut of its first 10nm chips from the end of this year to sometime in 2017 noting that it can’t keep up the pace it used to.

We all know it is becoming more difficult to shrink features further in a cost-effective manner, but this doesn’t mean that future devices will stop improving. Intel says that in the future, it will make improvements to the way chips are designed. They add that for many important new applications such as wearable devices and medical implants, chips are already powerful enough and power consumption is more important.

William Holt, who leads the company’s technology and manufacturing group, speaking at the International Solid State Circuits Conference said that for chips to keep improving, Intel will soon have to start using fundamentally new technologies in about four years. While Intel has not yet announced silicon’s successor, most technologists feel that the two leading candidates are spintronics and tunneling transistors.

Neither of these technologies offer increases in computing power and neither are ready for volume manufacturing. Both would require major changes in how chips are designed and manufactured. While neither offer speed benefits over silicon transistors, the new technologies would, improve energy efficiency something important for many leading uses of computing today, such as cloud computing, mobile devices, and robotics. Future chips connect to household, commercial, and industrial objects and thus will need to be as energy efficient as possible.

Sine packaging experts need to be aware of what’s going on in the front end lets take a look at these technologies.


Conventional electronic devices rely on the transport of electrical charge carriers – electrons – in a semiconductor such as silicon. Spintronics or “spin transport electronics”( also known as magnetoelectronics), depends on the intrinsic spin of electrons and the associated magnetic moment, in addition to its fundamental electronic charge, in solid-state devices. Devices follow the simple sequence:

1 – information is stored (written) into spins as a particular spin orientation (up or down),

2 – the spins, being attached to mobile electrons, carry the information along a wire, and

3- the information is read at a terminal.

Spin orientation of conduction electrons survives for a relatively long time which makes spintronic devices particularly attractive for memory storage and magnetic sensors applications, and, potentially for quantum computing [link].


Tunneling FET

The basic TFET structure is similar to a MOSFET except that the source and drain terminals of a TFET are doped of opposite type. A common TFET device structure consists of a P-I-N (junction, in which the electrostatic potential of the intrinsic region is controlled by a gate terminal. The device is operated by applying gate bias so that electron accumulation occurs in the intrinsic region. At sufficient gate bias, tunneling occurs when the conduction band of the intrinsic region aligns with the valence band of the P region. Electrons from the valence band of the p-type region tunnel into the conduction band of the intrinsic region and current can flow across the device. As the gate bias is reduced, the bands becomes misaligned and current can no longer flow.


For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 280 2016 European 3D Summit: Economic Profit in Today’s Micro electronics

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2016 SEMI European 3D Summit.


A very interesting chart from McKinsey on 2014 economic profit in the microelectronics industry (below). It is clear that very few companies are responsible for most of the economic profit.

McKinsey 1

The big 5 of Intel, TSMC, Qualcomm, TI and Samsung contributed > 70% of the entire industries economic profit for the last 15 years.

The following are the top 10 2014 assembly and test companies.

mckinsey 2

While market share is key in most semiconductor industry segments, there is no such link in assembly and test. Partnerships and portfolio appear to be the most important factors I assembly & test.

Their key trends for Assembly & test are:

mckinsey 3

None of these should be a surprise to readers of IFTLE.

Fraunhoffer Inst

In a joint presentation by the different Fraunhoffer Institutes in Germany, Andy Heinig show the following comparison of their SiO2 and polymer based processes.

Fraunhoffer 1

They indicate that the required number of routing layers not only depending on component complexity (i.e., pin count, pitch), but also on interposer material composition ( i.e. polymer vs SiO2 based)

– Polymer-based interposers with increased width and spacing of interconnect require a minimum of 3 metal layers

– Finer L/S of SiO2-based interposers allows routing on a single metallization layer

– Different consideration for power/ground nets (larger line/space) necessary


The 3M wafer support system for thinning and backside processing has been around for several years. Their standard process is shown below.

3M 1

They are also developing a thermal cure adhesive that can be mechanically debonded. This eliminates the LTHC layer and the laser module. Properties are shown below.

3M 2

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…


IFTLE 279 2016 European 3D Summit: Cost Modeling Memory Stacks; Needed Tech for Next Gen 3DIC

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the key presentations from the 2016 SEMI European 3D Summit that took place in January.

System Plus Consulting

System Plus Consulting showed an interesting cost comparison between AMD graphics modules with DDR5 vs HBM memory as shown below.

Sys plus 1

Also of interest is their look at the supply chain for the new AMD 2.5D module. ASE is assembling die from TSMC and Hynix on a UMC silicon interposer and mounting on an Ibiden substrate.

sys plus 2

Also of interest is their assessment of the Hynix HBM process cost.

sys plus 3


The Samsung 4 GB DDR4 DRAM stacks consist of 7um TSV on 67um pitch with 33um ubumps. The process uses thermocompression bonding, wafer level NCF underfill and Suss temporary bonding with Nissan (formerly TMAT) silicone underfill.

sys plus 4


Eric Beyne who has been active in 3DIC since its early beginnings focused on technologies that will be important for 3DIC to further penetrate the electronics industry. Beyne started out with a look at where 3D TSV technology sits as we enter 2016, namely interposers, FPGAs, graphics modules and memory stacks (shown below)

imec 1


Beyne sees the TSV themselves continuing to shrink going from the standard 5 x 50um a few years ago to a 2 x 40um in the near future. This has required changes in Cu barrier layer and Cu seed dep as shown below.



He proposed the following IMEC ubump strategy:

imec 3


For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…