Author Archives: sdavis

IFTLE 217 IMAPS 2014 Contd: Glass Interposers and Panel Processing

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2014 IMAPS Conference held in San Diego…


Shorey of Corning Glass gave an update on glass panel fabrication. He noted that “there are challenges in applying standard plating processes to glass,” but Autotech has recently reported significant progress in the ability to metallize glass vias using new adhesion promoters. They show complete fill with little overburden in 80um holes in 300um glass.

They also showed 370 x 470 x 0.3mm glass panels. A Rudolph Jetstep S3500 was used to create “~3um L/S…with additional work we fully expect to be able to resolve < 3um L/S”.  Smallest vias shown were 35um in 100um glass.

Corning 1


Rudolph Technologies

In an aligned presentation, Ruhmer of Rudolph discussed high resolution patterning to enable panel based advanced packaging.

When examining litho steps for panel processing Rudolph points to the following key items: minimum resolution, overlay accuracy, sidewall angle and CD control, depth of focus (DoF), exposure field size and warped panel handling capability.

– optical characteristics of suitable litho systems should offer N/A of 0.1 to 0.15 in order to meet L/S resolution requirements for high density interposers (1-2um)

– depending on the complexity of the interposer 5 or more mask layers per side can be required. In general the overlay accuracy should be ~ 1/3 the resolution limit of the system, so for a resolution of 1.5um the overlay accuracy should be 0.5um. Reconstituted substrates for FO-WLP is more complex due to die shift.

– accurate focus control across the wafer is required for tight CD control and consistent sidewall angle in photo dielectrics

– depth of focus for back end processing requires 10um or greater range, not typically available in front end steppers.

– exposure field size should at least cover one die to avoid stiching.

– in initial panel based FO-WLP testing warpage of approx 10mm was observed for a Gen 2 glass panel. Equipment with  warped handling features like switchable and compliant gaskets on chucks and handlers ae needed for litho and other processing steps.

Corning / Unimicron / Qualcomm

Corning, Unimicron and Qualcomm reported on their low cost interposer development program.

They sought to show feasibility of interposer manufacturing on their 200um thick 508 x 508mm glass panel format. Daisy chains are connected with 100um TGV (through glass vias) and 8/8 L/S.

The process flow using ABF dielectric is shown below.

corning-unimicron-qualcomm 1


Early handling led to glass breakage. The ABF lamination (Ajinomoto) gave the thin glass panel mechanical support more handlable.  Then vias were created through the ABF.

Warpage of the glass panels were compared to laminate (BT) panels of the same size with 200um core thickness. The glass panels showed 3X lass warpage.


DNP reported on a comparison of fabrication processes and electrical performance of silicon and glass interposers. I should note that these appear to be DNP processes, not necessarily standard processes. For instance they comment that silicon is fabricated on 200mm lines but glass can be fabricated on large panel lines. The facts actually are that Si is fabricated commercially on 300mm lines and large panel glass interposers are in R&D stage.

Their silicon and glass processes ae compared below.



In the silicon process, the holes are formed by ICP-RIE. The wafer is then thermally oxidized and coated with PECVD SiN. The holes are seed sputtered then plated with Cu, CMP’ed and both sides covered with Cu/PI RDL. TSV are on 200um pitch.

In the glass process, 50um TSV on 200um pitch are formed in 0.3mm glass by focused electrical discharge (Recall AGC is a proponent of this method). After Ti/Cu seed the vias a electroplated with copper and the surfaces CMP’ed. Copper / PI RDL are added to both sides.

Glass interposers showed better high freq. performance than silicon as was expected.




Mori of Shinko described their development of Glass Interposers with fine pitch ubumps and their warpage results. They examined glasses with CTE’s of 3.2 and 9.5 ppm and corresponding moduli of 73 and 90 GPa. Their design rules are shown below.

Shinko 2-1


Three laminates were examined with properties shown in the table below:

shinko 2-2


Warpage of the die on interposer on substrate showed that warpage of the assembled stack is lowered with lower CTE laminate substrate but is not affected by the CTE of the glass Interposer. Modeling verified these results.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 216 3D ASIP Program; 2014 IMAPS part 2: MR for Amkor Copper Pillar Bumps

By Dr. Phil Garrou, Contributing Editor


It’s that time of year again to be thinking about registering for the RTI sponsored 3D ASIP (Architectures for Semiconductor Integration & Pkging) which will be held at the Burlingame Hyatt on Dec 10-12 [link].

RTI ASIP has been focused on 3DIC and 2.5D for 11 years now. As we are now finally seeing  commercial commitment from the memory suppliers and the graphics module manufacturers hopefully we are observing 2.5/3DIC  finally taking off. Unlike other, more academic conferences, RTI ASIP has always been focused on the commercial and business aspects of bringing 3DIC to the market place.

This years program includes two special pre-conference symposia . A  ½ day symposia 2.5/3D IC design tools and flows led by Herb Reiter will include speakers from Cadence, Mentor, Apache design, GF, Rambus and Qualcomm. There will also be a half day tutorial on the current state of the art in 2.5/3D processing led by yours truly with “drill and fill” covered by Dean Malta of RTI; Temp bond and via reveal presented by Severine Cheramy of Leti and assembly presented by Laura Mirkarimi of Invensas.    As a special bonus, those attending the processing tutorial will receive a free copy of “The Handbook of 3D Integration Volume 3: 3D Process Technology” edited by Garrou, Koyanagi and Ramm.

The regular conference includes presentations by Micron, Xilinx, Nvidia, GF, Synopsys, Nanium, Unimicron ad many more . Of special interest should be the updates on their DARPA ICECool  3D cooling programs by Bakkir of GaTech and Gaynes of IBM Watson and the IoT (Internet of things) presentations by Beica of Yole and Schulz of the silicon integration initiative.

Hope to see you there.

Amkor – Extending Mass Reflow to Finer Pitch Copper Pillar Bumping

Another key paper from the recent 2014 IMAPS Conference in San Diego was by Fernando Roa of  Amkor concerned with extending the current processing envelope for Copper pillar bumping using mass reflow (MR).

Thermo compression (TC) is typically applied for copper pillar bumping. In general, it is a slower more expensive assembly process since each die has to be positioned and mated before moving on to the next die. A bonding head is typically used to hold the die flat and in alignment with the substrate while heat is applied to complete the connection. In general MR throughput is 2X that of MR.

In contrast, MR bonding places the die and then reflows them all at once.  Std FC attach and capillary underfill is shown below vs thermo-compression (TC) bonding.  TC typically underfills with non conductive paste (NCP) or film since capillary underfills are more difficult to use with copper pillar bumps because of their fine pitch.

amkor 1


Amkor typically uses the MR process flow for copper pillar bump (CPB) from 200 to 100um pitches with minimum changes to the standard process flow.

For fine bump pitch (b), since the bumps are much closer together there is less room to create solder mask defined pads as show below. Since the bump diameter is close to the typical width of the trace they are allowed to form connection directly on the trace.

amkor 2


While typical MR assembly relies on solder self alignment during reflow, MR of solder to trace is more difficult since self alignment to solder catch pads is not possible. In MR of fine pitch bumps the solder wraps around the trace in contrast to TC joints that typically show solder squeezing out of the joints because of the compression.

Very precise selection and control of die thickness, substrate construction and substrate finish is necessary to reduce or eliminate solder shorts and non wets. Roa indicates that Amkor efforts are underway to extend MR to finer pitch bumping activities.

IFTLE 215 STATS Acquisition; Will SLIT replace TSV?

By Dr. Phil Garrou, Contributing Editor

Rumors on the SCP Acquisition

We have discussed the Acquisition of STATSChipPAC (SCP) in recent blogs [see IFTLE 195,  “STATS in play….” and IFTLE 198, “….STATSChipPAC suitors named…”.] In late August, Bloomberg News reported that Jiangsu Changjiang Electronics (JCET) and Tianshui Huatian Technology were working on offers for SCP [link].

IFTLE continues to hear rumors from multiple credible sources that the deal with JCET is imminent and that final price is being negotiated. While denials are being floated by JCET, we all recall that similar denials were also rampant in the recent IBM / GF deal till the last minute.

IFTLE is also hearing that during these negotiations SCP, like IBM, is loosing key personnel throughout the organization. But, whereas IBM personnel movement was to ultimate acquirer GF, not so for SCP and JCET. Rumors from SCP indicate that JCET will not be retaining any key Singapore management in an effort to lower their cost position. As JCET waits to lower the ultimate acquisition price, IFTLE believes they are also lowering the overall value of SCP. A company is its people!  There are also unsubstantiated rumors of customers leaving SCP because of this chaos.

While it may be 2015 before the deal is consummated, IFTLE can see SCP falling from the #4 OSAT position and is probably already behind PTI.

Will SLIT replace TSV?

At the recent IMAPS meeting in San Diego Xilinx and SPIL presented the paper “Cost effective, high performance 28nm FPGA with new disruptive Silicon-less Interconnect Technology (SLIT).

In the traditional Xilinx silicon based FPGA module the FPGA die with microbup interconnect are connected to the 4 layers of 65nm interconenct on the silicon inerposer which then has TSV and c4 bumps to connect power/grd and other incoming sgnals.

In the new SLIT technology the same FPGA slices are mated to 65nm intrconenct on silicon but no TSV are required since ther is selective Si removal and backside contact formation along with required inline wafer warpage control. The structure is EXPECTED to give lower cost while delivering better electrical performance. The structures are compared below.

TSV “drilling and filling” are eliminated as are thin wafer handling, backside reveaand many inspect and metrology steps.

xilinx 1


(a) traditional Xilinx FPGA with silicon Interposer; (b) FPGA without interposer

Xilinx 2


(C) SLIT in X-section

The 65nm interconnect are created on std bulk silicon The bottom most dielectric layer is selected to have high selectivity during subsequent backside etch. The top of the metallization interconnect layer is capped in 45um pitch pads and microbumps.

The FPGA die are  thinned diced and stacked onto the interconnect wafer. After reflow the ubump gap is underfilled and overmolded and the mold cmpd is ground down to expose the die top surface.

Subsequent wafer thinning is done to the dielectric etch stop layer.  Contact holes re etched in the dielectric and pads and balls are created/placed.

The main processing issue is wafer warpage, especially after the full silicon removal. Stresses are balanced with a reinforcement layer and other stress controls during the processing.

This is certainly a very interesting proposed structure and IFTLE will be keeping an eye on SLIT processing.

More from IMAPS in subsequent blogs

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 214 Nanium’s Mamouth WLCSP, IBM Deal Done; Cu WB at TI

By Dr. Phil Garrou, Contributing Editor


Most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB fan out technology and is supplying such packages on 300mm wafers.

NANIUM also has extensive volume manufacturing experience in WB  multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package.

nanium 2

In 2012 Nanium licensed the 300mm FC bumping and Spheron fan-in WLCSP technologies from Flip Chip International (FCI) [link]. After completing line setup and qualification for that technology, the company added the capability to manufacture fan-in WLP product.

Today, they call themselves a “Wafer Level Packaging solution provider” as more than 90% of their business is now WLP.

In May we discussed Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” that proposed eWLB as an alternative to 2.5D silicon with sufficient capability for many applications in high volume at reasonable cost.  [ see IFTLE 194, “…… SEMI Singapore part 3: Nanium, Fujitsu, EVG”]

NANIUM has now announced commercialization of a 29nm, 25mm x 23mm (about the maximum reticle size allowed),  fan-in WLCSP  on 300mm wafers for customer  Custom Silicon Solutions (CSS).

CSS reports that such large dies are usually packaged in WB-BGA or FC-BGA with underfill material between bumped die and FC substrate for board-level reliability.

Naniums WLCSP has 1,188 solder balls on a  0.7mm BGA pitch. It has successfully passed more than 400 temperature cycles on board (-25 – +100 C). Die are 475um thick.


IFTLE Agrees that WLCSP technology has traditionally been limited to chips less than 7mm and the packaging community has been looking for technologies to allow the manufacture of greater than 10mm WLCSP.

ITLE has contacted Nanium for further “insight” and learned that they use 380um BGA solder balls that collapse to 300um stand off height after reflow. Reliability testing of the large WLCSP are done without underfill and do not have a polymer collar or similar technology improving their reliability. PBO based devices pass 400 cycles and PI based devices pass 600 cycles. Nanium does note that the customer is underfilling when assembling to the board “to be on the safe side.”

When asked directly what they key technology breakthrough was/is Naniums’s Steffen Kroehnert responded, “There really in not one big thing…there are a lot of small things…material dielectric choice makes a big difference…design features such as trace and pad design and size , copper area loading, Cu thickness, thick UBM and optimization of solder ball  alloy all contributed.”

IBM Deal Done

Every once in awhile I break with normal journalistic decorum and like a little boy in the school yard get pleasure from shouting “I told you so” (OK…maybe a little more than every once in awhile).  My little Italian grandmother (Nonna) told me not to gloat when you were right about something because no one likes such people… but it’s hard to resist. [For my non US readers, gloating is “…dwelling on one’s correctness with smugness.”]

IFTLE came to the conclusion that IBM would sell off their semiconductor business several years ago when it became clear that future node fabs would cost far more to construct  ( $4-6B) than the IBM semi business was making on a yearly basis (~ $1B). These simple economics would eventually prevail. As they pulled so called “IBM friends and family” around them in NY a few years ago, it became clear that they were positioning to have one of these “friends” buy the business and become their supplier. It has been clear for more than a year that Global Foundries was the logical choice.

Some were shocked when rumors leaked that IBM was having to sweeten the pot with significant cash in order to get GF to take over their money loosing semiconductor operation. But, as I have explained previously, that’s what is required when  you take over a business that’s loosing ~ $2B / yr . What Global gets out of this deal is not the manufacturing capability or the customer list, but rather the people and the IP. Once they restructure I see this as a good deal for GF and for IBM employees who obviously were no longer required by their now ex employer.

IBM has now officially announced the deal with Globalfoundries [link].  IBM will pay GF $1.5B to take over their chip manufacturing operations, which will continue to produce processors used in IBM systems.

Recently reported revenues from IBM’s Systems and Technology segment, which includes the company’s computers, declined 14%. The company’s other hardware segment–the Power systems, based on IBM-designed computer chips, fell 12%.

Cu WB at TI

TI began shipping copper WB, which delivers a 40% increase in conductivity, in its products in 2008.  Today, all of TI’s assembly sites are running copper WB on all TI package types, including BGA, QFN, QFP, TSSOP, SOIC, PDIP and others.  Copper is currently 71 percent of TI’s total WB usage. Existing analog and CMOS silicon technology nodes have been qualified with copper WB, and all new TI technologies and packages are being developed with copper WB.

TI is currently shipping about two billion units of copper wire bond technology each quarter.  TI has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial.

TI 1

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 213 What’s New in Permanent Polymer Dielectrics: Dow, HD Micro, Zeon

By Dr. Phil Garrou, Contributing Editor

It’s been awhile since we looked at what is new on the dielectric market so we checked with a number of dielectric suppliers and asked what was new in their product lines.

Dow Chemical

The old Rohm & Haas organization has been running the Dow Electronics Materials business for a while now, basically since they were acquired by Dow. I knew they would do well when I observed them make the ill advised low-K SILK product quietly go away.

They certainly have beefed things up in the BCB product line as follows.

  • Toughened BCB has been developed with 3X the elongation at some expense to CTE
  • A Dry film grade is being developed with thicknesses up to 100um
  • A positive-tone, aqueous developable product, BCB, 6505 is fully commercialized
  •  A BCB based temp bond adhesive, XP-130215,  for wafer thinning and 3D stacking is being sampled

I have compared the properties of a few of these new products to standard photo BCB 4000 below.

Property Cyclotene 3000/4000 Cyclotene 6505 (aq dev) Toughened BCB  BCB Dry Film
Cure temp (˚C) 210-250 210-250 210-250   200-250
Tg 350 350 350   250
Dk 2.7 3.2 2.7   2.6
CTE (ppm) 42 45 70   63
Tensile Strength (Mpa) 87 99 93   80
Elongation (%) 8 13 25   13
Residual stress 28 29 24   28
H2O uptake (%) 0.25 1.1 0.3   0.1


The PI community has not been standing still either. PIs always known for their high temp stability and their superior mechanical properties has had some catching up to do when it came to curing temperature amongst other properties.

HD Micro offers the following product lines.

C-4 flip chip RDL layers:

–        HD 4100 negative tone photo PI

–        HD8800 positive tone photo PBO

–        HD 8900 positive tone low cure temp photo PBO

2.5/3D Adhesives:

–        HD 3000 non photo temp adhesive

–        HD 7000 photo PI permanent adhesive

Stress Relief and Passivation Layers:

–        PI 2545 non photo wet etch PI

–        HD 8800 positive tone photo PBO

–        HD 8900 positive tone photo PBO low cure temp

Properties of these materials are compared below:

fig 1


Zeon is introducing the new positive tone photo “olefin based” Zeocoat  CP 3010 designed to deliver a low cure temp, low stress coating. Below are the properties of the polymer determined after a 180 C cure.

Property Zeocoat CP3010 (cured at 180 C for 1 hr)
Water Abs (ppm)

(130 C;98%RH;100 hr)

Mod (GPA) 2.9
CTE (ppm) 51
Stress (MPa) 23
Tensile Strength (MPa) 97
Tg ( C) 196
Dielectric constant (1MHz) 2.9
Leak current (A/cm2) @2 MV/cm 1.0 e -10
Breakdown Voltage (MV/cm) 6.5


For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 212 A Little More Patience Required for 2.5/3D

By Dr. Phil Garrou, Contributing Editor

There is an old proverb that states “All things Come to Those Who Wait.” It is exemplified by the French cartoon (below) showing a cat patiently waiting for a mouse to exit his hole in the wall. I personally am not the waiting type wanting to get things done ASAP but most civilizations look at patience as a virtue.

fig 1

We’ve discussed the leading edge before. The leading edge is where the money is made. So while you don’t want to be too early, you certainly don’t want to sit back and wait to see if something is going to happen and let others drain all the profit from that early period of introduction.

Now having said that, let me counter by saying that “All things don’t come to those who wait”. I waited for thin film  MCMs to take off in the 90’s and early 2000’s and they never did.  A lot of us gambled and in that case – lost. Life is a gamble !

TSV technology and 2.5/3D has had its own  dichotomy. We couldn’t sit back and allow others to get there first so we all anteed up our time and money without any assurance that there is big money to be made on this technology. Like the cat, we have been waiting (some more patiently than others) for 2.5/3D to enter HVM when in fact there has been no assurance that the mouse wasn’t going to exit from another wall (i.e another technological solution as happened in thin film MCMs).

Anyone who understood what TSV technology could bring to the party, knew that HVM and actually new product design itself could not expand until foundry technology was available (since TSV were/are clearly going in during chip fabrication) and memory stacks were available, since foundries don’t make DRAM. Of course it all has to be at the right price, but if its not even available, what matters the price?

In terms of foundries TSMC [see: IFTLE 122, “TSMC officially ready for 2.5D….”, ] was the first to announce and GlobalFoundries is not far behind [see; IFTLE 142,  “GlobalFoundries 2.5 / 3D at 20nm…” or IFTLE 164, “Semicon Taiwan contd: GlobalFoundries Manocha Interview”  ] so those at the leading edge can now design in 2.5D. But what about memory ??

While UMC [see: IFTLE 135, “UMC / SCP Memory on Logic…” and a few others have made noise about entering the 3D market space they appear to be significantly further behind.

The status of memory

Memory, as IFTLE has noted several times, has been slower coming.

The DRAM industry has been undergoing significant consolidation in the last few decades. The recent acquisition of Elpida by Micron has left 3 major players in the DRAM business as shown below.

DRAM Mkt Share of the Big 3 [Source: Gartner 2014]

DRAM Mkt Share of the Big 3 [Source: Gartner 2014]

Moving forward the main roadmaps for DRAM suppliers all address: (1) reduce power consumption, (2) satisfy bandwidth requirements and (3) satisfy density requirements , all while maintaining low cost.

With DDR architecture running into a brick wall the memory suppliers have been focusing on new architectures that will deliver lower power, higher bandwith memory solutions.  These include wide IO-2, HBM (high bandwidth memory) and HMC (hybrid memory cube).

Definition, standardization and scale up of these memory technologies has simply taken longer than any of us would have liked, but these are the new architectures what will take advantage of TSV stacking technology.

TSMC has recently compared the different memory architectures relative to DDR and one another  in terms of bandwidth vs power and price.

Memory Architectures vs bandwidth, power and price. [TSMC]

Memory Architectures vs bandwidth, power and price. [TSMC]

I compare the technologies below.


Memory Std

Bandwidth        (GBps)




Wide IO 2



JESD 229-2

High end smart phones




HMC consortium

High end servers, networking, graphics


128 (gen 1) 256 (gen 2)



High end graphics, networking and HPC

Comparison of New Memory Architectures

As we head into the fall of 2014 the last probably most important of the big 3 memory suppliers, Samsung,  has now announced production of TSV based memory stacks [see: IFTLE 209, “Samsung announces TSV based DDR4 ….” ].

So we are about to have HBM for graphics modules, wide IO-2 for mobile products and HMC for HPC and high end servers. Now there can be no more excuses.

Within the next 18 months, if we do not see product introductions announced,  2.5/3D will begin to fade away until it is only remembered as another one of the bad bets we made attempting to stay on the leading edge…

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 211 Semicon Taiwan part 2: Unimicron, Yole, Micron

By Dr. Phil Garrou, Contributing Editor

Continuing our look at 2014 SEMICON Taiwan.


YH Chen of Unimicron addressed “Panel Level Embedded Substrate Technology.”

Unimicron puts forth a proposal that embedded packaging saves cost because it (a) decreases the substrates used,(b) decreases the area of HDI board needed, (c) better electrical performance due to the proximity of the chips.

Unimicron 1


Unimicron started embedded passives technology (EPS) in 2009 and moved to HVM in 2012. This is based on burying MLC (multilayer caps).

Buried chip technology called EAS has the following roadmap:

unimicron 2

They are also looking at embedded hea “slugs” to increase thermal performance.

Line Embedded technology (LE) uses lasers to creat fine fetures that are then plated up and CMPed to give L/s as low as 8/8um.

unimicron 3

In another cost reduction development project, they are looking at combining the non organic interposer and the organic substrate into what they call “flip chip embedded intrposer carrier” as shown below.

unimicron 4

Yole Developpement

Azemar of Yole Developpement looked at “Fan-out & Embedded Dies Technologies and market trends.”

Azemar explained again that 2 different approaches are developing for Embedded packages, i.e. FOWLP based on reconfigured molded wafers and embedded die based on PCB laminate materials and infrastructure.

Currently Nanium and StatsChipPAC hold > 80% of the FOWLP market though this is expected to change when TSMC fully enters the market with their InFo-WLP technology.

yole 1

A generic embedded die packaging flow is shown below.

yole 2

For embedded die packaging, a new supply chain is required since the die embedding will be done by the PCB manufacturer who is making the substrate.

AT&S appears to hold ~ 80% of the embedded de market. They initiated this space with the TDK DC_DC converter package but Yole reports very little HVM since then.

yole 3


At the CFO Executive Summit Strohbecke of Micron  looked at “Micron Technology and the Changing Dynamics of the Memory Semiconductor Industry: Their 2014 vs 2018 assessment of DRAM demand vs application shows an increase in mobile and server/networking at the expense of PC memory.



For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 210 IBM Global Foundries reaching closure?; Semicon Taiwan 2014 part 1: Hitachi Chem & SPIL

IBM / GlobalFoundries – On Again ??

When last we discussed the soap opera that is called the IBM Global Foundries negotiations, I confirmed that IBM was actually paying for GF to take the semiconductor operation (which has been losing ~ $2B/yr) off their hands.

Since then the media had announced that the deal was off. But this made no sense, IBM had gone to far and their Semi employees would be leaving on their own since this was no longer a site to develop a semiconductor manufacturing career. Indeed GF began hiring IBM employees.

On 9/19, the Poughkeepsie Journal reported that “a source involved in the negotiations” indicates that “they are headed to arbitration as early as next week in the latest effort to strike a deal for IBM to sell its semiconductor manufacturing operations.”

SEMICON Taiwan 2014

SEMICON Taiwan is always a gathering that produces Major packaging announcements.

The Advanced Packaging Technology Symp was chaired by C. S. Hsiao, Vice President, Engineering Center, SPIL.

The SiP Global Summit and 3D Technology Forum was chaired by CP Hung VP of corporate R&D for ASE and DC Hu Sr VP of R&D and new business development for Unimicron.

CP Hung DC Hu


Hitachi Chemical

Toba of Hitachi Chemical described their embedding insulation sheet (EBIS) for FOWLP and FCCSP. The process flow for FO WLP is shown below using PBO ( HD 8940 ) as the RDL dielectric.

hitachi Chem 1


Proper  EBIS CTE and modulus and/or  die thickness was shown to reduce warpage by as much as 60%.

EBIS was also used for FC CSP packaging:

hitachi Chem 3


Using EBIS as a laminated MUF replacement (mold and underfill) resulted in center voids in the package. Compression molding was necessary to achieve void free structures.


M Lu of SPIL addressed “The Next Wave of 2.5D Applications”.

As IFTLE has stated in the past, the composition of future interposers will depend on the density requirements of the applications. Right now the only technology available to satisfy “G1” requirements is silicon substrate technology.



SPIL has optimized the following processes in order to be able to address this market space.

spil 2


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…


IFTLE 209 Samsung announces TSV based DDR4; What is Intel eMIB?; Amkor says the wait for 3DIC is not over yet

By Dr. Phil Garrou, Contributing Editor

Samsung finally announces commercialization of TSV based DDR4

IFTLE has been reporting for awhile that a Samsung announcement of stacked memory based on TSV technology was imminent. [ see IFTLE 123 “Intels Bohr on 3DIC;Samsung DDR4 roadmap…” especially since similar announcements have already come from Micron and Hynix.]

On Aug 26, Samsung finally announced that it has started mass producing 64 GB DDR4, dual Inline memory modules (RDIMMs) that use 3D TSV technology. The new memory modules are designed for use with enterprise servers and cloud base solutions as well as with data center solutions [link]. The release is timed to match the transition from DDR3 to DDR4 throughout the server market.

Samsung has started operating a new manufacturing line dedicated to TSV packaging, for mass producing the new server modules. The new RDIMMs include 36 DDR4 DRAM chips, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dies. The low-power chips are manufactured using Samsung’s most advanced 20-nanometer (nm) class* process technology and 3D TSV package technology.

The new 64GB TSV module reportedly performs twice as fast as a 64GB module that uses wire bonding packaging, while consuming approximately half the power.

Samsung believes that in the future it will create even higher density DRAM modules by stacking more than four DDR4 dies using 3D TSV technology.

Samsung has been working on improving its 3D TSV technology since it developed 40nm 8GB DRAM RDIMMs in 2010 [see IFTLE 65, “Samsung’s 32GB RDIMM DDR3…” ], and 30nm 32GB DRAM RDIMMs in 2011 using 3D TSV.

Fig 1

Amkor’s Liang says 3DIC will take another 3 yrs to get to HVM

At a press event held prior to the official opening of Semicon Taiwan 2014, Mike Liang, president of Amkor Technology Taiwan, announced that “demand of 3D ICs may take another 3 years due to concerns of high production costs.” He added that “…at present, only a few specific applications that require extremely high performance ICs require the use of 3D ICs, but the amount of such 3D ICs is not sufficient enough to support a full production line.” I’m sure this served to pour cold water on the subsequent 3DIC tech forum!

Intel Announces Embedded Multi die Interconnect (EMIB)

Intel recently announced that a new technology “Embedded Multi-die Interconnect Bridge” or EMIB will be available to 14nm foundry customers [link].

They claim it is a “… lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package.” While neither Intel nor any initial press reports gave any indication of exactly what this means.

It is highly likely that this is tied to the issuance of patent application publication US 2014/0070380 A1 published March 13 2014 [link].

In simplified form interconnect bridges (“silicon glass or ceramic”) are embedded in a laminate substrate and connected with flip chip as shown below:

Bridge Interconnect as described in recent Intel patent.

Bridge Interconnect as described in recent Intel patent.

A cross section of the package is more revealing showing connections through the laminate and connections through the bridge substrate (316) which would be TSV in the case of a silicon bridge substrate. The underside of the bridge substrate (314) may be connected to another bridge substrate for further interconnect routing as shown below.

While there is no silicon interposer, there do appear to be TSV in the embedded interconnect substrate as shown below. While removing complexity from the IC fabrication by eliminating TSV from the foundry process, the packaging operation becomes much more complex.

Since the 2.5D interposer has been reduced in size to the interconnect bridges, this may reduce cost, but will increase signal length vs a true 3D stack or a silicon interposer 2.5D

Intel EMIB Module in Cross Section

Intel EMIB Module in Cross Section

While Intel released the following description: “Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed,” IFTLE thinks this is somewhat misleading.

The packaging analogy to what they have done is as follows:

A high density bumped chip could be put down on to a high density build up PWB,  but in most cases the high density bumped chip is placed on a smaller BGA substrate which is then put onto a lower density, lower cost PWB.  The latter is the lower cost solution. In this case, large expensive high density interposers are avoided, and the much smaller emib are used for the high density interconnect. It will be interesting to see what if any the cost differential will be here.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 208 ECTC part 3: Thermal Compression Bonding – STATS, Toray, Qualcomm

By Dr. Phil Garrou, Contributing Editor 

SCP Status

Before we continue our look at key papers from the 2014 IEEE ECTC Conference, the latest on the potential sale of STATSChipPAC (SCP). In June SCP, announced  that it ended talks with one party (thought to be ASE) while discussions with other potential bidders were continuing.

Bloomberg now reports that the Chinese chip-testing companies Jiangsu Changjiang Electronics Technology and Tianshui Huatian Technology are considering bids for SCP and that a deal for SCP, valued at ~ $ 1B could be reached early next month.  [link].

Semiconductors have been labeled a  “strategic industry needed for China’s economic development and national security” by the Chinese Govt. China announced increased financial support for the industry and plans to set up a national investment fund according to Bloomberg.

Continuing our look at key papers from the 2014 IEEE ECTC conference

Thermo-compression Bonding

The advent of 2.5 and 3DIC has caused revisions in the way area array bump interconnect is carried out. The packaging hierarchy has traditionally been for BGA balls (~ 500um) to connect packages t boards and for C4 bumps (100-150um) to connect chips to packages.

Chip stacking with requirements for tighter pitch would prefer to have copper to copper connection, but such thermo-compression bonding currently requires 350-400C, 200kPa and most importantly 30+ minutes which makes high volume manufacturing impractical. Therefore the industry has adopted the   micro-bump and the copper pillar bump for such mating.

Sematech has put out the following cartoon to show approximately when technologies have to be changed based on required pitch.



Most OSAT roadmaps show that standard solder reflow can be used down to ~ 40um after which compression bonding must be used to avoid shorting.



A closer look at these mucro bumps (see below) usually reveals a Ni barrier layer on a copper pillar capped with Sn/Ag solder.



Such fine pitch connections make it difficult to underfill and have driven the refinement of pre applied underfills [both film (called non conductive film, NCF) and paste (called non conductive paste, NCP) ]. These technologies only work when one has good manufacturing control over both solder reflow and underfill cure.

Let’s look at some issues concerning such interconnect that came up during ECTC 2014.


Y. Jeong detailed the “Optimization of Compression Bonding Processing Temperature for fine pitch copper column devices.”     They examined thermal compression with non-conductive paste which they call TCNCP. The heat transfer from heating source to bumps must be tightly controlled in order to achieve the optimized bump temperature for the purposes of melting and soldering. To minimize voiding issues such as air entraps, a very short time window for curing has to be used in the NCP process. They determined the key parameters as shown below.



They concluded that “to have a successful bond, one of the most important keys is to obtain an optimized temperature profile which considers the ramp up/down speeds and times. The ramp up/down speeds and times affects the NCP flow behavior, void creation, and residual stress of the final product. In this regard, the peak and dwell time shall be precisely controlled to provide enough time for melting and soldering of bumps with substrate pads.”


Y. Liu of Qualcomm examined “Filler entrapment and solder extrusion in 3DIC Thermo-compression uBumps.”  Qualcomm indicates that filler entrapment could negatively impact electromigration in the solder joint.

The main reason for filler entrapment is reported to be premature cure of the pre-applied underfill caused by not fully optimized process condition and/or bump geometry. Once curing initiates, solder wetting is no longer able to push out filler and underfill from the joint due to the increased viscosity of underfill.

They also find solder extrusion from the side of the ubumps and conclude through examination of large arrays of bumps that the extrusion appears to be random.




T. Nonaka of Toray described “High Throughput thermal compression NCF Bonding.”  Torray points out that thermo compression bonding suffers from throughput issues because of the process flow shown below which requires the bonding head to cool between chip placements.



They propose a logical process change where the die are all placed and then cured and reflowed at once (gang bonded) as shown below.



For all the latest in 2.5/3DIC and advanced packaging, stay linked to IFTLE…