Author Archives: sdavis

IFTLE 278 Omnivision Stacked CIS; Apple Fingerprint Sensor with TSV

By Dr. Phil Garrou, Contributing Editor

Sony Samsung and Omnivision are locked in a technology battle for superiority in CMOS image sensors. While Sony has the lead in stacking technology, i.e. stacking the sensor on top of the image processor and connecting them with TSVs, OmniVision and Samsung quickly adopted the same technology and gained design wins using stacked chip products.

Rumor is that Sony will be working with GlobalFoundries on chip stack CIS, instead of Samsung to avoid any conflict with Samsung who is also in the CIS business.

We recently updated the latest from Sony [see IFTLE 272] Now lets look at some of the latest activity from Omnivision and Samsung.

Omnivision CIS

We last looked in depth at Omnivision in IFTLE 199 [ see IFTLE 199 Omnivision Roadmaps 3D stacking for CMOS Image Sensors…”]

The Omnivision OV13860 introduced in late 2014 is a 13 MP back side illuminated sensor with 1.3um pixels (actually larger than other 13MP sensors). It is the first Omnivision’s CIS built with stacked die technology which separates the imaging array from the image sensor processing circuits in the stacked structure. This allows for more functionality to be incorporated on the sensor die while resulting in a smaller size due to the stacking. [link].

Omnivision then announced the OV16850, a 16MP imager for smartphones. Using an 1.12um pixel and leveraging OmniVision’s stacked die technology, which captures stills and video in native 16:9 aspect ratio. This was followed by the OV23850 a 23.8 MP high resolution CIS. (images below [link]


Credit: Chipworks

Omnivision Xsect

Credit: Chipworks


Samsung’s first entrant into stacked technology with TSV was also at 16MP with the Samsung S5K3P3SX in late 2014. The CIS die is face-to-face bonded to a 65nm Samsung image signal processor die and connected with W based TSV. The CIS die is fabricated on a 65nm CMOS process with 5 levels of interconnect as shown below. [link]

Samsung 16 MP

Credit: Chipworks

Samsing Xsect

Credit: Chipworks

iPhone 6s Plus Fingerprint Sensor

The Apple iPhone 6s now has a “touch ID” fingerprint sensor embedded in the Home button.

While it is now used for unlocking the phone , it will also be used for identification purposes for Apple Pay mobile payments. It will also probably be used for other online services in the future.

The new device has the same structure and capacitive technology as the previous one, but with changes in sensor design and packaging.

The 12.5×10.9mm sensor is incorporated within a rectangular shaped housing composed of a stainless steel ring and an aluminum base. The sensor is protected by a sapphire window coated with two different materials and supported by innovative assembly of dies and flex PCB. The finger print sensor allows it to scan the fingerprint just by pushing the button. The sensor has a resolution of 10,752 pixels with a pixel density of 500ppi. It uses a capacitive touch technology to take an image of the fingerprint from the sub epidermal layers of the skin.

Apple FP

The new sensor has two die, a sensing die manufactured with 65nm CMOS technology and an 0.18um ASIC logic die. The new sensor is implemented with TSV (shown below) which allows a better packaging and connection to the flex connector.

Apple finger print TSV

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 277 SEMI ISS 2016 Part 2: Scaling Under Pressure; Tsinghua Bets on Packaging

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the SEMI 2016 ISS meeting.

Pacific Crest

Daniel Bakshet of Pacific Crest Securities pointed to the following changes in the semiconductor industry:

– economics are becoming challenged as process complexity increases

– compute functions are shifting from local to the cloud

– PC, tablet and smartphone demand is decelerating or declining

– signs of maturation are emerging as M&A becomes a dominant theme

They use the figure below to make the point (as we have for several years in IFTLE) that moving to a lower node no longer results in lower costs.

pacific crest 1

They see less demand for advancements in local compute capability as more of the compute function is conducted in the cloud.

They project that device growth is more likely to come from lower end products and thus not likely to require leading edge chips. They actually predict a reasonably good chance that incremental wafer demand declines at the leading edge, while previous nodes thrive.

They see autonomous Vehicles and Robotics as the areas of future growth.


Micron’s presentation by Mike Sadler, VP of corporate Development focused on consolidation in the memory industry with the following interesting slide showing acquisition and partnership driven capacity growth at Micron.

micron 1


Bob Johnson of Gartner showed this nice summary of when the remaining players have announced that they will continue scaling.

Gartner 1



Sonny Hui of SMIC showed the following figure of the % of devices manufactured (assembled) in China.



Ron Huemoeller focused on Amkors high density SWIFT and SLIM packaging which we have detailed previously [see IFTLE 243 Amkor Fan Out Package Platforms] with the following product positioning slide and the following expected timeline.

Amkor 1

Amkor 2

China’s Tsinghua group looking to buy into Global Packaging Industry

Reuters recently discussed the offers to acquire 25% stakes in ChipMos, PowrChip and SPIL by the Tsinghua group in China. [link]

The Chinese state-backed conglomerate aims to buy into the island’s technology sector as a step toward building China’s own semiconductor industry. Tsinghua made offers in quick succession late last year for a quarter each of chip testing and packaging companies Powertech Technology Inc, ChipMOS Technologies Inc and Siliconware Precision Industries Co Ltd (SPIL). The company plans to inject a total of $2.6 billion into the three in exchange for stakes plus one board seat at each with no management control. The offers came after Micron Technology Inc rejected Tsinghua’s informal $23 billion takeover bid on the presumption of U.S. national security concerns.

Shareholders of Powertech and ChipMOS approved the plans in January as they seek capital to expand and survive in a global chip sector experiencing record merger and acquisition activity.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 276 SEMI ISS 2016: The Focus Shifts to Packaging

By Dr. Phil Garrou, Contributing Editor

The annual SEMI ISS (Industry Strategy symposium) meeting took place as usual in January in Half Moon Bay CA. What was different was something that IFTLE has been predicting for while: “In the future when the front end community runs out of advances they will begin to focus on assembly/packaging.” Well…the future is NOW.


Intel’s Corporate VP Babak Sabi got on the packaging bandwagon with his presentation “Maintaining the IC Scaling Edge through Packaging.”

He showed the following detail on their Altera FPGA demonstrator using their Intel EMIB technology [for technology detail see IFTLE 209 “Samsung announces TSV based DDR4; What is Intel eMIB?”]

Intel 1

The following is an interesting comparison of Intel’s understanding of feature size vs substrate technology.

Intel 2


Mike Campbell of Qualcomm focused on “module and 3D packaging as the new integration path for semiconductors.”

Showing the following example for future SiP heterogeneous integration in a 2.5D format and the required enabling technologies.

qualcomm 1


Dan Tracy – Dir of SEMIs Industry research group also focused in packaging in his presentation “It’s All About Packaging—In this Materials World That We are Dealing With” using materials supplied by TechSearch Inc.

Looking first at materials supplier consolidation:semi 1

Mobil products are certainly the driver for packaging.

semi 2

He offered the following comments for individual markets:

Mold Compounds

– $1.2B market size

– stable Japanese supply base

– focus on warpage control, CTE, low moisture, low ionics

– molded underfill (MUF) for CU pillar FC

– high TC and high V apps emerging


– global mkt $250MM

– currently 30+ suppliers [note from IFTLE so this is ripe for consolidation]

– new resins and fillers for fine pitch requirements

– No flow applied prior to chip placement – both liquid and film based

– use of mold compound as underfill

– increased use of board level underfill for CSP, BGA, WLPs

Wafer Level Dielectrics

– $90MM market

– requirements for new material entrants include – low temp cure, low warpage


Handle Jones of IBS presented the following projection for wafer level packaging which he claims is being driven by Apple. Note he projects that we will be approaching 1MM WLP wafers/month by 2020.


Jones also noted that with the acquisition of STATSChipPAC, JCET has become the worlds 3rd largest OSAT.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 275 3D ASIP 2015 Part 5: The Memory Suppliers

By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the 2015 3D ASIP, conference we’ll look at the presentations from some of the memory suppliers and users.


Higashi form Toshiba discussed TSV technology for NAND flash. IFTLE did not take this to be a product announcement, but rather a technology status report.

We are all aware that flash faced major obstacles continuing normal scaling so it recently moved to monolithic stacking. NAND scaling will stop its planar 2D approach at 10 nm. All market players have developed 3D NAND technologies where the memory cells are now vertically aligned. There are many competitive monolithic transistor stacking technologies reported as shown below.

toshiba 1

Higashi proposes that TSV flash will be required to achieve the high performance ( low latency and IOPS/W ) and low power required for performance SSD.

toshiba 2


23Gb and 256Gb prototype chip stack is shown below.

toshiba 3

At the 2015 Flash Memory Summit, they showed a prototype SSD using this TSV based NAND.

toshiba 4

It was proposed that the first application may be data center servers.


During Tom Gregorich of Micron’s discussion on “Challenges in the Development and Deployment of Ultra High‐Performance 3Di DRAM Systems,” he noted that the ASIC to DRAM interface s what controls the bandwidth and power usage. The Micron HMC uses SERDES interface which is great for performance but in order to make it in consumer products they will need a new interface type to drop pricing.

AMD / Hynix

3D ASIP supporters Bryan Black of AMD and Minh Suh of Hynix updated the 3D ASIP audience on the status of Hynix HBM memory stacks and the status of the first graphics product to hit the market with TSV stacked HBM memory, the Radeon R9 Fury Series GPUs.

AMD Hynix 1

The interposer is made by UMC in the 300mm Fab 12 foundry (UMC) in Singapore. UMC is reported to have entered into volume production very recently (July 2015).

Hynix compared current HBM1 to the soon to be released HBM2 in the following slide.

hynix 1


The feel that the new generations of HBM will expand their use into more market segments.

hynix 2



The Patti architecture and manufacturing process are quite different from the 3 main DRAM suppliers. In terms of architecture he separates not only the control functions but also has a separate layer for the I/O. This allows them to deliver “the right I/O for every need.”


For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 274 3D ASIP 2015 Part 4: Comparing Memory Architectures; On the Passing of Moore’s Law

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 3D ASIP conference, one of the themes of this years conference was the coming of age of 3D stacked memory which now comes in several flavors from several vendors. This week, we’ll look at the Yole review and next week finish off with a look at the presentations by Toshiba, Hynix, Micron, AMD and Tezzaron.


In the plenary presentation, Thibault Buisson of Yole spoke on the “Comparison of new Memory Architecture -3D TSV Memory Packaging trends!” Some of the recent product and technology announcements are shown below. After MEMS and CIS, stacked Memory has become the next segment to see adoption of TSV technology. Graphics has been the first application using 3D stacked memories.

yole 1

All of the major memory suppliers ow have TSV based memory stacked products.

yole 2

Yole estimates that the SK Hynix HBM stack price with an assumption of 50% gross margin will range from $12.68 to $18.01 per stack.

They further conjecture that the AMD Radeon pricing rages from $191 to $258 with the GPU dies represening 43% of the component cost; the (4) HBM stack representing 28% , the silicon interposer representing 14% and the package subsrate 12%

Toshiba has announced the world’s first NAND flash memory packages integrating (16) 128 Gb NAND memory devices connected together using TSV. The multi-layer chips feature 1Gb/s data rate, 1.8V core voltage and 1.2V I/O voltage. The new packages use 50% less energy on write operations, read operations, and I/O data transfers than Toshiba’s current memory products. (see more below)

yole 3

The stacked memory supply chain is also clarifying.

  1. The HBM stack (memory dies, logic die) is made by Memory Manufacturer
  2. The GPU die is manufactured by wafer foundry
  3. The interposer is also manufactured by wafer foundry (could be a different one compare to GPU)
  4. The PCB package substrate is made by a substrate manufacturer
  5. The final assembly (HBM, GPU, interposer, interposer on PCB, passives assembly and BGA balls) is performed by an OSAT.

yole 4

X-sect comparison of Hynix HBM to Samsung stacked DDR4 is shown below.

yole 5

On the Passing of Moore’s Law

Every once in awhile you find an article and say “this is great, this is exactly as I would have written it”

I recently found such an article on the passing of Moore’s Law …or…as the author Peter Bright states it

“…Moore’s Law has passed away at the age of 51 after an extended illness” [link]

I hate to take up space just quoting him, but as I said I couldn’t have written it any better, so…

“In the 2000s, it [became] clear that … geometric scaling was at an end, but various technical measures were devised to keep up the pace of Moore’s law…. At 90nm, strained silicon was introduced; at 45nm, new materials to increase the capacitance of each transistor layered on the silicon were introduced. At 22nm, tri-gate transistors maintained the scaling.

Even with EUV, it’s unclear just how much further scaling is even possible; at 2nm, transistors would be just 10 atoms wide, and it’s unlikely that they’d operate reliably…as the transistors are packed ever tighter, dissipating the energy that they use becomes ever harder.

The new techniques, such as strained silicon and tri-gate transistors, took more than a decade to put in production. EUV has been talked about for longer still. There’s also a significant cost factor. Technology may provide ways to further increase the number of transistors packed into a chip, but the manufacturing facilities to build these chips may be prohibitively expensive.

Compounding all this is that all these extra transistors have become increasingly hard to use. In the 1980s and 1990s the value of the extra transistors was obvious: the Pentium was much faster than the 486, the Pentium II much faster than the Pentium. Those easy improvements stopped coming in the 2000s. Constrained by heat, clock speeds have largely stood still, and the performance of each individual processor core has increased only incrementally. What we see instead are multiple processor cores within a single chip. This increases the overall theoretical performance of a processor, but it can be difficult to actually exploit this improvement in software.

These difficulties mean that the Moore’s law-driven roadmap is now at an end. ITRS decided in 2014 that its next roadmap would no longer be beholden to Moore’s “law,” and… the next ITRS roadmap, published next month, will take an approach it describes as “More than Moore.”

IFTLE is in full agreement, as you know IFTLE thinks technologies like 2.5 and 3DIC have replaced Moore’s Law. May Moore’s Law rest-in-peace…

Those who continue to preach that “Moore’s Law is still alive and well” are akin to those who claim to have seen Elvis yesterday on the streets of Nashville!

For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…

IFTLE 273 Samsung Announces HBM2 DRAM; 3D ASIP Part 2 Prismark

By Dr. Phil Garrou, Contributing Editor

Samsung announces 4GB HBM2 DRAM

Samsung Electronics announced that it has begun mass producing the industry’s first 4-gigabyte (GB) DRAM package based on the second-generation High Bandwidth Memory (HBM2) interface, for use in high performance computing (HPC), advanced graphics and network systems, and enterprise servers. [link]

The newly introduced 4GB HBM2 DRAM, uses Samsung’s 20nm process technology and is reportedly more than seven times faster than the current DRAM.

The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit (Gb) core dies on top. These are then vertically interconnected by TSV holes and microbumps. A single 8Gb HBM2 die contains > 5,000 TSV holes, which is more than 36 times that of a 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.

Samsung HBM2 memory

Samsung’s new DRAM package features 256 GBps of bandwidth, which is double that of a HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips. Samsung’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds ECC (error-correcting code) functionality to offer high reliability.

Samsung also plans to produce an 8GB HBM2 DRAM package in the next 12 months. Offering designers a 95 percent space savings vs GDDR5 DRAM.

Samsung announced that production volume of HBM2 DRAM will increase over the remainder of the year.

The second-generation HBM (HBM2) technology is outlined by the JESD235A standard. It uses 128-bit DDR interface, 1024-bit I/O, 1.2 V I/O and core. Just like HBM1, HBM2 supports two, four or eight DRAM devices on a base logic die (2Hi, 4Hi, 8Hi stacks). HBM Gen 2 expands capacity of DRAM devices within a stack to 8 Gb and increases supported data-rates up to 1.6 Gb/s or even to 2 Gb/s per pin.

Continuing our look at the 2015 3D ASIP Conference…


Brandon Prior of Prismark addressed the “Status of 2.5/3D and other high density packaging technologies”.

2.5D / Silicon Interposer is an effective fine-pitch solution to provide >10,000 die-to-die connection. Currently used for:

– ASIC/FPGA die partition

– GPU/CPU/ASIC + memory

– For L/S <2μm and vias <5μm, Si interposer is the only available approach

  • Several notable production developments with 2.5 and 3D technology in 2015

– All major DRAM players with production capability of TSV memory stacks; but focus remains on “near memory” requiring extremely high bandwidth

– Si Interposer adoption by AMD for “gaming enthusiast” GPU

– Continued work with TSV for Image and other sensors for backside access

  • Increased adoption of 2.5 and 3D TSV dependant on cost and alternatives

– Si Interposer most relevant to server/telecom CPU and ASIC products

– TSV for portable processors still under review, but LPDDR5 is more likely

  • Companies such as Sony, Toshiba, Aptina, ST have been shipping image sensors with TSV for back side access since 2009/2010
  • Sony is first to ship using die stacking “hybrid” approach in 2012/2013; economical only for 8 – 13MP designs


  • Substrate technologies continue to progress

– 10-12μm L/S in HVM for MPU

– 8μm L/S capabilities in process at Kyocera, Ibiden, Shinko and others

  • Sub-5μm on organic is a challenge

– RDL technologies used in FO-WLP or Si Interposer are looking to displace build-up substrates

  • Ibiden and Shinko working on “organic interposer”

– Internal qualification now down to 2μm L/S and vias 10-25μm

– Yield remains a challenge, so Si Interposer remains compelling alternative


  • Expectation is that Apple will proceed with TSMC InFO FO-WLP for A10 in 2016

– Tool orders and capacity seen in supply chain

– Speculation on second location/source being required

  • OSATs see uptick in interest for products outside application processor

– OSATs: JCET/STATS, ASE, SPIL, Amkor, Nanium, PTI, DECA and Inotera

– Possible Customers: Marvell, Qualcomm, Mediatek, Dialog, Renesas, Infineon,

Freescale, Avago, Analog, Spreadtrum, Maxim, HiSilicon

  • Most focus on smaller die/packages: 3×3 to 8x8mm

– “Large die FO-WLP remain too expensive and yield challenged”

– Expect 1 and 2 die packages with hundreds of I/O in 2016 from multiple applications and companies

– Most production of FO-WLP focused on 1-3 layer RDL at 5-15μm L/S.

– 300mm reconfigured wafers remains dominant approach for now

  • Intel and Samsung remain skeptical of FO-WLP

– At this time, neither have plans to install fan out capacity

– Not seen as cost effective means to make a thinner package


Northrup Grumman / DARPA DAHI Program

After DARPA program Manager Dan Green gave an introductory presentation on the DARPA goals for DAHI (Diverse Accessible Heterogeneous Integration) [see IFTLE 206, “COSMOS and DAHI Herald the Era of 3D Heterogeneous Integration” ] Augusto Gutierrez-Aitken detailed DAHI activity in NGAS.

DAHI seeks to create circuits from various CMOS nodes with SiGe, GaN and/or InP.

They have developed a basic foundry infrastructure allowing external design teams to generate multiple technology heterogeneously integrated circuits

  • Developed a process to integrate multiple compound semiconductor technologies to CMOS wafers
  • Demonstrated three-technology integration between IBM 65nm CMOS, NGAS TF4 InP HBT, and NGAS GaN20 HEMT
  • Demonstrated integration of third-party technology

ngas 1

A typical NGAS DAHI flow is shown below.

ngas 2

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 272 2015 3D ASIP Part 1: Pioneer Awards; Sony 3D stacked CIS; Latest on SPIL Acquisition

By Dr. Phil Garrou, Contributing Editor

Beginning coverage on the 2015 3D ASIP (Architectures for Semiconductor Interconnect and packaging) conference sponsored by RI Int which is the final major high density packaging conference of the year.

This years technical Chairs were Prof Mitsumsa Koyanagi from Tohoku Univ. and Rama Alipati from GlobalFoundries.

Professor Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the Conferences first recipients of the “3DIC Pioneer Award”. After more than a decade into the concerted effort to commercialize 2.5 and 3DIC technology it seemed appropriate to look back and document who actually led the way in this technically challenging effort. After significant study, 3D ASIP management were convinced that the research groups in Tohoku University and Fraunhoffer – Munich were not only the first to recognize what 3DIC could do, but also have continued their studies to this day to help commercialize this important leading edge technology.”

Pioneering award 2


Hirayama of Sony detailed their work on 3DIC based CMOS image sensors.

AS shown below, the color pixels require fewer metal interconnect layers and high voltage, lower temperatures during processing and longer anneal times whereas the logic portions of the circuit are quite the opposite needing many more layers of interconnect and low voltage, higher processing temps and shorter anneal times. It therefore makes sense to fabricate these layers separately and stack them.

sony 1

This separation of circuits and functions is shown below.

sony 2

Sony introduced this technology in 2012 and by 2015 had more than 2/3 of their shipped CIS using this method of fabrication.

sony 3 CSI shipments

In the future, Sony sees introduction of processors and memory to this stack.

sony 4

SPIL Acquisition

Digitimes estimates that more than $893MM worth of SPIL orders are moving to other OSAT companies due to the potential acquisition by ASE [link].

As we have discussed previously [see IFTLE 252 ‘ASE Makes Bid for Siliconware Shares…” ], ASE has previously acquired a 25% stake in SPIL through an unsolicited tender offer, and has launched another tender offer to buy more shares of SPIL which will bring its total ownership interest in the company to almost 50%. ASE has also disclosed its goal is to acquire the rest of SPIL shares, i.e a complete takeover as IFTLE initially projected. .

SPIL now reports that fabless “..chip vendors such as Qualcomm, Broadcom and MediaTek all try to diversify their suppliers to reduce supply risks”. Thus the other IC assembly and test services companies will benefit from ASE’s potential takeover of SPIL. SPIL points to Amkor, China-based Jiangsu Changjiang Electronics Technology (JCET) and Taiwan’s Powertech Technology (PTI) as the beneficiaries.

Consolidation of Notebook computer vendors.

Digitimes also reports that Japan-based PC vendors Sony, Toshiba and Fujitsu are reportedly finalizing talks to merge their notebook businesses into one company [link]. Post merger Sony, Fujitsu and Toshiba would account for 30% of Japan’s notebook market, compared to 29% held by the NEC/Lenovo joint venture.

For all the latest in 3DIC and other high advanced packaging stay linked to IFTLE…

IFTLE 271 IMAPS 2015 Part 4: Scallop-less Etching; Gold Sealing; PI vs PBO; TLPS

By Dr. Phil Garrou, Contributing Editor

Finishing our look at IMAPS 2015…

ULVAC – TSV etching

ULVAC has developed an etch tool capable of both Bosch etching and their “direct etch” process. Direct etch uses a mix of SF6 and O2 and can result in either a sloped or straight sidewall as shown below. They claim that the direct etch results in significantly shorted PVD time and that the taper vias can result in 80% less electro dep time when filling the vias.


Tanaka Kikinzoku – Gold sealing technology

Tanaka Kikinzoku shared their results on hermetic low temp sealing for MEMS and WLP. They developed a wafer level hermetic sealing process using a rim structure covered with sub micron gold particle paste by stencil printing as shown below. The maximum leak rate was found to be 10-14 Pa·m3/s (He)



Asahi Kasei Electronic Materials

Asahi Kasssei (AKEM) shared their studies on the thermal cycle testing of organic passivations for WLSCP…well really they didn’t share them and I have a few comments about that. Through the years I have complained about reports that fail to fully identify exactly what they are examining. Many of us know them as A,B,C,D papers ….you know “A was much better than B and somewhat better than C and D.” This complaint is not pointed only AKEM, but rather at the many companies and institutes who publish such papers.

Granted such papers can lead us in the right direction if they are commenting that certain properties lead to better results, but they can never be reproduced since no one else knows what it was that was examined.

AKEM introduced their studies by indicating that previous studies had found that PBO failed thermal cycling tests (TCT) earlier than PIs and they wished to know why. The problem is that there are many different types of PIs and PBOs. The examples you choose to compare will totally control the results that you get. The only hints we get is that their PI is a low cure version (“imidization of our specific PI is finished at 200C”) Would it have hurt to give us an experimental or commercial designation ? since AKEM has not chosen to share the structure of this material with us. Even worse is the identification of the PBO. The comment is made that “..the cure temp of the typical photo PBO is over 300 °C …” It is not clear that this is the kind of example that they used and certainly not clear why they used a high temp cure PBO to compare to a low temp cure PI. Those of us in the field know that there are many low temp cure PBOs to choose from.

As an example their examination of strain change vs time (fig 11) they state that “strain is effected by the polymer difference. Equivalent strain in the case of PBO is larger than PI because the modulus of PBO is lower than PI.” Would it not be better to test two known PIs and two known PBOs of differing modulus to make this case? Since I do not know the identity of the two materials that they chose to compare, I cannot draw a clean conclusion about any of their results. I think you see the point.

ORMET – Transient Liquid Phase Sintering (TLPS)

Ormet has been around our industry since the late 1990’s optimizing their TLPS products. ORMET has recently been acquired by Merk. They view their materials as solder replacements for either hierarchical soldering (consecutive joints are soldered at sequentially lower temps) applications where solder remelt is a problem such as MEMS lid attach, SIP and PoP.   Also for high operating temp market segments such as power electronics. Basically the TLPS pastes consist of a high mp metal (copper), a low melting point alloy ( SnBi) and a flus-polymer phase. As the temp is raised the alloy begins to melt and reacts with the high mp metal to form high mp alloys or intermetallics until there is no longer a molten phase at that temp. Pastes are formulate specific to the application.

Ormet 1

They have worked with Kemet to develop a line of pastes for MLCC attach (multi layer capacitors) for high temp applications. Such materials have passed high temp storage (175 C for 2000 hrs); thermal cycling (-40 to +175 for 2000 cycles) and temp humidity bias (50V, 85C/85%RH 2000 hrs) without any failures. Brittle Cu/Sn intermetallic phases are found to initiate some cracks but appear to terminate on the Cu particles.

For all he latest on 3DIC and other advanced packaging stay linked to IFTLE…

IFTLE 270 IMAPS 2015 Part 3: High Density PCB Technologies; Unimicron, Princo

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Conference.


Unimicron discussed their continued development of < 5/5 L/S for polymeric interposer applications.

While silicon can meet fine line (< 5/5 L/S) requirements easily by wafer level processing, silicon processing cost is a barrier to many applications.

There are two types of processes available to meet fine line requirements on organic substrates, traditional semi-additive processing (SAP) or laser embedded technology. They are shown in xsect below. Unimicron reports that current status for SAP is 8/8.

unimicron 1

UV YAG lasers allow for maskless ablation processes by ablating trenches and blind vias simultaneously, but the throughput becomes slow as the features get larger. Throughput of eximer lasers is independent of pattern features since they are defined by the mask. The aspect ratio (h/w) for eximer laser was 1.2 for 3/3 in build-up film with fine filler particles and for 5/5. In general, the finer the filler particle size, the deeper the trench. Since they found that eximer laser ablation was much slower than lithography, the next developments will be with photo build up dielectric to replace the laser ablation. IFTLE should note that this is how it was done during the MCM era in the mid 1990’s, like the IBM SLC technology.

Princo – System on film

In yet another chips last packaging solution, Princo described their system on film technology. Following the figure below they 200mm glass wafer that is first surface treated with a PI and then a silane release coating then another PI layer. Steps 4 to 7 are a lift of copper metallization sequence (6/4um L/S ; 11um thick). Next comes a dielectric layer ad then laser formed vias. These steps are repeated for further layers (up to 8 so far). In step 14, the structure is released from the carrier. This RDL film wafer is then flipped over and the pads are opened through the PI layer and ENIG coated. Die are flip chip mounted, underfilled, overmolded and balls attached and balls placed.

They describe two modules. Module #1 consists of a µprocessor, LPDDR SDRAM / NAND flash combo memory and power management IC on a 6 layer 20 x 17mm module. The second module consists of a µprocessor and a bluetooth 4 dual mode chip packaged in a 4 layer 9.5 x 7.3mm thin film package.


For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 269 IMAPS 2015 Part 2 High Density Packaging ASE STATS Nanium

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Conference.


Advanced packaging has increased in complexity over the years, transitioning from single to multi die packaging there are several platforms now available as summarized by Beica of Yole in the following figure. When choosing a package solution, typically the most mature and established will be considered first.

yole beica 1

When looking at flip chip ~ 37% of the cost is attributed to the substrate. The substrate also increases the thickness of the package.

yole beica 2

Fan out packaging offers increased I/O but also a thinner package since the substrate is not required. Initially limited to eWLB licensees from Infineon (Nanium and STATSChipPAC) the market is expected to explode in the next few years as ASE, SPIL, Amkor TSMC and DECA bring fan out capacity online.

Yole’s Ivankovic compared expectations for glass/silicon interposers vs polymeric substrates. Glass interposer technology is still immature. Polymeric sub 10um L/S substrates are promising but need cost reduction and further L/S reductions. The sweet spot for silicon interposers appears to be up to ~ 3/3.

IFTLE feels that silicon interposers with coarser L/S can surely be manufactured but will not compete on a cost basis. A substrate technology gap exists between 10 and 1um. This will be where the battle for business will be fought.

yole ivanovis 1


Chen of ASE escribed their new Fan out Chip Last Package (FOCLP) which they see as a low cost alternative to eWLB FOWLP solutions. Copper pillar bumped die are mass reflowed onto a low cot coreless substrate, followed by overmolding, which also serves to underfill the die. The Cu pillars allow die connection at 50um or below, negating requirement for RDL n the die. The Cu pillars are bonded to one side of the copper trace (down to 15um L/S) and solder balls are directly bonded to the other side. This makes the “substrate” be effectively as thick as the copper in the traces and allows the final package to be as thin as 400um. Implementation with multiple die, inclusion of passives and 3D structures can all be implemented.

ASE foclp1

STATSChipPAC – High Density eWLB

Currently eWLB devise are used in baseband processors, RF transceivers, power management ICs, NAND memory controllers, on 2 node and ramping on 20nm. In a number of cases STATS reports a 20-40% reduction in package size and a 50% volume reduction due to its slim form factor.

STATS presented their work on with Qualcomm defining eWLB technology with high density ( 2/2 L/S ) and multilayer RDL. Their test structure contained 3 layers of RDL with 2/2, 5/5 and 10/10um L/S.


These structures were built and passed std JEDEC reliability testing.

Nanium – Advances in eWLB

NAnium described new developments in eWLB technology. Kroehnert indicates that the first eWLB based products have been qualified for wafer level SiP and WLPoP with embedded multi die, discrete passives, already packaged components sensors and optical elements.


Nanium eWLB Placement before Overmolding

As thin 300mm reconstituted wafers are not stable enough to be handled in traditional equipment, temporary bonding of recon wafers was developed. They found significant impact from bot the temp bond adhesive and the carrier composition.

The majority of work being done is to enable higher density integration:

– finer L/S

– multilayer RDL routing

– multi die placement with smaller inter chip distances

For all the latest in 3DIC ab=n other advanced packaging stay linked to IFTLE…