Author Archives: sdavis

IFTLE 200 Semicon West Suss Workshop: Laser Debonding and KLA Tencor platform for WLP inspection

By Dr. Phil Garrou, Contributing Editor

The 5th annual Suss Technology Forum was recently held at SEMICON West focused on trends in 3DIC and WLP.

Stephan Luetter compared the various temp bonding technologies and their current focus on excimer laser assisted release.   The EDL-300 is their eximer laser debond module which rasters the wafer with a 12x 4mm laser beam. Carrier is lifted of with a vacuum gripper with close to zero mechanical lift-off force. A requirement for laser assisted debonding, is that it uses a glass carrier wafer to allow transmission of the laser light. Suss has concluded that the new materials and simpler process flows allow cost of equipment reduction in the range of 1.5-3X.

Suss temp 1


The Suss open platform program supports 10 materials suppliers and 4 laser assisted RT debonding processes (including 3M, Brewer, Dow and HD Micro).

suss temp 2


Kim Arnold of Brewer introduced their 3rd generation temporary bonding solution BrewerBond which makes use of a laser assisted room temperature debond process.  Brewer who has been supporting the 3DIC infrastructure for a decade has introduced several product families to meet their customer needs. Each generation has increased throughput and thermal stability better allowing backside processing at higher temperatures.

brewer 1


The BrewerBond process makes use of a light sensitive layer which is decomposed during debonding with a 308nm excimer laser. Arnold indicated that development of a gen 4 product with higher throughput and higher thermal stability is underway.

Mark Oliver of Dow Chemical discussed their laser bond release process. Laser debonding at 308nm is shown below. The adhesive ends up on the device wafer side and is removed with a simple tape peel.

dow 1


Dow also proposed the use of temp bonding to deal with warping in technologies such as fan out WLP.

dow 2


Sood of KLA Tencor announced their CIRCL (Concurrent Inspection and Review Cluster)  platform to address inspection requirements for advanced WLP.

KLA Tencor 1


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 199 Omnivision Roadmaps 3D stacking for CMOS Image Sensors; IC Insights Details Trends Shaping the IC Industry

By Dr. Phil Garrou, Contributing Editor


Since Toshiba started using backside TSV in 2008 we have been anticipating  stacking of separate functions in true 3DIC fashion. Last summer, Sony announced such a structure.  [link 1]

Recently, at the  image sensors conference in London, Dr. Howard Rhodes, CTO of Omnivision, gave an keynote entitled “The Future of CMOS Imaging” where he expounded on the advantages of stacking and the separation of the imaging function from the logic function.

fig 1



Of special interest are Rhodes comments on “stacked CIS” which he calls “replacing the BSI Si substrate with logic.” Their roadmap shows Omnivision moving from wafer bonding with simple oxide bonding to “hybrid bond stacking with simultaneous bonding of oxide and Cu contacts to 3 wafer stacking where sensors, ISP and memory are fabricated separately and stacked.

fig 2


Longtime readers of IFTLE will recognize that Gen 1 “Oxide-oxide” bonding is the technology Sony licensed from Ziptronix in 2011 [link].

“Hybrid bonding” is the term commonly used to describe the patented Ziptronix DBI process where oxide and copper (or other metal) bonding occurs simultaneously [link], so one should expect to see more Ziptronix licensing in the future.

IFTLE would guess that there will be further licensing in Ziptronix future.

IC Insights

At the recent SST ConFab in Las Vegas Bill McClean shared his annual report on  “Major trends shaping the future IC Industry.” IC insights reports that recent growth in the IC industry has been mainly in memory.

fig 3


For the first time in 2013, communication surpassed computers in terms of market share.

Fabless sales are now 29% of total IC sales with the US is holding its ~70% market share of fabless market sales which it has had since 2010.

fig 4


The bulk of capex spending is being done by the major players, i.e. the ones who appear set to move forward to lower nodes (1-7 in the chart below).

fig 5


Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.

fig 6


A look at capital spending by region shows Japan and Europe falling for behind with a combined sub 10%.

fig 7


r all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 198 Intel & Micron HMC 3D Stacked memory; GS Nanotech announces 3DIC Plans; STATSChipPAC suitors named

We have all been waiting a long time to see the following headline:

Intel to Commercialize HMC  Stacked Memory – Knights Landing

Last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. [link] It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core. It will support for up to 384 GB of on board DDR4 RAM  and 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth. It will be the first Intel processor to use this new high performance on package memory.

Intel 1

The Micron 3D stacked  memory which we have know as the hybrid memory cube for several years is being called “multichannel memory or MCDRAM. Micron reports that having such memory in the CPU package is expected to deliver 5X the sustained memory bandwidth versus GDDR5 with one-third the energy per bit in half the footprint.

micron 4

Knights Landing is expected to be deployed in various high performance computing solutions such a as the Cray “Cori” at  National Energy Research Scientific Computing (NERSC) Center.

Long time IFTLE readers recall that Intel was involved from the beginning with the concept of HMC [ see IFTLE 74, “The Memory Cube Consortium” ] and in fact shared a glimpse of the memory cube technology at their developers forum in June of 2011.[link]

fig 5 IDF 2011

Recall Micron contracted IBM to manufacture the logic interface layer [see  IFTLE 95, “3DIC – Time Flies When You’re Having Fun; Further Details on the Micron HMC….”]

So it was interesting to see the logic layer on display recently in the IBM booth at ECTC. I’m pretty sure this is it (before the memory layers are attached).

IBM logic layer 2

While the excitement level around this announcement will be high, we should all understand that as described this is a high end HPC application, not the high volume driver that the 3DIC world has been awaiting. The question for intel is will Intel use this as a platform to compete with nVidia and AMD/ATI on graphics, or will this be just a niche HPC product?

We should also note that although Intel has numerous patents in the area, there is no current indication that this will be a 2.5D solution. Intel has thus far only said “it will be high bandwidth.”

GS Nanotech

Anyone else surprised by the recent announcement that GS Nanotech (Kaliningrad, Russia) “plans to launch mass assembly of 3D stacked TSV microcircuits in the next few years”? I must admit I had never heard of them. A quick look at their web page indicates that they manufacture chips for General satellite set-top-boxes and have ST Micro, Nanium, Toshiba and Winbond listed as customers.

FYI – we are in the process of inviting them to speak at the RTI ASIP conference in December to see exactly what they have and what their plans are.

Updating STATSChipPAC

From our friends at Digitimes: “STATS ChipPAC, the world’s fourth-largest IC backend service company, has put itself up for sale with ASE, Changjiang Electronics Technology, Samsung and Huatian Technology (Xian) likely to compete for the sale… STATS ChipPAC has been holding talks with potential buyers since mid-May, with ASE and Changjiang being the first two contenders… Changjiang aims to enhance its manufacturing technology and patent portfolio, and to ramp up total capacity by acquiring STATS ChipPAC, noted the sources… ASE’s bid for STATS ChipPac is more likely to prevent other potential competitors from taking over STATS ChipPAC to build up capacity against ASE…” Samsung, Huatian, Foxconn, UTAC and GlobalFoundries have also been rumored to be potential acquirers. [link]

For all the latest on 3DIC and other advanced packaging solutions, stay linked to IFTLE…

IFTLE 197 IBM / GF; 3D Integration Handbook Volume 3; 2014 iTherm

IBM/GF …the Saga Continues

Although both IBM and GF are refusing to address “rumors and speculation,” the rumors and speculation persist that the sale of IBMs semiconductor business to GlobalFoundries is imminent. The latest to comment on the expected deal is Businessweek / Bloomberg [link]

Most experts feel that GlobalFoundries is primarily interested in acquiring IBM’s engineers and intellectual property rather than the manufacturing facilities (200mm facility in Burlington VT and 300mm line in East Fishkill NY) since GF has its own state of the at capacity. GF would  act as a supplier for IBM’s semiconductor needs.

Reading the Vermont Free Press articles on the subject, it is clear that IBM employees expect GF to mothball the facility. For those of you wondering why there is a semiconductor facility in VT at all I offer you the following interesting comment “IBM opened its plant in Essex Junction in 1957, largely because the late Thomas Watson Jr., former IBM chairman and CEO, liked to ski.”

3D Integration Handbook

bookMitsumasa Koyanagi, Peter Ramm and I have finished our work on Volume 3 of the 3D Integration Handbook and it is now available for sale at Wiley VCH, Amazon or you favorite textbook retailer.

Vol 3 focuses on 3D Process technology, updating the original two volumes in 2008 with all new chapters on all the relevant process steps. We have gathered many of the worlds experts to give you their insights on 2.5 / 3DIC processing and an especially strong chapter on metrology from the staff at Sematech. The bond/debond section includes chapters by Brewer, EVG, Suss, TOK , 3M and RTI. Most areas are covered by at least two different authors to give the reader a more complete perspective of what is possible. Of special interest should be the chapters “Bonding and Assembly at TSMC” by Doug Yu, “Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices” and “Implications of Stress/Strain and Metal Contamination on Thinned Die” by Kangwook Lee.

Paul Franzon of NC State, Eric Jan Marinissen and Muhannad Bakir will be editing Volume 4 which will focus on Design, Test and Thermal. We hope these volumes prove to be of value to the community.

2014 iTherm

iTherm is the Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. The 2014 iTherm was held concurrent with the ECTC in Orlando, FL. This years General Chair was Mehdi Basheghi of Stanford and program chair was Madhusudan of Google. Attendance this year was up 50% to ~ 400.


Kumari and co-workers at HP addressed “Air Cooling Limits of 3D Stacked Logic Processor and Memory Dies.” Their goal was to determine how many memory die can be integrated into a package with logic before exceeding the temp limitations of the memory die. Modeling was done for 10nm technology with 24 cores as shown below. Core power is varied from 1.5 to 3 W (red cores). Sacked memory are 0.5W DRAM.

HP 1

Thermal results are shown below.

HP 2


Oprins and Beyne discussed the “Thermal Modeling of the Impact of 3D Interposer Materials and Thickness on Thermal Performance and Die-to-die Thermal Coupling.” For the test vehicle shown, they observe reducing the thermal conductivity from Si to glass results in an increase in the logic temperature and consequently a lower maximum logic power. The memory temperature at the other hand decreases for decreasing values of the conductivity since the in plane thermal coupling is reduced. This results in an increase of the allowable logic temperature. If the memory heating is included, an increase of the memory temperature can be observed for very low conductivity values.


Most applications for interposers combine high power components (logic) and temperature sensitive components (memory). Since the components are thermally coupled in the package, the logic power will be limited by either the temperature limit of the logic or memory, whichever is reached first. This means there is a trade-off between the logic self-heating and the thermal coupling which are impacted differently by the interposer material and thickness choice. It is shown that the Si interposer has a better thermal performance than the glass interposer in case only the logic temperature limit is taken into account and that the Si interposer package thermally outperforms the single chip package, the package-on-package configuration (PoP) and the 3D stacked configuration. In case the memory temperature limit and self-heating are taken into account as well, the glass interposer package has a better thermal performance for cases where the memory temperature limit memory is sufficiently lower than logic temperature limit.

For all the latest in 3DIC integration and other advanced packaging, stay linked to IFTLE…

IFTLE 196 2014 Symp on Polymers: Fraunhoffer IZM; ASE, Hitachi Chem

The 16th biennial Symposium on Polymers was held this May in Wilmington DE. Keynote speakers included Steve Bezuk, Qualcomm, James Lee, Strategic Foresight Investments, John Hunt, ASE and Mark Poliks SUNY Binghamton.

Frauhhoffer IZM

Michael Toepper of Fraunhoffer IZM continued a theme we saw from Ted Tessier at the IMAPS Device meeting in March [see “IFTLE 189, “IMAPS DPC part 3: FCI; GF/Amkor; Corning; Namics”] namely photo processing vs laser ablation for WLP.

In the 1990s, photo materials won out over dry etch materials because of lower COO. The processes are compared below.


The question now is  – Can we do even better with laser processing ? Laser is compared to photo processing below:


High absorption of UV radiation by polymers and poor thermal conductivity of the polymer result in etch depths per pulse in the 100 nm range with little thermal diffusion.  Scanning ablating allows for ablation of areas of 50 x 50mm at a time.

Materials suitable for Excimer ablation include:


Much finer vias can be produced with laser ablation, i.e 5um vias in 5um dielectric. Also since the ablation is done after cure, no polymer shrinkage occurs after the via is formed. A low cost polymeric cover layer is applied to catch debris during processing and is dissolved away after ablation.

With laser ablation non photo polymers which exhibit better thermal, mechanical and electrical characteristics than photo polymers can be used and such materials can use high loadings of nano-fillers which cannot be made photo-imageable.


John Hunt of ASE detailed “Polymer Innovations for Advanced Packaging Applications.”  John pointed out that every component and interface in the package must be carefully engineered. The variety of interfaces are shown below.


Multiple disciplines are necessary to develop materials for advanced packaging as shown below for underfills:


Many polymers are required for a single application for instance for 2.5D interposers:

blurb 2

There is still significant room for improvement as shown below:

blurb 3

Hitachi Chemical / HD Microsystems

Daisaku Matsukawa of Hitachi Chemical described their attempts to produce a low temp curable, positive tone photo PI. For many years PI has been known to have excellent mechanical properties but very high curing temperatures. In the 1990s, curing temperatures of the most popular grades were 350˚C+ .

Crosslinking a copolymer of preimidized PI and a phenolic containing moiety (see below) resulted in low temp cure PIs.

HD 1

While x-linking with aliphatic and aromatic di-epoxides resulted in poor films, they found that heterocyclic epoxides resulted in materials with good PCT resistance and adhesion at low cure temperatures, i.e. 150 – 200˚C. Material properties are shown below:

HD 2

IFTLE notes: while the curing temperature has gone down into todays preferred range of less than 200˚C the mechanical properties, once the main PI benefit, now look a lot like BCB and the Tg of the material now more resembles low Tg epoxy than PI or BCB. It will be interesting to see if such a material gains acceptance in the marketplace.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 195 STATS in Play ?…What Consolidation means to you… Micron and TSMC for 3DIC?

By Dr. Phil Garrou, Contributing Editor

STATS Status?

The hottest rumor at the 2014 ECTC in Orlando was that STATSChipPAC (SCP) was “in play” (about to be acquired). One version of the rumor had at least 3 bids on the company including GlobalFoundries (IFTLE finds it hard to imaging GF could swallow both IBM and SCP at the same time), ASE and “a group of un-named mainland China companies.”  Inquiries to SCP contacts substantiated the rumors although they had no knowledge of the details.

Sure enough the Wall Street Journal on May 16th indicated that SCP was “considering an offer for all its shares.”

When I went straight to the source and asked for a response, SCP sent me a copy of the response they sent to the Singapore stock exchange (the rumors evidently caused the stock shares to jump.

STATS ChipPAC Ltd (the “Company”) refers to the questions from Singapore Exchange

Securities Trading Limited (the “SGX-ST”) dated 15 May 2014, regarding the unusual price and volume movements in the shares of the Company.

 The Company has received a non-binding expression of interest from a third party, with a view to a possible acquisition of all the shares in the Company subject to a number of conditions. The Company regularly conducts strategic reviews of, and considers various proposals in relation to, its business and operations with a view to maximizing shareholder value. The Company is accordingly considering this approach. There is no assurance that this approach will result in any definitive agreement or transaction. Save as set out above, the Company is not aware of any other possible explanation for the trading and the Company confirms its compliance with the listing rules, in particular, Rule 703 of the SGXST Listing Manual.


The Company will make an appropriate announcement in the event that there are any material developments on this matter. Shareholders of the Company and investors are therefore advised to exercise caution when dealing in shares in and other securities of the Company. “


IFTLE has written many blogs detailing how we are in a period of consolidation and how Economics 101 tells us that there is no way to stop it. Let’s take a look at what this really means. I watched this occur in the chemical industry, and I am now watching it again in the electronics industry. For those of you that are business majors, I forgive you if you skip this and go on to something else. For those of you that are “techies” working for IDMs, foundries, material or equipment suppliers, pay attention please because this concerns you.

The 4 stages of a Business Cycle (extracted from GK Deans “The Consolidation Curve,” Harvard Business Rev., 2002.):


Stage 1: In stage 1, the combined market share of the three largest companies is between 10 percent and 30 percent. Companies in stage 1 industries aggressively defend their first-in advantage by building scale, creating a global footprint and establishing barriers to entry, i.e. protecting proprietary technology or ideas. Stage 1 companies focus more on revenue than profit, working to amass market share.

Stage 2: Stage 2 is all about scaling. Major players begin to emerge, buying up competitors.  The top three players in a stage 2 industry will own 15 percent – 45 percent of their market, as the industry consolidates. The companies that reach stage 3 must be among the first players in the industry to capture the most important markets and expand their global reach.

Stage 3: Stage 3 companies focus on expanding core business and continuing to aggressively outgrow the competition. The top three industry players will control between 35 percent and 70 percent of the market with five to 12 major players remaining. This is a period of large-scale consolidation plays. Companies in stage 3 industries focus on profitability and pare weak businesses units. The well-entrenched in this phase will attack underperformers. Recognizing start-up competitors early on allows market leaders to decide whether to crush or acquire them. Stage 3 companies should also identify other major players that will likely survive into the next, and final, stage and avoid all-out assaults on them which could leave both players injured.

Stage 4: In stage 4, the top three companies claim as much as 70 percent to 90 percent of the market. Large companies may form alliances with their peers because growth is now more challenging. Companies in stage 4 must defend their leading positions. They must be alert to the danger of being lulled into complacency by their own dominance.

Stage 4 companies must create growth by spinning off new businesses or buying into aligned fields to broaden their market presence.

Let’s take a look at a few examples to bring this closer to home. First, let’s look at DRAM memory consolidation.  In 1980, there were 41 listed suppliers [1] whereas after the recent acquisition of Elpida by Micron we are left with 3 suppliers having > 90 percent of the market [2].








[1] M Durcan, “Leveraging Capital Efficiency for Global Leadership”, Semi ISS , 2011

[2] C Chan, “DRAM Industry Outlook Rational Competition, not a Cartel”, Semi Taiwan, Sept 2013.

How many foundries do we expect to see moving past 22nm? TSMC, GF, Samsung and maybe. That’s it.

Some front-end IC equipment markets have recently been examined. [3] Each color below represents a different vendor and the dark grey area represents multiple small suppliers. Many of the market segments already have one to three suppliers with combined > 80 percent market share; several segments have 2 suppliers with > 90 percent market share and two segments have 1 supplier with > 75 percent share. All signs of a mature market.

Lentz front end












So, the front end is nearing full consolidation. With 450mm stalled and scaling coming to an end this means fewer and fewer fabs moving forward with the latest equipment. What’s a front-end equipment supplier to do?

“Stage 4 companies must create growth by buying into aligned fields to broaden their market presence”

We have all watched as Applied Materials has made their move into the backend equipment sector and even tried to spread their wings a little further into the PV market (ouch!)

Will anyone be surprised as we see LAM and KLA Tencor attempting to do the same? Since the front end suppliers have the deeper pockets IFTLE has expected for a long time that they will eventually buy out back end suppliers as consolidation continues.

Lastly, let’s look at some breakouts of market share in the back end equipment space. Below I am showing a Yole look at equipment market shares in 2011 with names and percentages removed (sorry but they sell this info). We can see consolidation has already begun there as well. As stated above IFTLE expects many of these players to be bought out by the front end players over the next few years.

back end Yole











So whether we find out next week that SCP has been acquired, or not, my message is the same: CONSOLIDATION is underway and will likely affect you and your current employer.

Micron and TSMC?

Josephine Lien at Digitimes is reporting that “TSMC reportedly to tie up with Micron to develop 3D ICs” According to these reports, TSC will integrate Micron’s hybrid memory cube-based DRAM chips with TSMC’s logic chips “through TSV technology.” Lien continues “A successful development of the chip stack technology between DRAM and logic chips will enable TSMC to extend this technology to integrate mobile application processors and DRAM chips, and therefore will help TSMC further expand its client base.”

During the summer months ahead, IFTLE will be giving you full coverage of:

2014 Symposium on Polymers ; 2014 ECTC; 2014 iTherm; 2014 Confab and Semicon West and more…

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 194 More on IBM / GF ; SEMI Singapore part 3: Nanium, Fujitsu, EVG

By Dr. Phil Garrou, Contributing Editor

The Latest on IBM and GF

Craig Wolf of the  Poughkeepsie Journal reports confirmation from Global Foundries that 150 to 200 IBM’ers will move from IBM’s East Fishkill chip plant to GlobalFoundries’ plant in upstate Saratoga County. GF has confirmed a contract with IBM in which “technical workers” based at the East Fishkill will work for eight months at GF’s Fab8 chip plant. IBM refused comment on the deal.

While one cannot conclude that his confirms the imminent sale of the IBM Semiconductor division to GF (which IFTLE has predicted for several years) , it certainly indicates that things are slow in the IBM plant.

Continuing our look at the recent 2.5/3DIC Forum at SEMI Singapore.


Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology and that eWLB offers an alternative with sufficient capability for many applications in high volume at reasonable cost.

PoP structures such as those shown below are being readied for portable applications where less than 1mm thickness is required.

Nanium 1

Nanium is working with AT&S to develop technology for reconstitution in laminate vs traditional eWLB which forms a wafer out of molding compound.

nanium 2


Fujitsu presented on “Highly reliable chip to chip Cu wiring technologies for 3D/2.5D interconnection.” Their premise is that as interconnect gets finer and finer traces will need full barrier layer protection similar to what is done on chip with dual damascene, especially when the interposer is a high density PCB. This is shown by HAST failures as shown below.

Fujitsu 1

Their proposed failure mechanism is:

- Halide ions and organic acid accumulate around the anode Cu

- Anode Cu dissolves and Cu ions are formed

- Cu ions diffuse and drift into insulating materials

- Cu dendrite growth on cathode surface triggers dielectric breakdown

fujitsu 2

A barrier layer is needed to prevent Cu corrosion. SiN failure is due to cracking due to the CTE mismatch.

fujitsu 3


Thorsten Matthias reviewed EVG solutions for interposer manufacturing.


Of special interest was his review of the work of GaTech and Zeon looking at the insulation of interposer TSVs with polymers instead of oxide. Oxide liner is usually less than 1μm thickness and the cost scales with thickness whereas polymer liners can be much thicker and the cost is independent of thickness. The GaTech simulations show the polymer liners will give superior electrical performance. FEA shows the polymer liners should show a Reduction of thermal induced mechanical stress.

EVG proposes spray coating as the technique to get the TSV insulated with polymer as shown below. EVG wafers were processed on an EVG NanoSpray coater with JSR Micro WPR 5100 positive resist and BCB for polymer insulation.

IFTLE notes that cross sections were shown for 40um dia TSV but not for the more common 10 x 100um TSV.


For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 193 SEMI Singapore Part 2: SPTS and STATSChipPAC

By Dr. Phil Garrou

At the recent 2.5/3DIC Forum at SEMI Singapore Dr. Surya Bhattacharya, Director of Industry Development (TSV) at, A*STAR Institute of Microelectronics chaired the day long session looking at the state of TSV technology. Let’s take a look at some of these presentations.


SPTS updated attendees on their endpoint controlled “via reveal” etch process. As we know, via reveal involves the following process sequence:


The SPTS Rapier module has their “ReViaTM” in-situ end-point detection technology which they claim increases throughput and yield.



The SCP presentation looked at “2.5/3D Integration: Moores Law and Beyond.” One message here is that 2.5/3D is not a cure all. As we have seen SCP present in the past, they conclude (and IFTLE concurs) that the right packaging solution must be chosen based on the requirements of the unique opportunity. We have seen the figure below before, but it is worth showing it again.


For instance, comparing 2.5D to an eWLB solution:


SCP reiterated that they see their position in the infrastructure as mid end and back end of line.


Their work with UMC which was initiated in 2012 has taken structures such as wide IO memory on Aps processors through reliability with positive results.


SCP has demonstrated MEOL (mid end of line) and BEOL process capability for 2.5/3D TSV with hand-off between foundry and OSATs.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 192 Semi Singapore: Review of SEMI 3DIC Standards Activities

By Phil Garrou

IFTLE has said many times that it will be impossible for a complicated technology like 3DIC to ever become commercial without standardization. SEMI has been working on this now for 3+ years . Lets take a look at their recent update from their SEMICON Singapore presentation.

Semi 3DIC standard Activities

Semi updated their 3DIC standards activities in late 2010 with the following structure:

semi 1

So far, they have published the following standards:

SEMI 3D1-0912, Terminology for Through Silicon via Geometrical Metrology

– Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services.

– The purpose of this Document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).

SEMI 3D2-1113, Specification for Glass Carrier Wafers for 3DS-IC

– This Specification describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state;

– Methods of measurements suitable for determining the characteristics in the specifications indicated.

SEMI 3D3-0613, Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames

–Address the methods for shipping thin wafers on tape frames.

SEMI 3D4-0613, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks

– Control of bonded wafer stack (BWS) thickness, total thickness variation (TTV), bow, warp/sori, and flatness metrology, is essential to successful implementation of a wafer bonding process.

– This std provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.

SEMI 3D5-0314, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through- Silicon Vias (TSVs) in 3DS-IC Structures

– This std assists in the selection and use of tools for performing measurements of geometrical parameters of an individual TSV (through-silicon via), or of an array of TSVs.

SEMI 3D6-0913, New Standard: Guide for CMP and Micro-bump Processes for Frontside Through Silicon Via (TSV) Integration

– This std provides a generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump.

SEMI 3D7-0913, New Standard: Guide for Alignment Mark for 3DS-IC Process

– Photo alignment mark configuration is the key to ensure consistent and precise alignment of layers, chips and wafers.

– This std provides an alignment mark strategy for chip to chip, chip to wafer, and wafer to wafer stacking.

NA Task Force Overview

Bonded Wafer Stacks -– Create and/or modify specifications that reflect bonded wafer stacks parameters and the wafer bonding process.

Inspection & Metrology –  Develop standards for metrology and inspection methods to be used for measuring TSV properties, bonded wafer stacks, and dies used in the 3DIC manufacturing process.

Thin Wafer Handling – Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro-pillar Grid array -MPGA) used in 3DIC high-volume manufacturing (HVM).

Taiwan 3DS IC Testing Task Force

• Design for Test (DfT) such as test structures and placement

• Test methodologies such as contact method and test procedures

• Test fixtures such as probe card and probe interfaces

Taiwan 3DIC Middle End Process Task Force

• Develop criteria for micro-bump dimensions, planarization and related. Dimensions can be determined into wafer-to-wafer level (WWL), die-to-wafer level (DWL), and die-to-die level (DDL).

• Develop criteria for TSV CMP process and related. (Via size, via surface roughness, post CMP Cu step height, and post CMP Cu bump planarization uniformity)

• Develop standard for photo alignment mark and overlay mark. Alignment marks for patterning TSVs and stacking devices/wafers would be standardized for recognition.

• Suggest wafer or die thickness variation and warpage before and after MEOL and identify thickness variation, void size, overall void percentage of temporary bonding glue layer, warpage control after temporary bonding and corresponding measure method.

• Develop TSV quality criteria such as thickness uniformity, TSV depth variation, void, pattern density, TSV metal extrusion.

Japan Thin Chip Handling Task Force

The Thin Chip Handling TF aims to develop standards for carriers such as chip trays for reliable handling and shipping of thin chips and dies used in high-volume 3DIC manufacturing.

• Test Method for Measurement of Chip (Die) Strength by Mean of Cantilever Bending was submitted

For more information, please visit the SEMI 3DS-IC Google Site:

More from SEMI Singapore in next weeks IFTLE.

For all the latest in 3DIC and Advanced packaging, stay linked to IFTLE…

IFTLE 191 ITRS Echoes Dylan “The Times They are a-Changin’ ”

By Dr. Phil Garrou

For several years now through PFTLE (in Semiconductor Int) and IFTLE  (in Solid State Technology) I have been mimicking Kareem Abdul Jabbar’s role as the street preacher in Stephen King’s “The Stand.” For those of you who have not seen the movie (or read the novel) he marches through Times Square ringing a big cow bell and wearing a sign reading “The End is Near.”  He is predicting the end of the world as we know it due to a plague released by a secret Government lab. No one believes him, but soon, as they all begin die, we become aware that he was correct.

Homer Simpson mimicking the Jabbar scene in The Stand.

Homer Simpson mimicking the Jabbar scene in The Stand.

I have not been predicting the end of the world, but rather the end of electronics as we know it, i.e relying on CMOS scaling. Similar to my economic prediction that the stock market will “soon” fall, sooner or later I will be right.   Therefore, it was with great anticipation that I perused the 2013 ITRS roadmap that was released a few weeks ago. Would they try to ignore what is happening or would they face the issue head on like the poet of my generation Bob Dylan who in 1964 released “The times they are a-changin”. I am happy to tell you they are facing the challenges head on although the ultimate solutions are, as we might expect, not yet crystal clear.

The 2013 ITRS Roadmap

The ITRS for those of you not familiar with the group  is jointly sponsored by the US, Taiwan, European and Korean SIA and the Japanese JEITA (Japan Electronics and Information Tech Industry Assoc)  so they are certainly “mainstream.” Hundreds of technologists from around the world staff the dozens of committees that every few years update where the semiconductor industry is going.

A quick look at the Exec Summary gives us a good understanding of the theme for this update “The ever changing environment.” They contend that the Semiconductor Industry, born in the 70s, had two main goals: (1) providing cost effective memory devices with pin-out and functionality standardization and (2) application specific integrated circuits (ASICS) that required specific functionalities to realize novel products.

Classical Scaling

In the 80s system specifications were in the hands of the system integrators. Through scaling, semiconductor technologies were introduced every three years by memory devices and were subsequently adopted by makers of logic devices. In the 90s continued scaling allowed logic and memory IC manufacturers introduced new technologies every two years and substantial part of the control of system performance and profits moved into the hands of IC manufacturers. This period of ~25 years can be called the Era of “Classical Scaling.”

Equivalent Scaling

In the late 1990’s we began to see technologies such as strained silicon, high- κ /metal-gate and multigate transistors be used to further improve device performance. This second Era known as the Era of  “Equivalent Scaling” That can be seen in the figure below [ this is not in the ITRS roadmap, IFTLE added it to strengthen the point]

191-fig 2

3D Power Scaling

Because 2D scaling will eventually reach fundamental limits, both logic and memory are now exploring the use of the vertical dimension (3D). Increase in the number of transistors per unit area will eventually be accomplished by stacking multiple layers of transistors. The combination of 3D device architecture and low power device will usher the (Third) Era of Scaling, “3D Power Scaling.”

System integration has shifted from a computational, PC centric approach to a mobile communication approach.

The heterogeneous integration of multiple technologies in a limited space (e.g., GPS, phone, tablet, mobile phones, etc.) is now the main goal of any design from a performance driven and reduced power driven approach. In the past performance was the only goal; today power consumption drives IC design.

The foundation of heterogeneous integration relies on “More Moore” (scaling) devices with “More than Moore” elements that add new non CMOS functionalities that do not typically scale or behave according to “Moore’s Law.”

Unfortunately the sections of the report that are of the most interest to IFTLE namely back-of-the-line “Interconnect” and “Assembly & Packaging”  are evidently not completed (or cleared for publication) yet. So discussion of those sections will have to wait. We have been given a glimpse of the packaging and assembly challenges in the table shown below.

packaging challenges

The full report (all that has been released thus far) can be found here [link]

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…