Continuing our look at the 2014 IMAPS Conference held in San Diego…
Colosimo of K&S examined high productivity Thermo-compression FC bonding. In traditional FC assembly, the chips are tacked down to the substrate and then solder joints are melted and mass reflowed in an oven. Mass reflow (MR) becomes more difficult as the pitch of the solder bumps becomes finer due to control of solder flow and warpage of the package when the die and substrate are heated and cooled together. These issues are exacerbated for thin die and die stacks. Thermo compression (TC) was developed to locally heat the solder without subjecting the entire substrate to the heating and cooling cycle. This requires the bond head heat past the MP of the solder and then cool down to a low enough temp to pick up the next die from the wafer mounted to tape. Current tools today can do this in 7 to 15 seconds (a few hundred units/hr) which is substantially slower than todays standard FC process.
The newly developed K&S TC tool reportedly can process 1000-2000 chips/hr.
Shinko detailed their studies on 3D stacking an SoC die and a memory die in a SiP package. The fig below shows X-sectional image of the 3D Sip. The structure has a bottom die (6mm sq) with TSVs, stacked on an organic substrate and a top die (9mm sq) stacked on the back side TSV of the bottom die. The bottom die has 10um TSV on 40um pitch.
MEOL (mid end of line) processing flow is shown below. The bottom wafer with copper pillar bumps on its front side and blind TSV is attached to a carrier and thinned to expose the TSV and passivated. The carrier is debonded and the die are sawn for assembly.
The figure below shows the die stacking and packaging flow. The bottom die with copper pillar bumps is assembled onto the BGA substrate. Next the microbumps on the top die are bonded to the TSV pads of the bottom die. The finished assembly is encapsulated and solder balls are attached to he BGA package.
BLR (board level reliability) comprising Temp cycling ad drop testing is shown in the following table. Weibull plot of temp cycling shows first failure at 2,344 cycles and 0.1% failure at 1194 cycles.
Samsung Electromechanics examined the fabrication of Fine featured organic interposers. The next gen packaging such as wide IO memory – logic packaging (JEDEC requires min bump pitch of 40um) requires connection on less than 50um pitch. The Samsung EM process flow using photoimageable build up layers reportedly is capable of less than 5/5 L/S with micro-vias on 50um pitch. The layers can be connected with Vias with min 10um dia.
Paul Ho’s group at U Texas has examined the impact of copper grain structure and material properties on via extrusion in 3D interconnects.
The copper vias they examined were 5.5 x 55um in 780um thick Si. In sample A the copper grain size was uniform. In sample B the copper grains were a mixture of large and small grains. The average elastic modulus for A TSV were 117 MPa and for B 93 MPa. TSV extrusion was found to be 117nm for A and 147nm for B. The smaller more uniform grains were found to exhibit higher yield strength and therefore less via extrusion. Stronger Cu/Si interfaces are also shown to achieve less via extrusion.
GaTech Mechanical Eng
Charles Ume of GaTech reported on his studies detailing the effect of bump pitch, package size, Mold compound and substrate thickness on PBGA warpage.
FEA studies reveal that solder bump pitch, package size and mold compound thickness affect he maximum PBGA thickness significantly, but substrate thickness does not.
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