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IFTLE 322 SEMI ISS 2017: A Period of Uncertainty?

By Dr. Phil Garrou, Contributing Editor

SEMI’s annual Industry Strategy Symposium was held at its usual site, Half Moon Bay, CA a few weeks ago.

It may just be me, but it seemed like this year’s overall message was one of an industry searching. IFTLE thinks the end of scaling and the public indications that 450mm does not appear to be moving forward has left the industry wandering a bit. Yes, there is excitement over IoT, but the exact way that this will play out in terms of low cost connectivity solutions and the inherent security dangers are not yet clear. For an industry that for the past few decades has had everything laid out on roadmaps this may be a bit disconcerting, but to IFTLE it is now significantly more exciting because the future is not as clear.

Is the following the semiconductor roadmap for the future?


With that said, here are some of the highlights of 2017 ISS from IFTLE perspective.

Linx Consulting

Corbett of Linx Consulting looked at the state of the wafer fab materials segment. They indicated that the total market for semiconductor materials in 2015 was $18.5B with most of the top players being in the wafer and gas businesses.

linx 1

The top 11 supplies have ~$12B sales. Removing the wafer suppliers leaves the following top 10 suppliers with categories of materials broken out as follows.

linx 2


As IFTLE said many years ago, consolidation in the semiconductor industry would lead to similar consolidation of their suppliers (materials and equipment). Linx presented the following materials merger list.

linx 3

International Business Strategies (IBS)

Our old friends at IBS note that:

– Apple semiconductor value in 2016 will be $9.6B

– Apple is driving advanced features including move to 10 and 7nm

– Smaller features will continue to give lower power and higher performance but now at a cost premium

– Chip scale packaging will enjoy significant growth

– 3D NAND will show high growth

– smartphones will continue to lead demand at least through 2025

– Growth of IoT will accelerate after connectivity to the cloud becomes very low cost and business models are established for monetizing value of data

Specific areas of high growth are shown below:


Western Digital / Sandisk

Chen presented an interesting history of NAND and concluded that this new conversion of 2D NAND to 3D NAND is more complex than past 2D to 2D conversions and will generate a period of limited cost reduction in the industry. In the past, 2D to 2D scaling transitions took 4-5 quarters but now 2 to 3D is expected to take 14 to 16 quarters!

WD 1

GlobalFoundries (GF)

Patton of GlobalFoundries sees 5G as disruptive technology, which will transform today’s communication architecture.

GF 1

Patton also pointed to packaging as the alternative to silicon scaling (readers certainly know that IFTLE agrees).

GF 2

For all the latest in Advanced Microelectronic Packaging, stay linked to IFTLE…

IFTLE 321 IMAPS 3D ASIP Part 4: SPIL Fan-Out Options; BESI Thermo-compression Bonding Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS 3D ASIP Conference from this past December.


Albert Lan discussed Fan-out from the perspective of SPIL.

Lan showed a nice cartoon depiction of the fan out options of die first, die last and face up and face down as shown below.


Of special interest is their fan out SiP with metal lid to partition EMI. The FO-SiP requires excellent control of the compression molding process.


This will allow elimination of substrate and thus thinner packages with better electrical performance as shown below.

Their warpage “adjustment” technique is also of intrest as shown below.



Hugo Pristauz of Besi described some essentials of thermal compression bonding (TCB).

Pristauz contends that TCB is used when confronted with issues of warpage, ultra fine pitch and / or thermal stress. He points out that there are actually 3 types of TCB processes as shown below.

Besi 1


As we have detailed on IFTLE previously [see IFTLE 108 2012 ECTC 2: NCF, WUF, MUF for tight pitch Assembly], NCF appears to be the TCB process of the future.

Current technology is capable of 10um pitch assembly (C2W face up) which means 2um@3s accuracy. Any attempts to move to 1um pitch would require 200nm@3s accuracy.

A significant issue is maintaining positional accuracy and co-planarity while ramping from cold to hot. Thermal compensation needs to be identified by the bonder (automatically) and recalled from memory during bond control.


Thomas Urhman of EVG discussed technologies for high performance and high bandwidth Applications.

The interesting slide below examines use of the various debonding techniques vs applications. The debonding techniques use heat, force and light respectively to induce separation from the carrier support.



Hybrid bonding, as originally developed by Ziptronix, and as being adopted by Sony for image sensor 3D stacking, requires plasma activation of the surface and tight control of the CMP process. Excess Cu dishing can ruin the bonding. Currently processes using 3-5um pad size at 6-10um pitch are available.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 320 3D ASIP: Amkor Multi Die Packaging; Brewer‘s New Temp Bonding Sys

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS 3D ASIP Conference 2016.


Mike Kelly of Amkor updated their status on 2.5 and 3D multi die packaging.

amkor 1

High density solutions on 2.5D interposer technology are focused on data center, networking, HPC and military.

Amkors 2.5D production readiness:

– MEOL wafer thinning and backside processing

– 300mm TSV line in K4 … K5 starting Jan 2017

– SPC control

– automated wafer handling

– yield > 97.5 % (die level)

– Assembly

– production in K4 (85K parts built to date)

Yields > 98%

Comparison of Signal Routing for high density technologies:

SWIFT production readiness:

– internally qualified

– ready for small body high volume production in Q2 2017 in K5

– large body process in development

Routing capabilities are compared below: Slim > 3x SWIFT > 3X FC

amkor 2


Emilie Jolivet of Yole shared information on memory stacks. Their look at memory stack IP concludes that the area has been dominated by Samsung, Hynix, Micron/Elpida as you would expect.

yole 1


We have previously discussed the Subu Iyer CHIPS program at UCLA [ see IFTLE 301 “Are Silicon Circuit Boards in our Future?”]

As described before, the plan here is to “disintegrate” (system partition) into functional blocks. These blocks would become a standardized IP library which would be available later as reusable IP. These chiplets (or dielets – the community has not decided what to call them) would then be recombined on a high density silicon fabric to fabricate the desired module. Iyer has calculated that these small (< 3 x 3mm) chiplets would require ~ 5um L/S to interconnect them. Lot of similarities to the current. In many ways this approach is similar to the CEA Leti chiplet activity and the DARPA CHIPS program which we shall look at soon.


Brewer Science

When you think about temporary bonding you certainly think of Brewer Science who has been developing products for this technology area for over a decade.

brewer 1

Through the years they have developed products for several potential debonding schemes:

brewer 2

Their latest development is a two part system called “thermo+ cure” bonding where a thermoplastic layer (~ 2um) first encapsulates the device features followed by a curable layer (~60um; 150-200 °C). Debonding, occurs at the thermoplastic / cured layer interface as shown below. No part of the structure, after curing, can flow during backside processing.

brewer 3

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 319 Mike Ma to Amkor; 3D ASIP Part 2: Image Sensing – Sony, Tessera, SMIC

By Dr. Phil Garrou, Contributing Editor

Ma to Amkor

Mike MaThis week, I can announce that Dr. Mike Ma, with 23 years in the microelectronics industry, has moved from SPIL to Amkor as Taiwan Country Manager. Mike served as Vice President of Corporate R&D and Spokesperson at SPIL. Mike holds M.S. in Materials Engineering from Northeastern Univ and PhD in Material Science and Engineering from North Carolina State Univ.

It’s great to see someone who has maintained his keen interest and knowledge in technology attain such a lofty position. Many of you might remember Mike during his earlier days at UMC.

We all know that when consolidation occurs like the ASE – SPIL merger (I know legally this is not being called a merger, but you also know IFTLE always calls a spade a spade) savings are achieved by staff reduction, especially at the higher levels – redundancy they call it. In this case IFTLE is confident that my friends at ASE have made a major mistake letting Mike leave. IFTLE message to Amkor – good pick up!

CMOS Imaging at 3D ASIP 

This year’s 3D ASIP put a special emphasis on CMOS image sensing.

It was the fall of 2007 when Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS). [see IFTLE 89 “Advances in CMOS Image Sensing”]

In 2012 Sony announced that it was separating the pixel section (containing the back-illuminated structure pixels) from chips containing the circuit section for signal processing, and oxide bonding the layers and then connecting them with TSV. [see IFTLE 172 “Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013”]

Seperation of pixels from circuits using oxide bonding and TSV

Seperation of pixels from circuits using oxide bonding and TSV

Earlier this year [see IFTLE 303 “Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7”] a Chipworks teardown of the Samsung Galaxy S7 revealed the first use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide –oxide bonding with subsequent TSVs connecting through the oxide interface (In most circles this is referred to as “HYBRID BONDING” and does not require TSV.

sony 4

So it seems only fitting that this years 3D ASIP image sensing plenary presentation was by Tetsuo Nomoto, Sr General Mgr of Sony’s mobile imaging systems business. Sony sees several key applications for CMOS image sensor technology:

sony 2

Nomoto indicates that the next generation will include stacked DRAM chips to achieve “ 5X faster scan out and storage data, improve distortion and reduce 1/F bandwidth” and then incorporating a DSP into the stack to 3 Layered modules with customized staked DRAM will be shown at the next IEEE ISSCC.

sony 3

The audience really perked up when Nomoto indicated that Sony believes such technologies will be instrumental to furthering robotics and robotic manufacturing.

sony 5

During the Tessera presentation by Paul Enquist, they described the new “hybrid bonding process as follows:

Tessera 1

Since Sony is currently in production with 6um pitch and Tessera is currently capable of 1.6um pitch in demonstration vehicles, they feel they are close to pixel level interconnect technology.

Tessera 2

Yole reports that back side stacked and back side stacked hybrid technology will take over ~ 60% of the marked by 2021.

Yole 1

Roc Blumenthal described SMICs CMOS image sensor capabilities.


Credit where credit is due

Lastly, that great cross section of the TSMC InFO package that I used in IFTLE 218 (shown below) inadvertently had the source cropped off on insertion into the blog. Full credit should go to Prismark consultants and Bingamton Univ. for this great tear down and cross section. Further details can be found in Prismark’s Semiconductor and Packaging Report Q3 2016.


For all the latest on Advanced Packaging, stay linked to IFTLE…


IFTLE 318 2016 IMAPS 3D ASIP: The Expanding World of Fan-Out Packaging

By Dr. Phil Garrou, Contributing Editor

The 13th 3D ASIP conference was held this year under the umbrella of IMAPS. This year’s meeting was chaired by Alan Huffman (Micross), Mark Scannell (CEA Leti) and Mitsumasa Koyanagi (Tohoku Univ) . I remained on board to help with the program organization and to transition the conference to IMAPS.

(L to R) Scannell, Koyonagi, Garrou, Huffman

(L to R) Scannell, Koyonagi, Garrou, Huffman

We’ll first take a look at the “Advances in Fan-out Packaging” course by Beth Keser of Qualcomm (see recent changes below) and next week begin with plenary lectures provided by Tetsuo Nomoto of Sony, Jean Michailos of ST Micro, Bill Chen of ASE and Subu Iyer of UCLA and then other key presentations.

(L to R) Keser, Nomoto, Michailos, Chen and Iyer

(L to R) Keser, Nomoto, Michailos, Chen and Iyer

Advances in Fan-out Packaging

Who better to teach the fan-out packaging course than the co-inventor of RCP while at Freescale. 20 years ago Beth was coating BCB wafers for Ted Tessier at Motorola, today she is the go to person for fan out packaging in the world. For those keeping track of such things, reports are that Beth has just become Director of Packaging at iCDG at Intel in Munich. This is the mobile business they bought from Infineon a few years ago that designs devices for mobile phones. You’ll remember them as the inventors of eWLB fan out packaging!

I won’t give away too much of her course since many of you have not yet seen the live presentation, which I recommend you all do to gain a complete understanding of what this technology is all about.

Lets start by offering up the IFTLE comment that I have used many times “ALL PACKAGES ARE FAN OUT EXCEPT FAN IN WLP” meaning lead frame packages, BGAs ect are all fan out.

By now we are all used to the FO-WLP process flow developed for the Infineon eWLB as shown below. With the proliferation of reconstituted, mold compound based FO-WLP, such processes have become known as face down, chips first.

keser 1

Reconstituted Fan-out has really taken off recently as it has been developed for multi-die , i.e SiP applications and PoP (package-on-package) applications. It has also developed capabilities to achieve much higher densities in both face down and face up process flows. For PoP applications Keser point out that it:

– eliminates warpage and co-planarity issues since there is no substrate

– offers PoP height reduction

– eliminates stress on the die from bump interconnect (maybe but there is still stress – see InFO X-sect below)

Second generation products have been coming out in rapid progression but Keser cautions that only the InFO is currently available. – Xilinx / SPIL “SLIT” [IFTLE 215]

– DECA “M series” [IFTLE 124, 175, 267]

– TSMC “InFO” [IFTLE 283, 305, 311]

– Amkor “SWIFT and SLIM” [IFTLE 243, 309]

– ASE [IFTLE 22, 269]

I will not go over all of these, but have given you links back to previous discussions in IFTLE

Of interest continues to be the upcoming ASE merger with SPIL and their announced investment to scale up the DECA FO-WLP technology [IFTLE 292].

I have commented in IFTLE 292 that DECA and InFO appear to be very similar technologies by polishing the surface during pillar expose step to produce a very flat surface for the RDL fabrication. Keser reports that TSMC is in production with 5/5 (L/S). Many of the speakers are showing InFO cross sections taken from analysis of the Apple A10 (TSMC has still not published process flow or cross section) I have included it below for those readers who have not seen it yet. This is a PoP package with memory on the top (side by side to thin the package down) and the processor below. Note the overall bow in the structure!

Keser 2

In short, “Fan-out packaging” is certainly expanding its technology capabilities and appears to be capable of taking significant package market share in the future.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 317 IEEE 3DIC Part 2: 3D Processing at Tohoku Univ & Extreme Thinning Options for Vias Last Pkging

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IEEE 3DIC Conference.

Tohoku Univ

Koyanagi and co-workers at Tohoku Univ studied the use of Ti as a 3D TSV barrier layer.

Cu was substituted in the early 2000s for Al interconnect wiring which no longer meet the resistivity requirements in the aggressively scaled technology nodes. Cu, which has low electrical resistivity has proved itself as a potential interconnect material, only if necessary barrier layers are in place.

The most serious concern with Cu as interconnect material is the formation of midgap defects in active Si, since it diffuses fast into the Si. Owing to this, the minority carrier life time is reduced several orders even at 200 °C. Moreover during this diffusion process since Cu travels through SiO2, the insulation nature of SiO2 is degraded which can result in premature dielectric breakdown leading to device failure. The well known method to prevent Cu diffusing into SiO2 and then in Si is to sandwich an amorphous metal layer between the Cu and SiO2. Required properties of a good barrier layer are low internal film stress, high thermal stability and low resistivity. Metals with high melting points are known to have larger activation energy for the diffusion to take place.

Although Ta is best suited as a barrier material based on melting point, Ta has more integrated film stress than Ti film, i.e. a 200 nm-thick sputtered Ta film possesses internal stress of 1.4 GPa, whereas the stress in a similar thickness Ti film is 0.8 GPa . Internal stress is the main cause for the delamination of sputtered Ta films. Thus Ti is a better barrier layer based on internal stress.

One way to improve the barrier performance of Ti, is to use a Ti/TiN structure as barrier layer, but TiN has a large resistivity (p~270 µ .

The Tohoku group has found a simple method to improve the barrier ability of Ti layer is to anneal the TSV structures in vacuum at temperatures up to 400 °C. This results in a significant improvement in leakage current characteristics for SiO2 dielectric. TiSix has been identified at the interface between Cu and SiO2 during the sputter deposition.

Another presentation by Tohoku Univ examined the reduction of keep-out-zone in 3DIC by local stress suppression with negative-CTE filler.

The thinning of the IC chips leads to low flexural rigidity of IC chips. In addition, the CTE of the underfill material is larger than that of metal microbumps. In other words, the underfill material shrinks more compared to metal microbumps. IC chips are bent by this shrinkage after the 3D integration process. This CTE mismatch induces local bending stress in thinned Si chips, and in turn effects the MOSFET electrical performance in thinned Si chips.

In general, SiO2 or Al2O3 filler have been introduced into the underfill to reduce the CTE of underfill. High density filler is required to realize a CTE close to the value of the microbumps. However, it is difficult to use the conventional density underfill for 3D IC with fine pitch microbumps due to its high viscosity. What’s required is a low viscosity low CTE underfill.

The Tohoku group suggests a negative CTE material as the filler to suppress the local bending stress. They used manganese nitride-based negative-CTE material as filler. The CTE of this material is -45 ppm/K at the temperature from 65 °C to 100 °C.

Tohoku 1


IMEC & SPTS reported on extreme wafer thinning optimization for via-last applications.

One of the approaches for 3D-SOC W2W bonding is schematically shown below. After oxide bonding, the top wafer can then be thinned and backside via-last TSV contacts can be created to connect electrically to both the top and the bottom wafers.



Two wafer thinning approaches were investigated targeting a 5μm top wafer Si final thickness:

  1. A) A combination of grinding to 25μm followed by an extensive 20μm Si CMP step
  2. B) a combination of grinding to 50μm followed by a short Si CMP step (1μm Si removal) and 44μm Si dry etch process based on a NIR end point detection system performed in an SPTS Rapier XE system.

They conclude that the safest approach combines grinding and a fast Si dry etch which, combined with an in-situ end point detection, enable a very precise and stable etch stop process at the desired

thickness. Moreover, a cost model has shown that this approach is 50% more cost effective as compared to an integration flow that would involve a long and expensive Si CMP step.


For those who havn’t seen it, Amkor has announced that they have completed product qualification of their Silicon Wafer Integrated Fan-Out Technology (SWIFT) WLFO technology for mobile, networking and SiP applications. SWIFT incorporates an “RDL first” process that allows SWIFT wafers to be built and yielded ahead of the assembly process. SWIFT is targeted for production in the second half of 2017 at K5 in Incheon, South Korea.


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 316 YMTC and China’s Desire for 3D NAND Production; Patent Activity In the 3D Memory Space

By Dr. Phil Garrou, Contributing Editor

Happy New Year to ALL from IFTLE !

A little diversion from chip packaging this week. Let’s take a look at China’s YMTC. As we have explained several times on IFTLE, semiconductors have been China’s biggest import for more than a decade. Forbes reports that China buys about half of the world’s chips (> $200B / yr), producing the biggest gap in their trade deficits—even ahead of oil. [link]

If your not in the memory business you probably have never heard of YMTC, but they are about to become the largest NAND memory producer in China.

Yangtze River Storage Technology.

China created the country’s largest chip maker last week, taking a giant step towards Beijing’s plan of becoming less reliant on foreign technology.

Under government direction, Tsinghua Unigroup, China’s largest chip designer has acquired a majority position in XMC, one of China’s leading chip makers. The new holding company is called Yangtze River Storage Technology.

One type of semiconductor China is particularly focused on is 3D NAND for mobile devices and solid-state drives. In 2015 YMTC announced that they were working with Spansion to co-develop 3D NAND technology. [link]

At the September 20th China IC Industry Development Seminar / China IC Manufacturing Annual Conference in Xiamen, Dr. Simon Yang, general manager of YMTC announced that they are “…striving to … enter large-scale memory field based on 3D NAND”. [link]



Yang explained that “…both DRAM and NAND Flash are applied to many products …. However, from the perspective of business operation, whether to start with DRAM or 3D NAND is both a technical issue and an economic one. If we go for DRAM, two extra problems pop up: first, rivals have massive depreciated products; second, demands for DRAM grow relatively slow. Therefore, I think M&A is a better choice for DRAM field. In contrast, flash memory cell technology is evolving from traditional floating gate to closed-loop-gate charge trap, and charge trap is one of the technological strengths of YMTC. 3D NAND is a major breakthrough for YMTC, and what we need to do now is to make 3D charge trap memory. The structure features high performance and low cost, which presents a great advantage.” Yang also indicated that 3D NAND would replace 2D NAND quickly and make profits during the depreciation period.


XMC announced a major NAND memory fab construction in March of 2016 which is expected to begin production in 2018 and reach a 200k wafers per month capacity within a decade. [link]

However it should be noted that Gartner recently published a report analyzing the probability of semiconductor projects in China, and estimated that there’s just a 40% probability of XMC being able to produce 100,000 wafers by 2020

It is felt that YMTC will likely require manufacturing technology from established international players such as Intel, Samsung, SanDisk, SK Hynix and Toshiba. Since those are too expensive to acquire, some feel YMTC remains focused on Micron. YMTC’s Tsinghua Unigroup tried to buy Micron for $23B last year but were blocked by the U.S. government. [link]

Forbes reports rumors that YMTC is still trying to work out a technology licensing and collaboration deal with Micron although this is being denied. [link]

Issues such as allowing China to buy into the US electronics industry are set to be examined by the Semiconductor industry working group of the Council of Advisors on Science and Technology (PCAST) in Washington. [link]

It is expected that Trump will take an even harder stance on such acquisitions to protect the US manufacturing which employs more than 250k workers and is the third-largest source of manufactured exports, according to the U.S. Commerce Department.

Yole Developpement

For those of you that missed it, Yole has recently released an interesting chart on the Issued IP in the 3D stacked memory field. As could be expected Samsung, SK Hynix and Micron/Elpida lead on the IP front.


For all the latest in advanced chip packaging, stay linked to IFTLE…

IFTLE 315: IMEC Leads at IEEE 3DIC 2016

By Dr. Phil Garrou, Contributing Editor

The 7th annual IEEE 3DIC Conference took place in SF a few weeks ago chaired by Paul Franzon of NC State and Bob Patti of Tezzaron. Without question, IMEC led all participants with several key papers at the conference. This week, IFTLE will look at IMEC contributions.

In their paper “Continuity and Reliability Assessment of a scalable 3 x 50μm and 2 x 40μm via-middle TSV Modules” IMEC describes a scalable via-middle module process, featuring an ALD oxide liner, a thermal ALD WN barrier and an electroless NiB platable seed. The module has been downscaled from 3μm to 2μm diameter TSVs. Both the front side to back side TSV continuity as well as the TSV reliability were found to be satisfactory.

When increasing the aspect ratio of the TSV from 10:1 to 17:1 and even 20:1 (for 3 x 50μm and 2 x 40μm respectively), the use of a conventional PVD barrier and seed reaches its conformality limits, as very thick layers need to be deposited in order to assure a continuous film at the bottom of the TSV. For this reason, an advanced and scalable 3 x 50μm TSV metallization scheme was developed and further scaled down to 2 x 40μm diameter/depth TSVs.

IMEC vias middle process flow is shown below.



The oxide liner is deposited in an ALD oxide system . 100% conformality is obtained over the entire TSV depth for 2 x 40μm TSV structures. The 17nm thermal ALD WN barrier is deposited followed by a 100nm electroless NiB seed . Both layers exhibit highly conformal deposition. The TSV copper electrofill is done on an ECD system. Void free filling is obtained for these 2 x 40μm TSVs placed at pitch of 5μm.

The device wafers are temporary bonded to a Si carrier wafer, using Brewer Science Zonebond process. Device wafer thinning is done by mechanical grinding, rough followed by fine grinding, to provide polished surfaces. The mechanical grinding is stopped before the first Cu TSVs are reached, thus leaving a silicon layer between the wafer backside and the tip of the TSVs. A wet process based on HF/HNO3 isotropically etches a few microns of Si, followed by an additional wet TMAH step, selective to the liner oxide, to reveal the TSV bottoms. Cu of the TSV remains encapsulated in the oxide liner. The back side passivation layer is processed on the revealed via bottoms. A low temperature nitride layer is deposited on the wafer backside, and a thick resist layer planarizes the whole surface. Blanket etch back of the layer without photolithography, to expose all TSVs while a thin resist layer remains on the field. The passivation layer together with the oxide liner are etched away in a dry etch process selective to the barrier metal. Finally, the resist is stripped.

Then back side RDL is integrated with a semi-additive process. TiW/Copper barrier and seed deposition, is followed by copper plating.

The liner/barrier integrity is verified by using the controlled I-V method The TSVs are tested in both copper confined (accumulation) and copper-driven (depletion) mode to check the quality of the oxide liner and WN barrier combination. The IVCTRL test indicates excellent barrier/liner reliability of the 2 x 40μm TSV.

In the IMEC paper “Die to wafer 3D stacking for below 10um pitch micro-bumps” reports on the process flow for embedded bumps for below 10um pitch micro-bumps. A process is introduced to fabricate Sn micro-bumps with zero undercut . Revealing bumps and planarization was done by CMP and surface planer. Initial TCB stacking showed well aligned bumps for 5um pitch daisy chains, good mechanical strength of bonded chips and IMC formation between Sn and bottom Cu pads. Calculations show that replacing Cu with Co and Ni will result in less material consumption which is interesting for sub 10um pitch micro-bumps.

In their embedded micro-bumps approach, micro-bumps are embedded in either organic or inorganic dielectric materials. As shown below UBM is processed in a damascene type approach and solder is embedded in a non-cured polymer or WLUF (wafer level underfill). Since a damascene process is used for UBM, spacing between them can be reduced. For 5um pitch, 1um spacing is used. Selection of solder diameter is based on alignment capability of TCB tool.

imec 2

It was found that at temperatures below 120oC, Cu/Sn IMC grows faster than Co/Sn or Ni/Sn IMC while at higher temperatures close to melting temperature of Sn (233oC) Co/Sn and Ni/Sn will grow faster.

The figure below shows plated Sn micro-bumps in 5um pitch and 40um pitch regions before seed etch.

imec 3


For die to wafer stacking an advanced high precision thermocompression bonding tool from Besi with alignment accuracy close to 1um was used. Total profile is around 10s with interface temperature of 250oC and force around 10-15kg. In order to prevent Cu or Co pads from oxidation during bonding, passivation layers such as SAM, NiB and immersion Au were used.

In their paper “Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects” IMEC reports that by taking into account the described alignment tolerances, via last diameters of 1μm enable 2μm pitch TSV interconnection densities.

When looking at dielectric bonding with via last TSV connections. Two wafers are finished with a very smooth, low-topography dielectric layer. The wafers are cleaned and the surfaces are activated by plasma processes. The wafers are subsequently aligned with high precision and brought into contact, resulting in a spontaneous room temperature wafer-to-wafer bonding. After annealing the bond between the wafers becomes permanent. The top wafer can then be thinned and backside via-last TSV contacts can be created to connect electrically to both the top and bottom wafer. The integration scheme is shown below.


The structure has 1μm diameter TSV on a 2 μm pitch. On top of the FEOL stack, 300mm top and bottom wafers have 1 damascene metal layer, called MET1T in the top wafer and MET1B in the landing or bottom wafer. Both wafers are finalized with a planarized SiO2 and a SiCN bonding layer. A SiCN bonding layer is preferred over SiO2 or SiON for its higher bonding strength. The top wafer is aligned to the bottom wafer and bonded at low temperature with high accuracy to the bottom wafer.

The bonding processing is completed by the post-bonding annealing process of 2 hours at 350°C to strengthen the bonded dielectric interface. After aligned bonding of the wafers, the top wafer is thinned to 5μm Si. The thinning process is a combination of wafer grinding, Si CMP and Si dry etch.

The wafer-to-wafer interconnects are realized with 1μm diameter TSVs, defined by through-5μm Si alignment on a high accuracy scanner. The smoothness of the Si surface is critical to enable the alignment. The TSVs are aligned to the corresponding landing pad.

In their final paper IMEC discusses “High-Density and Low-Leakage Novel Embedded 3D MIM capacitor on Si Interposer”. In this work they present a technique to fabricate embedded 3D MIM capacitor on Si interposer showing capacitance densities as high as 96 nF/mm2 and low leakage current of 1.5 pA/nF, while having a breakdown voltage of 10.5 V and > 10 years lifetime (T50%@1V,100 °C = 5.18e16 s).

The process flow is shown below.

imec 5

The list of investigated 3D MIM capacitor is shown in Table below.

imec 6


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 314 IMAPS 2016 part 3: Shinko’s iTHOP; Yole Predicts Sharp Rise in FOWLP Mkt

By Dr. Phil Garrou, Contributing Editor

Finishing our look at the 2016 IMAPS Conference, let’s take a look at presentations by Shinko, Yole, UCLA, Maxim and Asahi Glass.


Kyozuka of Shinko Electric discussed their i-THOP (integrated thin film high density organic package) package for mobile applications. Based on the trend of partitioning large chips into smaller functional units that are the connected on a high density SiP, Shinko sought to develop a high density (2/2 L/S) organic package for use in mobile devices. It involves the integration of thin film layers on a conventional build up PCB as shown below. Design specs and process flow are shown below.

Shinko 1


A discussion of the “embedding resin” which was not identified indicated that materials “B” and “C” “…can be applied for this structure” since no cracks were seen after T/C testing. IFTLE worries about these choices since these materials reportedly exhibit tensile strength between 60 & 100 MPa and elongations of < 2.5%.


Azemar of Yole discussed FOWLP market and technology trends. Yole sees the fan out market splitting in the future into (1) single die applications such as baseband, power management, Rf transceivers etc and a (2) high density market exemplified by the TSMC “InFO” that include larger IO count applications such as processors. This explains the sharp jump in their market forecasts as shown below.

Yole 1


Subu Iyer and his group at UCLA have been taking a look at Cu-Cu thermo- compression bonding for die to substrate interconnection. Temperature, pressure, and surface roughness were examined and optimized process parameters are shown below. Oxidation of the copper surface is shown to hinder the bonding as is surface roughness. Samples with roughness of a few hundred nm could not be bonded.


Annealing at 400 C for 2 hours gave the best bonding results.


Kelkar of Maxim discussed their mold compound free fan out package which they reconstitute on a silicon wafer.

In order to avoid the issues inherent with mold compound based fan out wafers such as warpage, Maxim has developed a process based on silicon wafers. They list one of the packages attributes as “low cost” although I’m sure there are those who would disagree. The process flow is shown below.

Cavities are formed in the silicon wafer by wet etching, die are placed face up in the cavities and the remaining space filled with epoxy. RDL and ball placement follow similar to other FOWLP chips first approaches. It is shown in cross section below. The parts have passed std WLP reliability testing.



Asahi Glass

Nomura and co-workers from Asahi Glass discussed CTE controlled glasses for the minimization of thermal stresses in package formation and assembly. In order to minimize the stress induced on silicon during thermal processing glass substrate are required to be perfectly matched to silicon over the required temp range. Asahi glass claims to have developed such a glass “glass C” as shown below.

Asahi glass 1

Glass C is an aluminoborosilicate composition with controlled chemical composition and thermal history. Silicon wafers bonded to this CTE matched glass show very low warpage over the required temp range.

Answer to IFTLE 313 question:

The “rock” on the right is none other than the island of Manhattan, built on a giant slab of mica schist. The photo was taken from 10k+ feet, at night, by my younger son Christopher who is a Chef in Maine. Old time IMAPS members might remember Christopher attending the IMAPS Ogonquit MCM workshops run by Jack Balde 20+ years ago.

If you swing the picture around so that the pointy end is in the top right corner, Times square is the bright area in the lower left.

An IFTLE technology tidbit is that my neighborhood (Hells kitchen which is just west of Times Square towards the Hudson river) was one of the first neighborhoods in NYC to be electrified (well before I was born). Recall Thomas Edison’s method for generating and transmitting electricity was called direct current (DC). Westinghouse Electric purchased the “polyphase” alternating current (AC) system invented by Nikola Tesla. In an AC system, transformers are used to step up, the voltage that leaves the power plant which enables electricity to travel over long-distance wires. When the electricity reaches its destination, another transformer would then step down, the voltage so that power could be used in homes and factories. There was a major commercial battle to see what technology would win.

My father told me that our neighborhood was initially fitted with the Edison DC system and ran that way through the early 1930’s before it had to be retrofitted with the less costly and more reliable Tesla system. I’m sure at the time everyone thought going with the Edison system was the safe and sensible thing to do, but sometimes it isn’t.
For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 313 IMAPS 2016 Part 2: JCET & Qualcomm Discuss CPI for Die in FOWLP

By Dr. Phil Garrou, Contributing Editor

Post Thanksgiving IFTLE mean an update on Maddie (L) and Hannah (R). The family spent Thanksgiving in NYC where I grew up. The rock behind them is from the meteor exhibit at the Museum of Natural history. Speaking of rocks, can anyone identify the rock on the right?

H & M


Lin of JCET discussed CPI (chip package interaction) for 28nm die in eWLB fan out packages. JCET proposes FOWLP as the 3rd wave of packaging:


They proposed the following current and future eWLB solutions:


They have evaluated electrical CPI and CBI (chip board interaction) for their FOWLP technologies with the following test package and found no problems.

jcet 3



Ray of Qualcomm examined CPI (chip package interactions) in FOWLP.


qualcomm 2

qualcomm 3

IMAPS 3D-ASIP in Burlingame CA DEC 13-15

Hope to see many of you at the annual 3D ASIP conference run this year by IMAPS and held at the Burlingame Marriott. Special attention was paid to bring new viewpoints on high density packaging technology. Some of the Highlight presentations include:

“Image Sensor Technology Evolution for Sensing Era” – Tetsuo Nomoto, Sony Semiconductor Solutions

“Future Landscapes for 3D Integration: From Interposers to 3D High Density” – Jean Michailos, STMicroelectronics

“3D Stacked Image Sensors from a Chinese Perspective” – Roc Blumenthal, SMIC

“Heterogeneous SoCs” – Professor Subramanian Iyer, UCLA

“3D Heterogeneous Integration of CMOS, InP, and GaN Devices Using Hybrid Wafer Bonding” – Andrew Carter, Teledyne

“Essentials of Thermo-Compression Bonding” – Hugo Pristauz, BESI

“ Extreme Wafer Thinning to 5 µm for Low Cost Via Last” – Dave Thomas, SPTS

“Chiplet Partitioning for 3D Many Core Architectures” – Denis Dutoit, CEA-Leti

For full program details and registration see:

For all the latest on advanced packaging, stay linked to IFTLE…