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IFTLE 186 IMAPS Device Pkging Conf: Qualcomm, Prismark

This year’s IMPAS Device Packaging Conference in Ft McDowell, AZ had a series of excellent keynote talks. We’ll first take a look at some of those and then look at several key presentations from the conference.

Qualcomm

Steve Bezuk, Sr. Dir. of Package Engineering for Qualcomm discussed “challenges and directions in mobile device packaging”. Qualcomm expects 7 billion smartphone units to be shipped between 2012 and 2017.

Handset thickness continues to be reduced and is now approaching 6mm. Since the battery and the screen are not shrinking chip packaging and the substrate board must make up the difference. Most of these packages are FC and WLP. Bezuk commented that 5 years ago very few of the packages were WLP but now this category accounts for near 50% of the packages IC.

Molded FC die on thin core or coreless substrates are approaching 750um thick and warpage issues are becoming significant.  Warpage is dependent on :

- core thickness, CTE and modulus

- EMC thickness over die

-  die thickness (ratio of Si/EMC).

Solder balls have become a significant fraction of the total package height.

qualcomm 3

Tighter pitch requirements ( < 140um) have necessitated  a move to copper pillar connections which in turn need thermocompression bonding to overcome warpage/flatness issues in such structures.

Thinner packages require thinner EMC above the die which results in increased warpage and requires EMC with higher mold shrinkage and higher modulus.

qualcomm 4

Bezuk reports that typical HVM substrate properties in 2014 are as follows:

Current 2014 HVM

Patterning Method (µm)

SAP (15/15)

Min FC pitch (µm)

40/80

Core material CTYE (ppm)

3

Decouling solution

Embedded caps

Buildup dielectric

Prepreg, ABF

Having reached a core CTE of 3, reduction in substrate core CTE is no longer an option so the industry is turning to develop materials of increased modulus.

Bezuk proposed that the next move (time undefined) will be from today’s FC PoP structures to 2.5/3D moving first to wide IO DRAM on logic and next to logic-on-logic. Although he added that there was no clear infrastructure answer for where interposers will be coming from.

Prismark

Brandon Prior of Prismark continued on the theme of “Mobile packaging and Interconnect trends.” Their analysis of the Apple 5S smartphone confirms the Qualcomm comments about increased use of WLP as can be seen in the fig below.

prismark 1

Despite all the talk about high density laminate technology approaching < 5um L/S, Prior indicated that the Apple 5S was the first device to use 50um L/S and CSPs on a 0.4mm pitch. It is also interesting that caps continue to shrink. 01005 is 0.4 x 0.2 x 0.13mm which is extremely hard to assemble.

The Apple A7 processor is packages in PoP with the memory package being 1Gb of LPDDR3. The substrate has 27um L/S and 150/170um bump pitch. Memory chips are Ag WB which is a lower force assembly process than Cu WB. While these memory chips are still WB, Prismark stated that they expect performance DDR to go FC at the big 3 memory suppliers and expect 5B units shipped by 2018.

prismark 2

Prior showed the following application processor roadmap for phone/tablet low end vs high end products.

prismark 3

Transition to 0.4mm packages

FBGA and WLP are in high volume production at 0,4 and 0.35mm pitch. Wafer CSP moving to 0.3mm and below. Prismark forecasts > 28% of CSP/WLCSP to be 0.4mm or less by 2018.

prismark 4

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 185 Lecturing the Packaging Community on Nomenclature

The word “lecture” is one of those wonderful English words with multiple meanings. Lecture can mean “a talk or speech given to a group of people to teach them about a particular subject,” but it can also mean “a talk that criticizes someone’s behavior in an angry or serious way.” In IFTLE 185, lecturing means both!

Those of you that are regular followers of IFTLE know that every once-in-awhile, I’ll stop reviewing the latest technology presentations to try to bring home a point. The latter is necessary right now.

Some may call this one of my “rants” but the online dictionary defines a rant as “…an argument fueled by passion and not shaped by facts.”  I can assure you this rant will be shaped by both passion and facts.

What triggered IFTLE 185 was a panel session held at the recent IMAPS Device Packaging Conference in Ft McDowell AZ. A good panel session experts discuss controversial topics but that is not exactly what happened here.  This panel session degraded into a school yard verbal battle (panel members and audience) over what certain terms mean. If you really want to follow the chronology of the discussion you can here [Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel].

It is simply amazing that the assembled group of technical practitioners could not agree on what certain packaging terms mean but….they couldn’t. At first I chose to sit quietly in the audience amused at the miss speak…but then… my good friend Bob Patti, a panel member,  spotted me in the corner of the room and called me out …” Phil what do you think “…it was at that point , no longer able to hold back, that I unleashed my tirade […a long angry speech of scorn and criticism…]

Let me attempt to articulate my position on several of the topics that came up that night …

INTERPOSER – for some reason, be it ignorance, youth or a combination of both, some in the audience continue to believe that the term interposer was invented for 2.5D.

All 1st level packages are interposers, The purpose of an interposer is to spread a connection to a wider pitch. Interposer comes from the Latin, interpōnere, meaning “to put up between.” A BGA substrate is an interposer ! This is clearly shown in the Infineon slide that they have been showing for nearly 20 years.

infineon 2

SYSTEM-in-PACKAGE – there was mass confusion on what this meant and what is included in this definition. Several experts felt that 2.5/3D were NOT included in the definition of SiP. I think some of these disagreements come from the fact that corporations do not divide things up in their business units based on definitions so all things SiP may not be in the same business unit and this influences their thinking.

In the 1990s multiple chip packages, MCMs as they became known, were sets of chips that were connected on high density Si, laminate or ceramic substrates by WB or C4. In the early 2000’s it became vogue to call these system-in-package as industry focus became delivering functions for portable devices in separate modules. Need more history on MCMs try the Multichip Module Technology Handbook [link] which Iwona Turlik and I edited in 1998.

Let’s look at another Infineon slide, below. Whether its side by side, stacked, through hole or embedded, these multiple chip solutions are all versions or categories of SiP.

Infineon 1

2.5D, 2.1D and 5.5D: Please stop the madness!

3D packaging defines the various ways of stacking chips in the z direction whether it be WB them to a common substrate, package-on-package stacking, embedded chip stacking (in laminate or EMC ) or direct connection with TSV.

The term 2.5D is usually credited to ASE’s Ho Ming Tong who ~ 2009 (or even earlier)  declared  that we might need an intermediate step towards 3DIC since the infrastructure and standards were not ready for 3DIC stacking yet.  Tong felt the silicon interposer would get us a major part of the way there, and could be ready sooner than 3DIC technology.  He used the term 2.5D, which immediately caught on with other practitioners. Tong was not trying to create a new nomenclature, he was making a joke that we were not ready for 3D but this silicon interposer with TSV would get us close. He actually got laughs when he called it 2.5D at the RTI ASIP conference fall of 2009.

We are now starting to hear the laminate community use the term 2.1D for high density laminate and some in the silicon interposer community using the term 5.5D  for a 3D memory stack on an interposer. To all this, all I can say is “STOP – Enough-is- enough…it’s no longer funny..”

At one point during Bryan Black’s AMD talk at the conference he said “3D” and the audience interrupted him to ask whether he meant 2.5D. His response was something like “Oh yeah…well they both mean the same thing to me..” meaning we are talking about stacking technology with TSV.  Bryan is correct!

LARGE AREA PROCESSING (LAP)

LAP is being held out as the solution to everything that is not economical these days. FOWLP not low enough cost to break into commodity applications ? …don’t worry we’ll use LAP and the price will come down. Glass interposers not looking like the price will be low enough for mobile products?…don’t worry we can manufacture on LAP lines and the price will come way down.

Certainly our microelectronics educations have taught us that larger usually means cheaper, i.e. chips from 300mm lines ARE cheaper than the same chips from 200mm lines. This is true as long as the equipment and technology is available to give you high yields, i.e. see the current 450mm situation.

My point to the audience was that PCB are made in large panels because they can be…higher density BGA substrates are made in much smaller strips because they have to be!

I actually have hands on experience at what we called LAP back in 1995-1997, as we had a major DARPA contract to try to manufacture MCM substrates  on a sq 400mm format. Check out my chapter “High Density, Large Area Processing (LAP) in the Multichip Module Technology Handbook [link]. By the way our program with MMS and others to manufacture high density MCM substrates made for a great magazine cover (see below)…too bad it didn’t yield!

LAP

Do I think that pursuing high density LAP is a worthy R and D goal ?…certainly, lets just not act like it will be easily accomplished.

Other problems with today’s nomenclature?? Let me know …

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE !

 

IFTLE 184 SEMI Europe 2.5/3DIC Summit : Gartner; GlobalFoundries; TSMC; IMEC

By Garrou

Let’s take a look at some of the key presentations from the SEMI Summit that took place in January in Grenoble.

Gartner – 3D Market Forecast

Stromberg of Gartner gave a market forecast of greater than 1.5M 300mm wafer equiv per month or 2B units / year of 2.5/3D (non MEMS non CIS) by 2018 but then listed several pages worth of technical issues that could affect the forecast.

Gartner

Editorial Comment:

In emerging technologies like 2.5/3D  guaging market timing and size is an art, not a science but I’m not sure what numbers like this are worth if you preface them by saying they could be inmpacted by thermal issues, yield issues, design issues and  competitive treats by PoP and  WB devices. Of course all those things are true, but then what kind of confidence do we have in the nubmbers / timing ?  This is true for al lthe marketing houses not just Gartner.

GlobalFoundries

GF has been detailing their imminent commercialization of 2.5/3D IC for several years. Their current status report is shown below.

GF1

Their response to Interposer TSV formation, front side routing and backside reveal and RDL  issues are shown below. High IO counts require dense interposer frontside routing (i.e. over 1600 wires for a HBM port.

GF2

The GF supply chain for 2.5D productization is shown below:

GF5

TSMC

Miekei Leong , VP TSMC, gave the standard TSMC CoWoS pitch but did offer a definition of their supply chain model where OSATS are now integrated as part of the supply chain.

TSMC 1

Another interesting roadmap showed TSMC demonstrating HBM (high bandwidth memory) on CoWoS by 4Q 2014.

tsmc 2

IMEC – Cost Analysis

Eric Beyne of IMEC presented data on a cost breakdown of their 5 x 50µm TSV full flow 3DIC process (without stacking) showing the TSV middle fabrication process and the thin and backside eveal processing are about equivalent in cost.

IMEC 1

They find that a lot of cost is invested in CMP processing which can be improved by reducing the Cu overburden after TSV fill.

imec 2

This can be compared to the 10 x 100µm TSV costs presented by Ramaswami of Applied Materials shown below:

AMAT 1

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 183 RTI ASIP: Tezzaron; Suss / EVG; Packaging of Apple A8

RTI- Architectures for Semiconductor Integration & Packaging (ASIP) is always held in Burlingame, CA at year’s end. It is focused on commercial 3DIC technology and applications and is always a good indicator for the status of the industry.

In the next few blogs we’ll take a look at some key papers from this years conference.

Tezzaron acquires Ziptronix facility outside RTP NC

As we have discussed previously Tezzaron has purchased the former Sematech fabs in Austin and is running the operation as a subsidiary Novati [ see IFTLE 146, “TSMC Apple…Novati” and IFTLE 166 “IEEE 3DIC part 1;….Novati” ]

Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing [link].

In addition Tezzarons Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly. [link]

Tezzaron, known for its fine featured TSV showed the following process status and an interesting X section of a W TSV connected at M5.

suss 1

Suss and EVG

Suss and EVG examined their processes and equipment available for thin film handling of 2.5 & 3DIC wafers, namely temp bonding and debonding.

They are both working with a number of materials suppliers as shown in the Table below. All of them now supply room temp (RT) debonding solutions

 Temp bonding materials supplier

Suss

EVG

     
Brewer Science

x

x

3M

x

Dow

x

x

Dow Corning

x

x

Thin Materials AG

x

JSR

x

Shin Etsu

x

HD Micro

x

x

 

 

Typical thickness requirements for temporary adhesives are dependent on the interface that is being bonded as shown below.

Suss 2

Both Suss and EVG have recently  introduced eximer laser assisted RT debonding which was first introduced by 3M years ago. [ref]

suss 3

EVG is also touting a laser-initiated debonding process flow.

Brewer has introduced a new UV absorbing release layer which is stable up to 350 ˚C.

suss 4

Amkor, STATS ChipPAC and ASE to package  Apple A8

DIGITIMES is reporting that Amkor  and STATS ChipPAC will each package  40% of the Apple A8 processor, with the remaining 20% by ASE.[link]

They report that Apple’s A8 chip will be a package-on-package (PoP) SoC solution comprising processors and mobile DRAM in a single package.

(TSMC, which is believed to have landed foundry orders for Apple’s next-generation A8 chip, has reportedly also secured wafer bumping orders for the processor as part of its turnkey solution.  TSMC reportedly will start ramping up production using 20nm process technology for Apple’s A8 chip in the second quarter of 2014.

IFTLE 182: IEEE ISS 2014 IBM, Linx, IMEC, IHS, IBS

The recent Semi Industry Strategy Symp (ISS) occurred in Half Moon Bay CA a few weeks ago. In the past this has been a treasure trove of information on how and why the IC industry is making the moves that it does. Let’s take a look at some of the key papers from this conference.

IBM

IBM fellow Jon Casey examined “System Scaling Technologies and Opportunities for Future IT Workloads and Systems” He notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.

Volumetric scaling will be critical to future performance enablement

– Tightly coupled modules and components

– 3D stacking and interposer integration

Casey examined the current state of interposer substrates and showed the following comparison:

IBM 1

 

 

 

 

 

 

 

 

Linx

Linx consultants looked at “Chemicals and Materials in Semiconductor Devices.” IFTLE notes that an examination of materials suppliers shows that while chip production is moving out of Japan due to cost, Japan still has quite a few of the major materials suppliers on its shores.

linx 2

 

 

 

 

 

 

 

 

 

 

Linx lists 3DIC among the major 5 challenges for the IC industry in the future.

Linx 3

 

Like many other prognosticators, Linx points to the cost of 450mm fabs as the main cause of the ever shrinking customer base.

linx 4

IMEC

An Steegen, Sr VP, IMEC examined “Scaling Beyond 10nm.” She offered the following roadmaps for 3D applications and TSV dimensions.

IMEC 5

And the following CoO Analysis for their  3D process flow.

IMEC 6

IHS

IHS examined semiconductors in the electronics value chain.  An unexpected piece of data is that consumers are spending more on hardware (HW) than content i.e.:

IHS 7

IBS

Our friends at Int. Business Strategies (IBS) who in the past have contributed significant data to IFTLE arguments that 3DIC makes economic sense in light of the other scaling options, addressed They indicated that growth in 2013 was mainly due to an increase on memory pricing. They expect Capex decreases in 2014 (small decline)  and 2015 (large decline).

While there is uncertainty in the timing for scaleup of 20 and 16 nodes, by 2020 they expect greater than ½ semi sales will come from 32nm and below.

IBS 8

They also conclude that low power and low cost will dominate the application space for 32nm or less devices.

They continue to predict that cost/gate will no longer be a cost driver.

IBS 10

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

 

 

IFTLE 181 IEEE 3DIC contd: Tohoku Univ; Fujitsu; ASE; RTI

Finishing up on the IEEE 3DIC meeting from Oct 2013 in San Francisco lets look at some of the remaining key papers from the conference.

Tohoku Univ – Lattice Distortions in Thinned Silicon

Professor Koyanagi and coworkers at Tohoku Univ and GINTI [ Global Integration Initiative – see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati” ]

It is accepted that to achieve compact-sized 3DIC each functional wafer should be thinned to 50μm or less. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping and local deformation in the stacked die .  Moreover, the weak mechanical strength of the extremely thin die/wafer itself has a potential concern lead to die breaking for 3DIC integration, because thin LSI chip with high density TSVs is highly fragile and more easily damaged. Hence, it is important to understand the impact of chip’s mechanical strength on device reliabilities decreasing die thickness, especially below 50μm thickness.

Koyonagi and co-workers have found that the Young`s modulus (E) of Si substrate begins to noticeably decrease below 50μm thickness. The Young`s modulus in 30μm thick Si is 30% of the modulus of 50μm thickness. In 30μm Si the lattice structure is highly distorted which induces the Young`s modulus reduction and consequently weakens the mechanical strength.

1

DRAM chip of 200μm thickness were bonded to a Si interposer and thinned down to 50, 40, 30 and 20μm respectively. The measured retention characteristics of DRAM cell on these thicknesses of silicon are degraded dramatically below 50-μm thickness, i.e. the retention time of DRAM cell in 20μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip.

2

They assume that the band-gap energy in the thin chip is affected by the distortion of the lattice structure, hence effect on a minority carrier lifetime, consequently shortening the retention time of DRAM cell.

Fujitsu – Influence of Wafer Thinning on Backside Damage

Fujitsu is known for their ultrathin WOW process [ see  “Development of Multistack Process on  Wafer-on-Wafer (WOW)

Ultra-thinning to 10 microns or less of Si wafer is expected to realize small TSV with low aspect ratio and coupling capacitance. Subsurface damage following wafer thinning from the back of 300 mm wafers using three different types of thinning process was investigated by means of Raman spectroscopy, XTEM, and Positron annihilation analysis, respectively. A coarse grinding generates significant rough subsurface ranged several micron and damage layer including amorphous and plastic-deformed Si along grinding topography. Fine grinding, second step of thinning, reduced those surface roughness and almost removed after thinning at least removal of 50 microns. However, plastic-deformed subsurface layer with a thickness of 100 to 200 nm are still remained which leaves an inside elastic stress layer ranging up to about 10 microns in depth. Chemical-Mechanical Polishing (CMP) process as a final step of thinning enables to remove residual damages such as structural defects and lattice strains after 1-5 microns thick polishing while vacancy-type defects only remain.

3

The authors acknowledge that further investigations are necessary to find “hidden residual defects” and to understand the influence of thinning on memory devices (see Tohoku discussions above).

ASE / Chiao Tung Univ – Low Temp Bonding

ASE and National Chiao Tung Univ  have studied three types of bonding, including Cu-In, Sn/In-Cu, and Cu/Ti-Ti/Cu, for application of 3D interconnects.

Cu-In bonding and Sn/In-Cu bonding can form intermetallic compounds at the bonding temperature lower than 180 C. Cu and In samples were bonded face-to-face with a bonding pressure of 1.91 MPa, followed by a heating temperature of 170 C for 50 min. Sn/In and Cu samples were bonded face-to-face with a bonding pressure of 1.91 MPa, at bonding temperature of 180 C for 50 min.

Cu/Ti samples were bonded face to face with a bonding pressure of 1.91 MPa, at a heating temperature of 180 C for 50 min.  They add that Cu can be protected from oxidation by capping Ti on Cu surface before bonding. This last structure is especially significant if one can really do such bonding at 180 C . Their EDX investigation of the interface shows that “…apparently there is a Cu layer at the bonding interface instead of Ti layers…due to lower activation energy at the surface, Cu tends to diffuse towards the surface  …”  IFTLE feels this combination certainly deserves further study.

All bonded structures have shown excellent electrical performance and reliability characteristics. Based on bond results, these structures can be applied for low temperature bonding in 3D interconnects.

RTI – 10um Pitch Bonding of Hetero Materials

Matt Lueck of RTI Int described their successful demonstration of the use and reliability of Cu/Sn microbumps for the fine pitch interconnection of heterogeneous semiconductor die. InP die have been bonded to Si substrates using a 6.4 mm × 5.12 mm area array of alloyed Cu/Sn microbumps on 10 μm pitch.

A key technological challenge facing the 3D integration of heterogeneous semiconductors is the formation of high density metal interconnects between dissimilar substrates, such as compound semiconductors (CS) and Si. Due to the difference in the coefficients of thermal expansion (CTE), one can expect: 1) some misalignment between microbumps fabricated on the CS substrate and the Si substrate during bonding at an elevated temperature; and 2) bond interconnects will experience shear strain as the bonded die pair is cooled to room temperature and during any subsequent thermal excursions.

4

To estimate the magnitude of the misalignment, they calculated the relative change in distance between corner microbumps in a 10 μm pitch 640 × 512 array on CS die vs. Si die. Operability was determined by electrical testing of long daisy-chains of bumps.

The average channel yield was approximately 97% for both InP-Si and Si-Si die pairs translating into the array operability greater than 99.99%. The reliability of InP-Si and SI-Si die pairs was compared after 500 thermal cycles of -40 – 125 C. No significant change in yield was seen for the homogeneous Si-Si die pairs. The InP-Si die pairs that were underfilled showed a 2.8% decrease in channel yield whereas those not underfilled showed a 13.9% decrease.

5

They conclude that Cu/Sn micro bumps can be successfully and reliably used for integration of InP and Si die.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 180 GaTech Interposer Conference

Continuing our look at the 2013 GaTech Interposer Conference.

CORRECTION to IFTLE 178:

A reader has written in to indicating that the FPGA chip described in the Xilinx/SPIL paper was fabricated by TSMC not UMC .

Corning and Schott Glass

As discussed in IFTLE 170, Windsor Thomas of Corning gave a presentation entitled “The manufacturing readiness of Glass interposers” and Schott glass followed with a presentation entitled “New Ultra-thin Glass for Microelectronics.”

Since the whole LCD infrastructure is based on thin glass we certainly did not need any convincing that large panel, uniform, thin glass is available in roll and/or large panel format. Corning like Asahi Glass and Schott glass has been researching the formation of TSV (or TGV) for several years now and all appear somewhat able to form through vias down to maybe 25um. The real question is how do we than use this feedstock to get low cost glass interposers.

Though we were shown some Cu fill experiments, neither Corning nor Schott  indicated that they would enter the interposer market, did not indicate who such a partner would be and in fact stated that their discussions with the FPD industry( which they most certainly now supply) indicate that there is absolutely no interest in FPD suppliers entering the interposer supply market.

IFTLE concludes that if any of the current glass suppliers want to see glass become a interposer substrate material and more broadly a preferred packaging substrate material, they must resolve who will actually be supplying the final packaging products.

Asahi glass has attempted to fill this void with Triton, their JV with nMode [see IFTLE 141, “100GB Wide IO memory; AGC Glass Interposers; Nvidia talks stacked memory” ] Corning and Schott have not yet indicated what their proposed solutions are.

Shinko

Koizumi-san  of Shinko discussed glass substrate prototyping status. Shinko points out that glass cores can be used to mimic Si like interposers or build-up PCB substrates.

Shinko1

He showed data on a 200um glass core PCB with a 5/0/5 build up process ( 30um polymer/18um thick Cu per layer) . When diced such structures resulted in what they called “Se-wa-re” (loosely translated back split) which was fracture through the glass core layer due to the stresses built up on both sides of the core. Modeling calculations show that the glass internal stress is mainly caused by the total copper layer thickness.

shinko2

Altera

John Xie of Altera examined the use of organic interconnect for stacked die integration.  Altera’s take on Interconnect resolution trends are compared below. The proposal is that organic build up (BU) substrate (dry processed) is rapidly approaching the capabilities of this film BE of line packaging on silicon.

Altera 1

Xie contends that high end substrate suppliers are quickly approaching 2/2 L/S and will allow direct attach to substrate and elimination of the interposer as shown below. This in turn will be a cost reduction driver. He calls this 2.1D or Ultra high density organic  interconnect. They can currently get 92um bump pitch, 8um lines and 80um vias. Their 2 year goal is to obtain 55um bump pitch, 2um lines and 20um vias.

Altera 2

Zeon

Zeon introduced their ultra tine dry films for Interposer RDL applications. Properties of the Zeon “cyclo olefin” polymer film are shown below.

Zeon 1

Ushio

Ushio addressed large area litho tools for 1 – 5µm  L/S. They claim their tool is capable of 2µm L/S in a 70 x 70 sq mm area.

Sohio 1

For all the latest on 3DIC and advanced packaging stay linked to IFTLE…

IFTLE 179 GaTech Interposer Conf: Amkor, GlobalFoundries

Continuing our look at the 2013 GaTech Interposer Conference.

Amkor

Ron Huemoeller of Amkor addressed interposer use, defining the markets and materials options as follows:

Amkor 1

Amkor projects that in the high end silicon will dominate; in the mid-end, silicon will be prominent and organic /glass may play a role; in the low end, organic, or low cost glass or silicon if they exist will play a role.

Silicon Interposers

Product Applications

- Gaming, HDTV, mobile tablets, computing, servers

- High end graphics cards will be the initial focus of HBM memory integration

- mobile space has the potential to follow based on availability of low cost solutions

 

Visible and Anticipated Demand

- continued low volume production of FPGAs and ASICs

- moderate volumes for high end graphics cards; HBM cost/availability driven

- high volumes for mobile; interposer cost driven at less than $0.01 per sq mm.

 

Market Longevity

- expect to have a very long life cycle

- long term continued use through deconstruction of very high end node logic to address system level cost and power related memory integration issues.

Amkor describes the silicon interposer supply chain

-  Current

- TSMC – not supplying to the industry

- UMC and Global Foundries – both have limited capacity and neither desires to be a merchant supplier

- Future

- Yet unannounced merchant supplier

- use of depreciated equipment and excess capacity

- lowers cost vs tier 1 foundries

- supply interposer without desire to bundle chip fab.

Organic Interposer Sources:

- Tier 1 Shinko, SEMCO

- 2/2 (L/S) 10/22 (via/pad); very limited sampling

- Tier 2 Kyocera

- 5/5 (L/S); 18/30 (vias/pads); very limited sampling

- Tier 3 Kinsus, Unimicron

- early development

 

GlobalFoundries

Dave McCann of GlobalFoundries examined market needs for interposers. McCann used the latest Gartner data on SoC costs to point out that development costs for a 10nm design are expected to approach $400MM.

GF1

GF again made the case that “DIS-integration” can actually offset scaling costs, i.e.:

GF2

GF indicates that the yield of high density interposers is high (“..approaching 100%”), even for  full retical sized; 4 metal layer top side, 1 metal layer backside structures.

GF has come up with the following roadmap for silicon, high density laminate and glass.

GF3

Like Amkor, GF has mapped 2.5D requirements by market space and come up with the following.

GF4

Also similar to Amkor GF pointed out that the industry needs a low cost high volume source of  high density interposers. Although showing their capabilities for interposer fabrication, interestingly they did not offer themselves up as the solution.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 178 IMAPS 2013 continued: Xilinx/SPIL; Nanyang/IME; Cannon, AT&S

Finishing up our look at the fall 2013 IMAPS meeting.

Xilinx / SIliconware

We are all aware of the Xilinx / TSMC / Amkor partnership to develop the first comemrcial 2.5D FPGA module. Since that announcment in late 2010 there have been rumors about Xilinx looking for lower cost second sources. Last summer, Siliconware (SPIL) announced the instillation of a dual damascene line for fabrication of high density interposers. [ see IFTLE 158, “2013 ConFab part 2: Amkor and Siliconware”]

At the fall IMAPS meeting Xilinx and SPIL  shared results from their progra to 2.5D 28nm FPGA program.

The high performance FPGA die (it appears manufactured by UMC)  is a 4 slice 28nmchip mounted on a 25 x 31mm 100um thick Si interposer with 45um pitch microbumps. The interposer is assembled onto a 45 x 45mm organic BGA with 180um C4 bumps. The figure below shows the structure in cross section. SPIL is manufacturing the interposer and doing the assembly.

SPIL 1

Nanyang Univ / IME

Copper TSV exert thermo-mechanical stress on silicon due to the CTE miss match. This stress can result in variability of the device mobility and mechanical reliability issues. This can be alleviated by using a oxide liner that has a lower elastic modulus such as some of the “low-k” dielectric materials (black diamond). This would reduce the keep out zone and in addition such materials will lower the parasitic capacitance of the circuit.

These Singapore institutions looked at the use of low-k carbon doped oxides to serve as a more compliant layer TSV insulator layer due to its lower modulus (7.2 GPa vs plasma enhanced TEOS with modulus of 75GPa) . The FEA analysis shown below indicates that the low-K materials “should” lower the stress exerted by the Cu TSV on the silicon. Micro raman spectroscopy on samples verifies that the use of a  low-k liner results in less compressive stress exerted by the Cu TSV on the silicon between the TSV.

IME 1

CV measurements show that the capitance is reduced by 26% ( k of peteos = 3.9 vs low-K of 2.88).

[ IFTLE sees no discussion of mechanical reliability comparisons. Since low-k is known for being very fragile, I wonder whether the TSV stress will fracture the low-k material which would show up as less stress on the silicon?]

Cannon

Cannon, normally associated with front end (FE) lithography addressed “Lithography Process Optimization for 3D and 2.5D Applications.” Cannon has developed the FPA-5510iV and FPA-5510iZ TSA steppers to support high density processes and to support implementation of 2.5 & 3D technology. A comparison of their specs is shown below.

cannon 1

In a typical backside manufacturing process, patterned wafers are bonded face down to a support wafer before being ground and thinned. The bonding and thinning process causes shape distortion in the wafer. Downstream processes require litho that produces patterns that can overlay such distortions with high accuracy. These systems also employ vacuum assist functions to compensate for large wafer warpage.

AT&S / EPCOS

In July 2013 AT&S (Austria) and TDK-EPCOS announced that they were cooperating on embedding technology to allow standards development and increased customer acceptance [link].

The embedding technology developed by AT&S is shown below:

AT&S 1

The authors propose that the use of PCB real estate is lowest for an emedded component and showed the following comparison to a 3x3m die + 10 resistors packages with a QFN (45mm sq)vs flip chipped (21mm sq) vs embedded 916m sq).

AT&S 2

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IFTLE 177 Monolithic 3DIC ; Merck acquires AZEM; Intel Invests in SBA Materials; Xilinx Semi Award

Will Monolithic 3D IC Technology become a real competitor to 3DIC with TSV

The language of 3DIC is certainly a bit confusing. In the past I have made fun of EE Times reporters confusing BE finfet technology with TSV based 3DIC. [ see IFTLE 62 “3D and Interposers – Nomenclature confusion; Equipment Market Shift to Pkging Continues” ].

There is also confusion brewing concerning TSV based 3DIC and what can be called monolithic 3DIC.

Back end (BE) 3DIC with TSV is a parallel process where each layer or stratum is fabricated with TSV separately and subsequently joined. Monolithic 3DIC is a front end (FE), sequential process where a second layer of silicon is deposited or grown onto the first finished chip and the transistor and interconnect processes are repeated.

The issue with the sequential process has always been the temperatures required to deposit or grow a second crystalline layer of silicon on top of the IC. It is difficult to overcome the 400°C process temperature limitation imposed by the use of aluminum and copper IC interconnect  when creating the second layer of silicon and implanting and annealing the second layer of transistors.

For instance the early work of Akasaka-san at the LSI R and D Labs of Mitsubishi Electric described the basic concept of monolithic 3DIC as shown below.

Fig 1

Akasaka, Y., Nishimura, T., Concept and Basic Technologies for 3DIC”, IEEE Proceed., nt. Electron Device meeting, vol. 32, 1986, p. 488

It was clear nearly 30 years ago that “to fabricate 3-D IC successfully, a wafer temperature during the crystallization should be kept low enough not to destroy the device or not to change the device performance fabricated in the beneath layer”. They proposed that the key was to “to control the thermal profile in the polysilicon layer” and Akasaka proposed “…a laser or an electron beam recrystallization is thought to be a suitable method due to their effective low process temperature.”

Certainly laser annealing has come a long way since the first prognostications of Aksaka.

fig 2

Zvi Or-Bach of Monolithic 3DIC is now proposing the use of smart-cut® for the formation of the second strata (and not amorphous silicon crystallization) with shielding layers to protect the first strata interconnect, as shown below.

fig 3

Will these advances allow monolithic 3DIC to compete with TSV based 3DIC ? Some say that sequential 3D technology can be much less complex and expensive to implement,…maybe we will be finding out soon.

CEA-Leti recently announced an agreement with Qualcomm to assess the feasibility and the value of sequential 3D technology [link]. The program between Leti and Qualcomm reportedly “..will  allow the critical assessment of this technology in the context of practical applications, further evaluating the potential impact of this sequential 3D technology for future industrialization.”

In early January Taiwan’s National Applied Research Laboratories (NARL) said can use monolithic 3D-IC technology to make “super chips” [link].They reported that it “enables 150 layers of chips to fit in space once used to stack a mere two chips using traditional technology while helping improve signal propagation speed and provide a higher order of connectivity.”

[ IFTLE note – “150 layers is likely the silliest marketing statement  I have seen since IBM and 3M released the headline claiming “3M and IBM today announced that the two companies plan to jointly develop …. stacked silicon towers…..commercial microprocessors composed of layers of up to 100 separate chips.”[link]

At the recent IEEE  IEDM meeting Taiwan’s National Nano Device Laboratories described  fabricating a monolithic sub-50nm 3D chip, which integrates high-speed logic and nonvolatile and SRAM memory. To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then thinned and planarized the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints.

Merck to Purchase AZ Electronic Materials (AZEM)

Consolidation in the microelectronics industry continued in Dec when Merck agreed to buy AZ Electronic Materials SA (AZEM) for $2.6 B [link]. Merck which controls the liquid crystal market for flat panel displays now becomes on the largest photoresist suppliers.

Intel Invests in SBA Materials

Startup Santa Barbara Materials (SBA Materials) with patented “Liquid Phase Self Assembly” technology is a nano–‐structured, advanced siloxane based approach to porous compositions that could have use in electronics, optical and energy storage arenas. IFTLE has been keeping an eye on SBA for several years since they appear to be the only SiO2 dielectric choice for Low K IC chips that can actually deliver on sub 2.5 Dk [ see “Low-k dielectric family introduced by SBA Materials” and IFTLE 138,  “Foundry Intel; 300 mm Capacity; SBA Low-K Oxide”].

SBA has recently closed  a series B financing round which included Intel Capital as one of the investors. [link] CEO Bill Cook indicates that more will be coming on the strategic investor front “soon.”

2013 Semi Award to Xilinx

SEMI has announced that Xilinx is a recipient of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer “which provides more than two orders of magnitude increase in die-to-die bandwidth per watt. This achievement effectively addressed both challenges of decreasing power and increasing bandwidth for advanced digital ICs. It also decreased latency to only 20 percent for standard input/output connections. Initially announced in 2011 and first shipped in 2012, the incorporation of a silicon interposer, also called 2.5D technology, delivers performance and power requirements dramatically improved compared to standard packaging” Liam Madden  accepted the award on behalf of the Xilinx which includes Trevor Bauer, Liam Madden, Kumar Nagarajan, Suresh Ramalingam, Steve Trimberger, and Steve Young.

Semi stated that “Xilinx use of a silicon interposer in their packaging of advanced FPGA represents a major innovation in assembly and packaging technology and provides a learning curve for the many of the technologies that will be needed for high-volume production of 3D-stacked die…. While the elements of redistribution layers on silicon, TSVs, and microbumps were already available [they had not been combined commercially] to provide this high bandwidth, low power packaging solution.”

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