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IFTLE 271 IMAPS 2015 Part 4: Scallop-less Etching; Gold Sealing; PI vs PBO; TLPS

By Dr. Phil Garrou, Contributing Editor

Finishing our look at IMAPS 2015…

ULVAC – TSV etching

ULVAC has developed an etch tool capable of both Bosch etching and their “direct etch” process. Direct etch uses a mix of SF6 and O2 and can result in either a sloped or straight sidewall as shown below. They claim that the direct etch results in significantly shorted PVD time and that the taper vias can result in 80% less electro dep time when filling the vias.

ULVAC 1

Tanaka Kikinzoku – Gold sealing technology

Tanaka Kikinzoku shared their results on hermetic low temp sealing for MEMS and WLP. They developed a wafer level hermetic sealing process using a rim structure covered with sub micron gold particle paste by stencil printing as shown below. The maximum leak rate was found to be 10-14 Pa·m3/s (He)

tanaka

 

Asahi Kasei Electronic Materials

Asahi Kasssei (AKEM) shared their studies on the thermal cycle testing of organic passivations for WLSCP…well really they didn’t share them and I have a few comments about that. Through the years I have complained about reports that fail to fully identify exactly what they are examining. Many of us know them as A,B,C,D papers ….you know “A was much better than B and somewhat better than C and D.” This complaint is not pointed only AKEM, but rather at the many companies and institutes who publish such papers.

Granted such papers can lead us in the right direction if they are commenting that certain properties lead to better results, but they can never be reproduced since no one else knows what it was that was examined.

AKEM introduced their studies by indicating that previous studies had found that PBO failed thermal cycling tests (TCT) earlier than PIs and they wished to know why. The problem is that there are many different types of PIs and PBOs. The examples you choose to compare will totally control the results that you get. The only hints we get is that their PI is a low cure version (“imidization of our specific PI is finished at 200C”) Would it have hurt to give us an experimental or commercial designation ? since AKEM has not chosen to share the structure of this material with us. Even worse is the identification of the PBO. The comment is made that “..the cure temp of the typical photo PBO is over 300 °C …” It is not clear that this is the kind of example that they used and certainly not clear why they used a high temp cure PBO to compare to a low temp cure PI. Those of us in the field know that there are many low temp cure PBOs to choose from.

As an example their examination of strain change vs time (fig 11) they state that “strain is effected by the polymer difference. Equivalent strain in the case of PBO is larger than PI because the modulus of PBO is lower than PI.” Would it not be better to test two known PIs and two known PBOs of differing modulus to make this case? Since I do not know the identity of the two materials that they chose to compare, I cannot draw a clean conclusion about any of their results. I think you see the point.

ORMET – Transient Liquid Phase Sintering (TLPS)

Ormet has been around our industry since the late 1990’s optimizing their TLPS products. ORMET has recently been acquired by Merk. They view their materials as solder replacements for either hierarchical soldering (consecutive joints are soldered at sequentially lower temps) applications where solder remelt is a problem such as MEMS lid attach, SIP and PoP.   Also for high operating temp market segments such as power electronics. Basically the TLPS pastes consist of a high mp metal (copper), a low melting point alloy ( SnBi) and a flus-polymer phase. As the temp is raised the alloy begins to melt and reacts with the high mp metal to form high mp alloys or intermetallics until there is no longer a molten phase at that temp. Pastes are formulate specific to the application.

Ormet 1

They have worked with Kemet to develop a line of pastes for MLCC attach (multi layer capacitors) for high temp applications. Such materials have passed high temp storage (175 C for 2000 hrs); thermal cycling (-40 to +175 for 2000 cycles) and temp humidity bias (50V, 85C/85%RH 2000 hrs) without any failures. Brittle Cu/Sn intermetallic phases are found to initiate some cracks but appear to terminate on the Cu particles.

For all he latest on 3DIC and other advanced packaging stay linked to IFTLE…

IFTLE 270 IMAPS 2015 Part 3: High Density PCB Technologies; Unimicron, Princo

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Conference.

Unimicron

Unimicron discussed their continued development of < 5/5 L/S for polymeric interposer applications.

While silicon can meet fine line (< 5/5 L/S) requirements easily by wafer level processing, silicon processing cost is a barrier to many applications.

There are two types of processes available to meet fine line requirements on organic substrates, traditional semi-additive processing (SAP) or laser embedded technology. They are shown in xsect below. Unimicron reports that current status for SAP is 8/8.

unimicron 1

UV YAG lasers allow for maskless ablation processes by ablating trenches and blind vias simultaneously, but the throughput becomes slow as the features get larger. Throughput of eximer lasers is independent of pattern features since they are defined by the mask. The aspect ratio (h/w) for eximer laser was 1.2 for 3/3 in build-up film with fine filler particles and for 5/5. In general, the finer the filler particle size, the deeper the trench. Since they found that eximer laser ablation was much slower than lithography, the next developments will be with photo build up dielectric to replace the laser ablation. IFTLE should note that this is how it was done during the MCM era in the mid 1990’s, like the IBM SLC technology.

Princo – System on film

In yet another chips last packaging solution, Princo described their system on film technology. Following the figure below they 200mm glass wafer that is first surface treated with a PI and then a silane release coating then another PI layer. Steps 4 to 7 are a lift of copper metallization sequence (6/4um L/S ; 11um thick). Next comes a dielectric layer ad then laser formed vias. These steps are repeated for further layers (up to 8 so far). In step 14, the structure is released from the carrier. This RDL film wafer is then flipped over and the pads are opened through the PI layer and ENIG coated. Die are flip chip mounted, underfilled, overmolded and balls attached and balls placed.

They describe two modules. Module #1 consists of a µprocessor, LPDDR SDRAM / NAND flash combo memory and power management IC on a 6 layer 20 x 17mm module. The second module consists of a µprocessor and a bluetooth 4 dual mode chip packaged in a 4 layer 9.5 x 7.3mm thin film package.

Princo

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 269 IMAPS 2015 Part 2 High Density Packaging ASE STATS Nanium

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2015 IMAPS Conference.

YOLE

Advanced packaging has increased in complexity over the years, transitioning from single to multi die packaging there are several platforms now available as summarized by Beica of Yole in the following figure. When choosing a package solution, typically the most mature and established will be considered first.

yole beica 1

When looking at flip chip ~ 37% of the cost is attributed to the substrate. The substrate also increases the thickness of the package.

yole beica 2

Fan out packaging offers increased I/O but also a thinner package since the substrate is not required. Initially limited to eWLB licensees from Infineon (Nanium and STATSChipPAC) the market is expected to explode in the next few years as ASE, SPIL, Amkor TSMC and DECA bring fan out capacity online.

Yole’s Ivankovic compared expectations for glass/silicon interposers vs polymeric substrates. Glass interposer technology is still immature. Polymeric sub 10um L/S substrates are promising but need cost reduction and further L/S reductions. The sweet spot for silicon interposers appears to be up to ~ 3/3.

IFTLE feels that silicon interposers with coarser L/S can surely be manufactured but will not compete on a cost basis. A substrate technology gap exists between 10 and 1um. This will be where the battle for business will be fought.

yole ivanovis 1

ASE FOCLP

Chen of ASE escribed their new Fan out Chip Last Package (FOCLP) which they see as a low cost alternative to eWLB FOWLP solutions. Copper pillar bumped die are mass reflowed onto a low cot coreless substrate, followed by overmolding, which also serves to underfill the die. The Cu pillars allow die connection at 50um or below, negating requirement for RDL n the die. The Cu pillars are bonded to one side of the copper trace (down to 15um L/S) and solder balls are directly bonded to the other side. This makes the “substrate” be effectively as thick as the copper in the traces and allows the final package to be as thin as 400um. Implementation with multiple die, inclusion of passives and 3D structures can all be implemented.

ASE foclp1

STATSChipPAC – High Density eWLB

Currently eWLB devise are used in baseband processors, RF transceivers, power management ICs, NAND memory controllers, on 2 node and ramping on 20nm. In a number of cases STATS reports a 20-40% reduction in package size and a 50% volume reduction due to its slim form factor.

STATS presented their work on with Qualcomm defining eWLB technology with high density ( 2/2 L/S ) and multilayer RDL. Their test structure contained 3 layers of RDL with 2/2, 5/5 and 10/10um L/S.

STATS 1

These structures were built and passed std JEDEC reliability testing.

Nanium – Advances in eWLB

NAnium described new developments in eWLB technology. Kroehnert indicates that the first eWLB based products have been qualified for wafer level SiP and WLPoP with embedded multi die, discrete passives, already packaged components sensors and optical elements.

Nanium

Nanium eWLB Placement before Overmolding

As thin 300mm reconstituted wafers are not stable enough to be handled in traditional equipment, temporary bonding of recon wafers was developed. They found significant impact from bot the temp bond adhesive and the carrier composition.

The majority of work being done is to enable higher density integration:

– finer L/S

– multilayer RDL routing

– multi die placement with smaller inter chip distances

For all the latest in 3DIC ab=n other advanced packaging stay linked to IFTLE…

IFTLE 268 IMAPS 2015 Part 1: A Comeback for WLP in IoT

By Dr. Phil Garrou, Contributing Editor

IMAPS 2015 also known as the 48th International Symp on Microelectronics was held this past Oct in Orlando, FL. Umi Ray of Qualcomm was General Chair and Erika Folk of Northrup Grumman was Tech Chair. There were 30 sessions, > 150 presentations and > 135 exhibit booths. Certainly, in terms of microelectronic packaging, this is the largest annual exhibition in the USA. In the next few weeks we will take a look at some of the presentations that caught the eye of IFTLE…

First, let’s first take a step back to one of the best boxing movies of all time, ROCKY. In 1976, Sly Stallone (who by the way spent his early years growing up on my block in Hell’s Kitchen, NYC) wrote and starred in this rags to riches American Dream story of Rocky Balboa, an uneducated but kind-hearted boxer in the slums of Philadelphia who gets a shot at the world heavyweight champion Apollo Creed, and looses the fight. The film earned three Oscars, including Best Picture. In 2006, the film was selected for preservation by the Library of Congress as being “culturally, historically, or aesthetically significant.”

Rocky

Anyone who saw the film at the time will never forget the single line that ended the movie. As the ring announcer is proclaiming Creed the winner, Rocky, with both eyes swollen shut, is shouting out “Adrian!, Adrian!“ calling for his girlfriend (Talia Shire) . It brought grown men and women to tears. [link]

Anyway after many sequels, none of which came anywhere near the quality of the original, fast forward to 2015 and the movie “Creed” where Adonis Creed, Apollo’s son asks Rocky to become his trainer after no one else will work with him. In a strange twist of fate Creeds son also ends up fighting against the champion and looses but “…though he lost the fight, Creed won the night”. For his performance, Stallone has been nominated for the Golden Globe Award for Best Supporting Actor in a Motion Picture, his first nomination since the original Rocky, 40 years ago. Certainly a comeback for Rocky!

So you ask yourselves where is IFTLE going with this? Be patient.

I want to start our look at IMAPS 2015 with the presentation by the new Yole Developpement packaging team on the technology and market trends for WLP. You may wonder why I focus on this technology which was Leading Edge literally 20 years ago. Certainly it is near and dear to my heart since many of my most exciting days in technology were shared with the WLP pioneering groups at Flip Chip Technologies (FCT) and Microelectronics Center of NC / Unitive as this initial wafer level technology was being conceived and developed with my team developing BCB. These two small startup companies certainly were underdogs, and they were using my new dielectric, also an underdog, but within 2 years we were in nearly every cell phone made in the world.

Since it’s inception by Rajen Chanchani at the Boston IMAPS conference in 1994 to the commercialization of the UltraCSP by Pete Elenius of FCT in 1998, what was at first one of many chip sized package solutions evolved into wafer level chip scale packaging and then more simply into wafer level packaging or WLP.

[for a complete history of bumping and WLP see “On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging,” A. Huffman, P. Garrou, (link)]

By the early 2000’s it became obvious that WLP had unmatched advantages in both form factor and cost and the technology was quickly licensed by all the key OSATS and OEMs worldwide and adopted in nearly all mobile phone products. 20 years ago this was the leading edge and those working in the area and finding success felt like this [link]:

“Trying hard now…It’s so hard now…Trying hard now”

“Feeling strong now…won’t be long now…getting strong now”

“gonna fly now….flying high now…gonna fly…fly… fly ! “

Yole points out that although WLP has been seemingly out of the spotlight with the advent of higher density packaging solutions such as copper pillar bump, 2.5 & 3DIC and fan out and embedded packaging, WLP remains a highly important and constant presence. The mobile market continues to be the main driver for WLP with over 90% of all fan in packages being found in handsets and tablets.

Since the WLP eliminates the need for WB, substrates, FC bumps and in most cases mold compound, it still results in the shortest interconnects, lowest parasitics, and best electrical performance in terms of speed and frequency. Bump pitch of 0.35mm are currently in high volume production with 0.3 and 0.25mm under consideration. Most fan-in die are below 7 x 7mm and below 200 I/O. In general warpage and board level reliability for larger dies remains a concern. If your die is relatively small and your I/O demands relatively low, this is the best packaging solution.

fan in limits

Fan-in WPL units hit 35B in 2014 with a 9% CAGR. BT + WiFi + FM combos, CMOS image sensors and Rf transceivers account for ~ 50% of all WLP applications.

unit forcast

Yole has identified more than 70 high volume fabless and IDM companies implementing their designs in fan-in WLP along with over 20 fan-in manufacturing companies.

What the Future Holds for WLP

In the future IoT (Internet of Things) will eventually succeed mobile phones as the microelectronic driver…the big dog. However, there have been many unjustified presentations over the last few years detailing, without any support data, how IoT will drive leading edge, high end technologies like 3DIC. IFTLE does not agree with that conclusion but rather contends that IoT will be low I/O and will demand two things – small form factor and low, low cost. As such IoT will generate a huge potential market for fan-in WLP.

Back in the mid 1990’s, WL-CSP was an underdog who proved itself and became an integral part of cell phone manufacturing and, now after being somewhat overshadowed by newer leading edge technologies for a while, is about to make a comeback due to the inherent strengths of this technology. Anyone care to bet against it?

For all the latest in 3DIC and other advanced packaging technologies, stay linked to IFTLE…

IFTLE 267 The 2015 IWLPC: DECA, SPTS, IMEC / KLA-Tencor, IMEC / EVG

By Dr. Phil Garrou, Contributing Editor

This week, let’s take a quick look at the 12th annual Int. Wafer Level Packaging Conference (IWLPC) which was held in San Jose in October. But before we do, a Christmas message from my granddaughters:

H&M

IWLPC 2015

The 2015 IWLPC technical focus consisted of   1) fan-out WLCSP, 2) 2.5 and 3D IC packaging, and 3) MEMS. This conference is becoming a major player in the exhibition end of the packaging business this year having 65 booths set up in San Jose.

IWLPC

DECA

We have looked at the activity of Deca several times since their initial pronouncements in 2012 [see IFTLE 124, “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP” and IFTLE 175, “2013 IWLPC; 450mm on Hold?”]

Cost, yield and reliability issues have effectively limited the widespread adoption of FOWLP. Placing singulated chips on the carrier to form the molded panel requires high placement accuracy. Any misplacements can lead to pattern overlay difficulties in the buildup process on the reconstituted panel. The requirement for high placement accuracy restricts throughput at the pick-and-place operation, leading to high process costs. During the molding operation and mold cure, die drift or movement can occur. This die drift can further complicate pattern overlay matching in the buildup process on the panel and can result in yield loss when the drift is excessive.

In the DECA process die with preformed Cu studs are placed face-up on a carrier, using a high speed pick and place tool. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs. A high speed optical scanner is used to determine the actual position of every die on the panel. This information is fed into a proprietary Adaptive Patterning design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. Adaptive Patterning works by dynamically adjusting one or more build-up layers to accurately connect to the Cu studs protruding through the mold compound for each individual die in the molded panel.

After the Adaptive Patterning design files are created, fan-out processing can commence. The build-up proceeds through polymer 1, RDL, polymer 2 and UBM layers, with the lithography system implementing unique designs at the polymer 1 and RDL layers on a per panel basis. Finally, ball attach and package finishing are performed to produce singulated fan-out packages.

deca 1

The board level reliability was examined for a 8mm X 8mm package with 324 IOs on a 0.4mm pitch. The packages were mounted to 1mm thick printed circuit boards (PCBs) with non-solder-mask defined PCB pads. Standard JEDEC conditions were used for temperature cycling and drop testing. First cycling failure occurred at 665 cycles and with no failures observed up to 250 drops.

SPTS – Plasma Dicing

Plasma dicing is attracting significant interest within the semiconductor industry as a viable alternative to conventional singulation methods using saw blades or lasers. Plasma dicing promises benefits such as increasing wafer throughput, die per wafer and die yields (due to low damage processing). For small die, in particular, where the time required for a high number of mechanical slices in “series” can be substantial, a “parallel” process such as plasma dicing which etches all dicing lanes simultaneously, can significantly increase wafer throughput.

Maximum benefits are gained when plasma dicing is “designed in” from the beginning. With dicing lanes defined by photolithography, these lanes can be narrower than the width of a dicing blade, saving valuable silicon real-estate which can be used to increase the number of die per wafer. Also, the designer can make sure that dicing lanes are free from metals and other layers which can hinder plasma etching. This is often quoted as the prime challenge which prevents implementing plasma dicing in an existing production scheme.

IMEC / KLA Tencor

IMEC / KLA Tencor shared their results on investigations to determine the best way to insure µbump presence and co-planarity. µbump dimensions are being scaled down to 20 um pitch (10 µm in width and 8 µm high). For die-to-die and die-to-wafer stacking, the need for highly accurate and repeatable measurement of µbumps at both die-level and wafer-level is a must for this technology to become a viable industrial option.

Bump co-planarity is defined as the difference between the heights of the tallest and the shortest µbump within a die as shown below.

IMEC 1

A failure to properly characterize the co-planarity of each die and detect defects of interest such as damaged, missing or mislocated bumps can lead to the wrongful classification of the die as suitable for asembly. This may have a number of yield-affecting consequences during stacking, such as open and short circuits, die cracking and thermal sinks. As the number of die in a typical die stack increases, a single falsely classified die will affect the entire product.

One of the challenges in constituting a meaningful subset for measurement is to define a population of µbumps which is large enough to be statistically significant and to select µbumps from areas in the die which will represent height range and coplanarity of the full die.

Nanium / EVG

Nanium and EVG shared some information on Temporary Wafer Carrier Solutions for Thin FOWLP and eWLB-based PoP.

In order to achieve a cost competitive position related with other packaging technologies, FOWLP has been using 300mm diameter reconstituted wafers, which brings challenges related with its mechanical and thermomechanical properties like wafer bow, wafer warpage and wafer expansion. Nowadays, more FOWLP designs require reconstituted wafers with thickness below 400um. When wafer thickness drops below 400~450um, the reconstituted wafers acquires a flexible behavior that does not allow self-supporting handling anymore.

Adding to this challenge, the need for RDL processing on both sides of the eWLB wafer, for 3D and PoP constructions, requires the temporary protection of one RDL side while the other is being built. Solutions such as temporary wafer bonding for 2.5/3DIC technology , cannot be copied-exact for eWLB wafers because of the very high and non-linear thermomechanical behavior of such wafers and to the temperature limitations the molded material imposes. For example, Si wafers failed as carriers due to the mechanical mismatch to eWLB wafers and with adhesives with bonding process temperature above 200ºC . The selection of carrier wafer and adhesive material are key elements to the success of any temporary bonding and debonding technique for eWLB or fan out in general.

Based on their studies we are not told what the preferred carrier or temp adhesive are, but we are led through several solutions and told what properties lead to the best results.

For all the latest on 3DIC and other advanced packaging options, stay linked to IFTLE…

IFTLE 266 IMAPS Goes Searchable; GaTech Interposer Conf Part 3

By Dr. Phil Garrou, Contributing Editor

IMAPS now “Googleable”

Of upmost importance to researchers at Universities, Research Institutes and even Commercial Companies is the ability of others to find their publications.

For years, a pet peeve of mine with IMAPS (the International Microelectronics and Packaging Society) is that once your work was published it was …well…lost. Mind you I was Technical VP and then President of the Society in 1997 so I’m not some complaining outsider. I have been saying this for more than 20 years. Certainly their journal and proceedings are “archival” in the technical sense of the word. Both are bound and printed and available to individuals and libraries for posterity, but many of their conferences containing key publications are only available if you know they exist and go to the IMAPS web page to download them.

In the 1990s most of the key papers on multichip modules (MCMs) were put into the conference of the same name that many of us sponsored through IMAPS. It was a great Conference, but try finding those papers now unless you have copies of all those proceedings.

Nothing has changed more in my lifetime then how we write reports and share data. In 1975, my first year in industry, we wrote report drafts on yellow legal paper and gave them to the office secretarial pool to type for us. They went back and forth a couple of times (since they couldn’t read my handwriting) and figures were added after they were drawn on a draft board.

Literature searching was done in the library where you combed through books and journals till you found what you were looking for. Once you found a key paper you went through all the references in that paper and went backwards like that till you were pretty sure you had found everything that was worthwhile.

All that changed with the computer and the internet. The computer which we got individually in our offices ~ 1985 (best I can recall) caused the unemployment of a lot of young women in the secretarial pool, but it sure increased my productivity in terms of putting a report together. Internet searching of the scientific literature came a bit slower, but by the late 1990s, or certainly by the time Google Scholar came into being in 2004, most researchers simply put their queries into the Google and up popped more references than you could read.  Everything was now available, well everything that Google searched. You can also easily see where this leads. If everyone only references things that are searchable in Google, then after a few years the only references you can find are those that are searchable by Google. Not so great for scientists publishing in non searchable sources.

The Europeans caught on to this problem first and we saw IMAPS conferences in Europe requesting co-sponsorship of IEEE so that their work would be put into IEEE Explore (yes its Google searchable).

It has taken awhile, but after a lot of bitching by myself and others and a lot of hard work by IMAPS staff everything is now searchable back to 2010. Not only the journal and the annual fall meeting but also key conferences like the Device Packaging Conference (DPC). YES – all the slides presented at the DPCs (since 2010) are now searchable and downloadable. I have tested this out myself and sure enough Google now finds them. For more details try www.imapsource.org/

Georgia Tech Interposer Conference (GIT 2015)

Finishing up our look at the GIT, lets look at Intels EMIB and the SPIL / Xilinx SLIT

EMIB

Intel is still keeping design flow and ground rules for EMIB (embedded multi die interconnect bridge) close to the vest and I did not see much new from Bob Sankman.

emib 1

Certainly the EMIB eliminates a chip attach operation since there is no Si interposer, but the BGA substrate sure looks a whole lot more complex to me. It certainly is an elegant solution, but I’m not convinced it is the low cost solution till I hear from customers what these modules will really cost. It certainly is of interest that Altera has announced a Stratix 10 to be done with EMIB.

emib 2

SLIT

Xilinx and SPIL were he first to announce TSV free high density interconnect more than a year ago. See IFTLE 215, “STATS Acquisition; Will SLIT replace TSV?”]

Xilinx indicates that the UMC/SPIL version of CoWoS, SSIT is ready for production.

SLIT 1

SLIT offers

– 65nm BEOL design rules                                                                                                                                             – non TSV interconnection                                                                                                                                                    – reduced CAPEX                                                                                                                                                                              – less inspection metrology steps                                                                                                                                             – SLIT patent issued to Xilinx

Xilinx compares SLIT to other solutions below:

slit 2

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

 

IFTLE 264 2015 GaTech Interposer Conf Part 2: The Status of Glass

By Dr. Phil Garrou, Contributing Editor

The GaTech group ad many of their members have been studying the applicability of glass as 2.5D interposers for several years now. Some of the papers presented at this year’s meeting updated the industries status in this area.

LPKF Vitrion

LPKF Vitrion updated the attendees with their latest Through Glass Vias (TGV) technology status which is shown below.

LPKF 1

Shinko

Shinko updated their 2014 presentation on the status of Glass interposer R&D and manufacturing. Shinko is looking at glass as an alternative to silicon interposers. Their proposed process flow is shown below.

shinko 1

An example of a fully assembled glass interposer is shown below.

shinko 2

Shinko points out that there are voids inside the TGVs and they are very difficult to avoid. These voids increase the via resistance ~ 8.5%. They are in the process of determining what the acceptable void content is.

shinko 3

They are capable of 2um L/S RDL on the glass. They are in the process of reliability studies and failure analyses.

They are currently examining 250mm sq panels which increase unit production 2.7X vs 200mm wafers.

Unimicron

DC Hu from Unimicron shared their perspective on glass technology readiness. Hu lists the following requirements for glass mass production readiness:

Based on 510 x 510mm panels and 2/2 L/S fine line capability

– glass process readiness

  • Thin glass handling
  • Via forming technology
  • Via filling technology

– production equipment readiness

– reliability

He compared TGV formation from Via Mechanics, LPKF, Corning, Schott and Asahi Glass and via filling by seed and plate vs screen printed paste technologies. The paste technologies appear capable of 20um vis on 50um pitch.

While plating can be done on a 500mm sq panel, fine line patterning (2um L/S) requires a large panel stepper.

unimicron 2

Technology status vs silicon is shown below.

unimicron 3

TDK

TDK discussed what they claim is the first glass based Rf modules. Rf integration is clearly the key enabler for next gen smartphones. Key technologies for Rf modules are shown below.

TDK 1

The glass Rf module concept, which is being developed with GaTech, is shown below.

tdk 2

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 263 GIT 2015: High Density Laminates and Lasers – Kyocera, ESI, Suss

By Dr. Phil Garrou, Contributing Editor

The Georgia Tech High Density Interposer Technology conference (GIT) held a few weeks ago in Atlanta. Traditionally it has been a great place to compare and contrast high-density interposers in silicon vs glass vs laminate. In the next few weeks, we will take a look at some of the key presentations.

Kyocera – Adv Laminate Packaging Design Rules

Some of you youngsters might not recall that Kyocera the ceramics company expand into the high density laminates business when they purchased IBM Yasu production in 2005. In the late 1980s and early 1990s, IBM had been working on increasing the density of laminate packages by adding thin film layers with photo vias. They called these SLC (surface laminar circuits) Such high density BGAs were necessary for flip chip packaging to move to HVM. This all took off ~ 1992 when IBMs Yutaka Tsukada announced the technology for flip chip underfill and SLC circuits. Ground rules for the first gen SLC are shown below:

kyocera 1

 

Kyocera, seeing that higher densities and lower costs would not be coming from the ceramics business, made a bold move a decade ago when they bought the business from IBM. It is interesting to look at how the technology has advanced in a decade. Their latest ground rules are shown below.

kyocera 2

ESI – High Accuracy Lasers for Adv Packaging

Electro Scientific Industries (ESI) shared the latest results with their CornerStone ICP Series UV laser drilling system designed for use in Integrated Circuit Packaging applications.

They report positional accuracy of +/- 4 µm and 10 µm via capability with AR of 1:1.

esi 1

 

System capabilities are summarized below:

esi 2

In addition, the new system has a 25% smaller footprint than typical laser drills in HVM production today.

Suss Microtec – Eximer Laser Ablation for Adv Packaging

Suss shared their information about damascene processing of RDL using their eximer laser tool. The eximer laser is used with mask based projection with a field area of 35 x 35mm sq.

suss 1

 

Suss has developed a process flow for the stacking of high density RDL layers using non photo dielectrics.

Suss 2

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFLE 262 SEMICON Europa part 1; Update on G450, Panasonic Plasma Dicing; Thin Flexible Die Packages; Osram reviews LED packaging options

By Dr. Phil Garrou, Contributing Editor

G450 – 450mm wafer status report

For most of us, whether we work in the FEOL or in packaging, what we want to know about the attempted move to 450mm wafers is (1) if it will really happen and if so (2) when will it happen. Unfortunately, those answers are not yet clear. The recent G450C update at SEMICON Europa shared some new information, but we really cannot expect such a highly politicked program to ever come out and say “This just isn’t going to work.”

G450C is a collaborative consortium being run at the Albany nano tech center. Members are Intel, TSMC, GlobalFoundries Samsung and IBM. IBM, recall has sold off all production capability to GF, so this program, to them, is really a window on what can be done, not something they will commercialize.

The consortium goal is to have a “full flow 14/10nm process capability on line by 2016.” Of interest was their tool installation status report as shown below.

G450-1

In terms f process readiness, they reported the following:

  • Process Capability demonstrated on 98% 14nm process steps
  • Productivity: 80% of process tools can achieve 300mm equivalent or better (WPH)
  • Performance: Process tools at or near 300mm process targets
  • Suppliers can deliver HVM tools in 18-24 months after signals
  • Potential die cost savings of >30% achievable

Panasonic – Plasma Dicing

Panasonic reports that plasma based dicing is both damage free and results in more die per wafer due to the narrower dicing streets. Panasonic reports etch rates of 20m/min with their APX300 HVM tool.

panasonic 1

 

In addition, the fracture strength of the silicon is greatly increased.

panasonic 2

Front side and backside process flows are shown below.

panasonic 3

Fraunhoffer EMFT – Ultra-thin devices in flexible packages

Christof Landesberger of Fraunhoffer EMFT discussed their program to develop a processing scheme for embedding and interconnection of ultra-thin IC devices in flexible chip foil packages.

Target applications include:

  • Smart phones – Reduce package thickness
  • Healthcare and Wearables
  • Large area electronics; e. g. bendable displays and photovoltaic modules
  • Sensors on curved surfaces; to be adapted or integrated to machines, buildings, robots, housings
  • IoT applications

The key question to be answered is: “Will there be increased mechanical robustness of ultra-thin silicon die after embedding them in films?”

They report a strong increase in breaking force for ultra thin silicon after embedding as shown in the following weibull plot.

EMFT 1

 

Their process flow is sown below.

EMFT 2

In their micro controller demonstrator, 25um thick die are inserted in the cavities on the flexible substrate. The chips are covered by 10um of thin film dielectric and patterned and connected. The final packages showed no cracking or delamination after bending.

Their initial conclusions are hat rigid packages will be used for 50-150um thick die and such flexible packages will be used for ultra thin, 10-30um die.

Osram – review of chip interconnection in LED packages

Standard LED packages remain lead frame based. They are:

– easy to assemble by standard SMT reflow

– show the lowest manufacturing cost

– integral solder pad with excellent heat sinking

– single WB interconnect with proven reliability

osram 1

A multitude of packaging configurations are available and are being used.

osram 2

Die attach methods include conductive epoxies, non conductive silicones, sinterable materials and eutectic metal solders which all provide different thermal performance and cost and ae better compatible to different packages.

osram 3

 

Amongst other things, they conclude:

– When comparing acrylate based silver filled die attach to their epoxy counterparts Osram finds that the acrylates show less stable interconnection after solder heat treatment.

– Corrosive gasses like moisture, NO2 and SO2 diffuse through clear silicone encapsulant. Attack on copper is even worse. Hybrid silicones should be used as well as Ni diffusion barriers for copper gold plated surfaces.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 261 Consolidation Continues; the Info on InFO?; RTI 3D ASIP

By Dr. Phil Garrou, Contributing Editor

Consolidation in our maturing industry is the ONE most important this that is happening to microelectronics in the 21st century because this is/will set the playing field for everything that follows. Many of you will be working for massive new companies soon whether you know it or not. This is something you really should be paying close attention to.

LAM Acquires KLA_Tencor

Consolidation continues with the recent announcement that Lam will acquire KLA-Tencor in a cash and stock transaction. The combined company will combine Lam’s capabilities in deposition, etch, and clean with KLA-Tencor’s capabilities in inspection and metrology. The combined company will have ~ $8.7B annual revenue making it roughly the same size as AMAT.

There will likely be opposition from some in the semi industry but probably less so than for the AMAT/TEL proposed merger since there is really little overlap in their focus markets.

Western Digital (WD) to Acquire SanDisk

The hard disk drive segment of our industry reached maturity ~ 2011. The hard disk drive business started in the 1960’s. Since then the > 200 companies who have been in the business competed on data density and latency and smaller form factors. Most of that industry has long since vanished through bankruptcy, mergers and acquisitions. As expected for a mature industry segment there are now 3 surviving manufacturers – Seagate, Toshiba and WD. Seagate acquired Samsung’s HDD business in 2011; Western Digital (WD) merged with Hitachi’s HDD business in 2011 and Toshiba acquired Fujitsu’s HDD business in 2009. This divided up the HDD market into WD 48%, Seagate 40% and Toshiba 12%.

Growth in mature industry segments requires acquisitions in aligned fields. Thus it could have been expected that WD would make a move into other types of data storage. WD’s acquisition of SanDisk gives the company an instant foothold in the global, non-volatile NAND flash memory market.

With the PC HDD business in decline due to both a weakening PC market and solid state drives (SSDs) making major inroads into that market, WD needed access to NAND storage technology both for laptops/desktops and to maintain competitiveness with NAND players in the enterprise space. This acquisition will allow WD to expand its participation in higher-growth memory storage segments.

It is reported that WD will have to raise $18.4 billion to finance the $19B SanDisk acquisition. In September WD announced that Chinese state-backed Unisplendour Corporation ( a subsidiary of Tsinghua Holdings ) would be investing $3.8B for 15% of WD “to help facilitate growth and future strategic initiatives.”

Sony Acquires Toshiba’s CMOS Image Sensor Business

Toshiba has announced that it will sell its image sensor business to Sony for ~ $166MM and pull out of the sensor business. For Sony, the acquisition of Toshiba’s image sensor business would further solidify its already dominant position in the industry where it already controls 40% of the market.

For those of us that have been following 3D with TSV since its inception, we recall that Toshiba was responsible for one of the early milestones, namely it was Oct 2007 that Toshiba announced the commercialization of their “chip scale camera module” which used “through chip vias.” Although it was only a one layer device, it marked the first mainstream commercial use of TSV in the silicon chip industry. By the way that was reported in one of my very first blogs in PFTLE, the predecessor to IFTLE which ran for several years in the now defunct Semiconductor International magazine. At that time PFTLE predicted that the CMOS imaging chips would eventually be broken up into functions and stacked. Sony brought that concept to commercialization a few years ago. [ see IFTLE 172, “IFTLE 172 Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013” ]

TSMC InFO

What’s the inside info on InFO. Try as you might, despite the significant press it has received, you cannot point to a publication that clearly outlines the process flow for TSMC’s InFO package. I have been asked whether it is chips first or chips last and all I could answer was: “Good question.”

Well, sources in Asia have leaked the following process flow to me. Although I cannot guarantee this is the actual TSMC InFO process flow (until Doug Yu confirms it) I’ll none the less show it to you since it is a quite interesting flow. The answer to the question for this process flow is chips first or interconnect last. Die are placed face up, pillars are plated on die and then molded. Routng to the package BGA balls is through mold vias (TMV). The wafer is then polished down to reveal tops of Cu pillars and standard” RDL is processed up from there. Ability for finer features appears to come from more planar starting surfaces and better controls of photo processes. IFTLE would guess that warpage is the major problem for this process flow.

InFO

3D ASIP Conference 12 Years and Going Strong

As it has for the last decade, 3D ASIP will once again close out the packaging conference season with its mid December 3DIC focused meeting outside of SF.

The 12th annual 3D Architectures for Semiconductor Integration and Packaging, or 3D ASIP as it has become known, will be held December 15-17, 2015, at the Sofitel San Francisco Bay Hotel in Redwood City, Ca. It is the longest running conference on 3DIC focused on commercialization and infrastructure.

The conference general chair and program coordinator is Dr. Philip Garrou, Microelectronics Consultants of NC. The technical co-chairs this year will be Professor Mitsumasa Koyanagi, Tohoku University, and Dr. Rama Alapati, director of packaging product management, GLOBALFOUNDRIES.

Matt Lueck of RTI International and Herb Reiter of EDA2ASIC Consultants have developed two half-day tutorials focused on temporary bonding/debonding and interposer design respectively. Presenters from CEA-Leti, HD Micro, Dow, TOK, Brewer Science, SUSS MicroTec and TOK will discuss the current state of the art in bonding and debonding technologies. The interposer design program includes presentations from Mentor Graphics, Cadence Design Systems, Ansys, E-System Design, Zuke, and eSilicon.

“This year, 3D ASIP will honor two trailblazers in 3DIC, Peter Ramm, Fraunhofer EMFT and Professor Mitsumasa Koyanagi, Tohoku University. They will be honored for their early pioneering work in the 1990s that set the stage for what we today know as 3DIC. Following the award ceremony, each recipient will deliver a short presentation on his group’s early work in 3DIC.

Screen Shot 2015-11-16 at 6.02.36 AM

 

Plenary presentations will be delivered by Brandon Prior, Prismark, discussing the status of 2.5/3D and other high density technologies; Rozalia Beica, Yole Développement, comparing and contrasting the new 3D memory architectures; and DC Hu, Unimicron, reviewing the transformation of substrate technology.

Screen Shot 2015-11-16 at 6.02.45 AM

 

The nine invited sessions cover topics including: Memory Stacks become Reality, Products and Production in the 2.5/3D Infrastructure, Equipment and Metrology, High Density Packaging without TSV, and Heterogeneous Integration.

Key presentations will include Hynix, Micron, Tezzaron and Toshiba discussing their new 3D stacked memory products; Xilinx/SPIL, Amkor and TSMC discussing their non TSV high density solutions; AMD discussing the commercialization of Fiji graphics modules with HBM memory stacks. Dan Green of DARPA discussing their DAHI heterogeneous integration 3D platform and Sony discussing their new stacked image sensor technology.

For more information on the conference agenda, visit the conference website at www.3dasip.org.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…