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IFTLE 203 Apple Acquires LuxVue µ-assembly Technology

By Dr. Phil Garrou, Contributing Editor

Apple has acquired 24 tech companies in the last 18 months. Recently, Apple acquired LuxVue, a start-up focused on low power micro-LED displays. Although Apple has not disclosed any details of the acquisition, not even the purchase price, one can easily envision where micro LED displays could play a big part in Apples thrust into wearable electronics such as the i-watch. Reportedly the LuxVue display is 9 times brighter than both LED and LCD screens.  Such µ LED displays would be compatible with curved surfaces and would save power and thus increase battery life. Brighter, lower power displays could have applications in other Apple products and products such as Google glasses.

Little is known about the LuxVue technology other than the patents that have been issued. They have no web page and have made no public presentations that I can find. The do have several dozen patents many of which deal with transferring micro devices, which specifically for displays would be LED devices as small as 10 x 10 miron and placing them on 10 micron pitch.

Their preferred transfer device consists of a substrate with an arrangement of protruding mesas. Each mesa contains electrodes with a thin coating of dielectric. By providing a charge between the electrodes, an electrical field is created which electrostatically attracts the miniature chips or LEDs [for example, see USP 8333860 B1].

It is proposed that using this approach one can selectively choose to remove specific micro devices from a source substrate by applying voltage only to the projecting mesas corresponding to the positions of the device to be transferred.

In essence, this is massively parallel pick and place. We are all familiar with conventional pick-and-place assembly using vacuum collets and pin ejectors. For devices that are on the scale of 10 micron however, manipulation and accurate placement are significantly more difficult with today’s tools. This LuxVue “electrostatic chuck” mechanism is one way to deal with manipulation of such small devices.

If massively parallel pick-and-place sounds familiar, recall similar technology Semprius and more recently X-Celeprint have been developing.  These startups are based on the work of John Rogers at U. Ill. Which uses PDMS stamps rather than the more complex electrostatic chuck. [link 1] [link 2]

I have compared the two technologies in the figure below:

Xceleprint vs luxvue


I contacted Professor Rogers and X-Celeprint CTO Chris Bower, and they agreed that microassembly of such LEDs is indeed the sweet spot for X-Celeprint technology. They sent the images below which show some early examples of transparent and flexible devices using Micro-Transfer-Printed inorganic LEDs. At this point, they were just willing to say that this was an area “of active interest.”

Double printing the RGB LEDs allows circuit redundancy, so a bad LED or connection does not produce a bad pixel. This is the technique already in use by display manufacturers [link 1] and more recently 3DIC practitioners to insure that a bad TSV does not result in a failed chip [link 2].


As devices continue to get smaller, we can expect to see micro transfer technologies such as these take a more prominent role in their assembly.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 202 ConFab 2014: Novati, Lumileds; Chipworks; IEEE CPMT Packaging Panel

By Dr. Phil Garrou, Contributing Editor

Dave Anderson, CEO of Novati talked about “More-than-Moore, Advanced Packaging and Creating Game-Changing Innovation.” In keeping with the main theme expressed by IFTLE for several years, Anderson echoed, “Most companies can’t afford to continue to pursue Moore’s Law scaling” and offered “More-than-Moore” as a product customization route for the future.

Andrew Kim of Philips Lumileds updated attendees in “Trends in LED Manufacturing.” (As you may recall IFTLE and its incarcerated spokesman Lester Lightbulb are not strong supporter of LED replacement  of the incandescent bulb, i.e. see IFTLE Lester Lightbulb.)

Kim presented a “very simplified” process sequence for LEDs manufacturing. (“Wow that sure should be cheaper and better for the environment than a tungsten filament bulb.” – Lester) In addition, as we have shown before, the new light sources are not only the “electroluminescent emitter,” but a far more complicated circuit of PCB and components [see IFTLE 63 “Bidding Adieu to Lester the light bulb”]

Limileds 1


Kim sees the following options developing for substrate alternatives.

– Sapphire: currently dominant, current substrate cost for larger sizes

– Silicon: Manufacturing and performance

– GaN on GaN: Cost and value proposition

– SiC: Single LED user with captive source

Evidently the DOE game plan is still to reach $8 / bulb by the early 2020’s. (“Wow that will make it only 16X the cost of an incandescent bulb” – Lester)

lumileds 2


LEDs certainly offer new form factors for light and in the future will allow creation of devices that we are not today thinking about.  IFTLEs issue with LED lighting is with how it was sold to the consumer as a saver of power and a saver of cost. IFTLE arguments have been presented previously and can be found here [link].

By the way, we are now more than three years into our single bulb testing which was started in Aug 2011. The CFL was dead in < 10 months but the LED and the incandescent are still burning bright 3 years into the testing. Remember the incandescent cost me only 50 cents.

Fellow SST Blogger Dick James from Chipworks shared “Inside Today’s Systems & Chips: A Survey of the Past Year”. During their reverse engineering of the Apple iPhone 5s, Chipworks identified the CMOS image sensor as Sony’s  AW34 5399.

chipworks 1


IEEE CPMT Packaging Session


Bill Chen of ASE put together an Advanced Packaging panel to update ConFab attendees on the latest packaging advances.

packaging group


Garrou (IFTLE), Chen (ASE), Huemoeller (Amkor), Bezuk (Qualcomm) and Black (AMD)

The presentations of Amkor, Qualcomm and AMD have been reviewed recently by IFTLE [ see: “IFTLE 179 GaTech Interposer Conf: Amkor, GlobalFoundries”; “IFTLE 186 IMAPS Device Pkging Conf: Qualcomm, Prismark”; “IFTLE 188 IMAPS Device Packaging Conf Part 2: AMD, SCP”.

As part of my presentation, I looked at the status of a few of the 3DIC rumors that we have discussed on IFTLE, which didn’t come true and the current status of announced products including Hynix stacked memory, Microns HMC stacked memory and graphics modules from Nvidia. Memory is now happening, so hopefully the rest of the products will be coming soon.

Garrou 1


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 201 2014 ConFab: Global Foundries; IBM, G450C

By Dr. Phil Garrou, Contributing Editor

Yes, we have now passed numero 200 on what I shall self proclaim the #1 informational blog for 3DIC and advanced packaging on the internet! Again, my thanks to Pete Singer for continued support.


Now that you have taken a look at us, let’s take a look at some of the presentations at this year’s ConFab.  Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry.

Emerging applications will include:


1. Computer vision

2. Augmented reality

3. Concurrent application and modem operation

4. Gesture recognition

5. Medical applications

6. Contextual awareness

7. HD video and games

8. 3D camera and 3D display

9. Multiple concurrent displays

10. Multiple concurrent audio and video CODECS

Kengeri concludes that “the semiconductor industry is challenged on the Economics of technology scaling.” Cost of building a new leading edge fab continues to escalate while capex / wafer is increasing at a rate of 38%.

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In addition, ROI is delayed due to increased investment requirements and longer time to volume.

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GF also offered some interesting insights into the industry landscape.

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Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Patton confirmed that scaling beyond 22nm will require alternative device structures and new material innovations.


Click to enlarge.

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Beyond silicon, packaging and board innovations are required to continue to miniaturize. IBM points to interposers and die stacking to do this.


Click to enlarge.

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Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

G450C is a public/private program based at the College of Nanoscale Science & Engineering in Albany with goals of :

-  Driving effective industry 450mm development

-  Focus on process & equipment development

Members include Intel and the major foundry players and for now IBM (rumors of their acquisition by GF remain rampant).

G450 1

The consortium sees the following changes coming between 300mm and 450mm.

G450 2

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…


IFTLE 200 Semicon West Suss Workshop: Laser Debonding and KLA Tencor platform for WLP inspection

By Dr. Phil Garrou, Contributing Editor

The 5th annual Suss Technology Forum was recently held at SEMICON West focused on trends in 3DIC and WLP.

Stephan Luetter compared the various temp bonding technologies and their current focus on excimer laser assisted release.   The EDL-300 is their eximer laser debond module which rasters the wafer with a 12x 4mm laser beam. Carrier is lifted of with a vacuum gripper with close to zero mechanical lift-off force. A requirement for laser assisted debonding, is that it uses a glass carrier wafer to allow transmission of the laser light. Suss has concluded that the new materials and simpler process flows allow cost of equipment reduction in the range of 1.5-3X.

Suss temp 1


The Suss open platform program supports 10 materials suppliers and 4 laser assisted RT debonding processes (including 3M, Brewer, Dow and HD Micro).

suss temp 2


Kim Arnold of Brewer introduced their 3rd generation temporary bonding solution BrewerBond which makes use of a laser assisted room temperature debond process.  Brewer who has been supporting the 3DIC infrastructure for a decade has introduced several product families to meet their customer needs. Each generation has increased throughput and thermal stability better allowing backside processing at higher temperatures.

brewer 1


The BrewerBond process makes use of a light sensitive layer which is decomposed during debonding with a 308nm excimer laser. Arnold indicated that development of a gen 4 product with higher throughput and higher thermal stability is underway.

Mark Oliver of Dow Chemical discussed their laser bond release process. Laser debonding at 308nm is shown below. The adhesive ends up on the device wafer side and is removed with a simple tape peel.

dow 1


Dow also proposed the use of temp bonding to deal with warping in technologies such as fan out WLP.

dow 2


Sood of KLA Tencor announced their CIRCL (Concurrent Inspection and Review Cluster)  platform to address inspection requirements for advanced WLP.

KLA Tencor 1


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 199 Omnivision Roadmaps 3D stacking for CMOS Image Sensors; IC Insights Details Trends Shaping the IC Industry

By Dr. Phil Garrou, Contributing Editor


Since Toshiba started using backside TSV in 2008 we have been anticipating  stacking of separate functions in true 3DIC fashion. Last summer, Sony announced such a structure.  [link 1]

Recently, at the  image sensors conference in London, Dr. Howard Rhodes, CTO of Omnivision, gave an keynote entitled “The Future of CMOS Imaging” where he expounded on the advantages of stacking and the separation of the imaging function from the logic function.

fig 1



Of special interest are Rhodes comments on “stacked CIS” which he calls “replacing the BSI Si substrate with logic.” Their roadmap shows Omnivision moving from wafer bonding with simple oxide bonding to “hybrid bond stacking with simultaneous bonding of oxide and Cu contacts to 3 wafer stacking where sensors, ISP and memory are fabricated separately and stacked.

fig 2


Longtime readers of IFTLE will recognize that Gen 1 “Oxide-oxide” bonding is the technology Sony licensed from Ziptronix in 2011 [link].

“Hybrid bonding” is the term commonly used to describe the patented Ziptronix DBI process where oxide and copper (or other metal) bonding occurs simultaneously [link], so one should expect to see more Ziptronix licensing in the future.

IFTLE would guess that there will be further licensing in Ziptronix future.

IC Insights

At the recent SST ConFab in Las Vegas Bill McClean shared his annual report on  “Major trends shaping the future IC Industry.” IC insights reports that recent growth in the IC industry has been mainly in memory.

fig 3


For the first time in 2013, communication surpassed computers in terms of market share.

Fabless sales are now 29% of total IC sales with the US is holding its ~70% market share of fabless market sales which it has had since 2010.

fig 4


The bulk of capex spending is being done by the major players, i.e. the ones who appear set to move forward to lower nodes (1-7 in the chart below).

fig 5


Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.

fig 6


A look at capital spending by region shows Japan and Europe falling for behind with a combined sub 10%.

fig 7


r all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 198 Intel & Micron HMC 3D Stacked memory; GS Nanotech announces 3DIC Plans; STATSChipPAC suitors named

We have all been waiting a long time to see the following headline:

Intel to Commercialize HMC  Stacked Memory – Knights Landing

Last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. [link] It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core. It will support for up to 384 GB of on board DDR4 RAM  and 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth. It will be the first Intel processor to use this new high performance on package memory.

Intel 1

The Micron 3D stacked  memory which we have know as the hybrid memory cube for several years is being called “multichannel memory or MCDRAM. Micron reports that having such memory in the CPU package is expected to deliver 5X the sustained memory bandwidth versus GDDR5 with one-third the energy per bit in half the footprint.

micron 4

Knights Landing is expected to be deployed in various high performance computing solutions such a as the Cray “Cori” at  National Energy Research Scientific Computing (NERSC) Center.

Long time IFTLE readers recall that Intel was involved from the beginning with the concept of HMC [ see IFTLE 74, “The Memory Cube Consortium” ] and in fact shared a glimpse of the memory cube technology at their developers forum in June of 2011.[link]

fig 5 IDF 2011

Recall Micron contracted IBM to manufacture the logic interface layer [see  IFTLE 95, “3DIC – Time Flies When You’re Having Fun; Further Details on the Micron HMC….”]

So it was interesting to see the logic layer on display recently in the IBM booth at ECTC. I’m pretty sure this is it (before the memory layers are attached).

IBM logic layer 2

While the excitement level around this announcement will be high, we should all understand that as described this is a high end HPC application, not the high volume driver that the 3DIC world has been awaiting. The question for intel is will Intel use this as a platform to compete with nVidia and AMD/ATI on graphics, or will this be just a niche HPC product?

We should also note that although Intel has numerous patents in the area, there is no current indication that this will be a 2.5D solution. Intel has thus far only said “it will be high bandwidth.”

GS Nanotech

Anyone else surprised by the recent announcement that GS Nanotech (Kaliningrad, Russia) “plans to launch mass assembly of 3D stacked TSV microcircuits in the next few years”? I must admit I had never heard of them. A quick look at their web page indicates that they manufacture chips for General satellite set-top-boxes and have ST Micro, Nanium, Toshiba and Winbond listed as customers.

FYI – we are in the process of inviting them to speak at the RTI ASIP conference in December to see exactly what they have and what their plans are.

Updating STATSChipPAC

From our friends at Digitimes: “STATS ChipPAC, the world’s fourth-largest IC backend service company, has put itself up for sale with ASE, Changjiang Electronics Technology, Samsung and Huatian Technology (Xian) likely to compete for the sale… STATS ChipPAC has been holding talks with potential buyers since mid-May, with ASE and Changjiang being the first two contenders… Changjiang aims to enhance its manufacturing technology and patent portfolio, and to ramp up total capacity by acquiring STATS ChipPAC, noted the sources… ASE’s bid for STATS ChipPac is more likely to prevent other potential competitors from taking over STATS ChipPAC to build up capacity against ASE…” Samsung, Huatian, Foxconn, UTAC and GlobalFoundries have also been rumored to be potential acquirers. [link]

For all the latest on 3DIC and other advanced packaging solutions, stay linked to IFTLE…

IFTLE 197 IBM / GF; 3D Integration Handbook Volume 3; 2014 iTherm

IBM/GF …the Saga Continues

Although both IBM and GF are refusing to address “rumors and speculation,” the rumors and speculation persist that the sale of IBMs semiconductor business to GlobalFoundries is imminent. The latest to comment on the expected deal is Businessweek / Bloomberg [link]

Most experts feel that GlobalFoundries is primarily interested in acquiring IBM’s engineers and intellectual property rather than the manufacturing facilities (200mm facility in Burlington VT and 300mm line in East Fishkill NY) since GF has its own state of the at capacity. GF would  act as a supplier for IBM’s semiconductor needs.

Reading the Vermont Free Press articles on the subject, it is clear that IBM employees expect GF to mothball the facility. For those of you wondering why there is a semiconductor facility in VT at all I offer you the following interesting comment “IBM opened its plant in Essex Junction in 1957, largely because the late Thomas Watson Jr., former IBM chairman and CEO, liked to ski.”

3D Integration Handbook

bookMitsumasa Koyanagi, Peter Ramm and I have finished our work on Volume 3 of the 3D Integration Handbook and it is now available for sale at Wiley VCH, Amazon or you favorite textbook retailer.

Vol 3 focuses on 3D Process technology, updating the original two volumes in 2008 with all new chapters on all the relevant process steps. We have gathered many of the worlds experts to give you their insights on 2.5 / 3DIC processing and an especially strong chapter on metrology from the staff at Sematech. The bond/debond section includes chapters by Brewer, EVG, Suss, TOK , 3M and RTI. Most areas are covered by at least two different authors to give the reader a more complete perspective of what is possible. Of special interest should be the chapters “Bonding and Assembly at TSMC” by Doug Yu, “Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices” and “Implications of Stress/Strain and Metal Contamination on Thinned Die” by Kangwook Lee.

Paul Franzon of NC State, Eric Jan Marinissen and Muhannad Bakir will be editing Volume 4 which will focus on Design, Test and Thermal. We hope these volumes prove to be of value to the community.

2014 iTherm

iTherm is the Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. The 2014 iTherm was held concurrent with the ECTC in Orlando, FL. This years General Chair was Mehdi Basheghi of Stanford and program chair was Madhusudan of Google. Attendance this year was up 50% to ~ 400.


Kumari and co-workers at HP addressed “Air Cooling Limits of 3D Stacked Logic Processor and Memory Dies.” Their goal was to determine how many memory die can be integrated into a package with logic before exceeding the temp limitations of the memory die. Modeling was done for 10nm technology with 24 cores as shown below. Core power is varied from 1.5 to 3 W (red cores). Sacked memory are 0.5W DRAM.

HP 1

Thermal results are shown below.

HP 2


Oprins and Beyne discussed the “Thermal Modeling of the Impact of 3D Interposer Materials and Thickness on Thermal Performance and Die-to-die Thermal Coupling.” For the test vehicle shown, they observe reducing the thermal conductivity from Si to glass results in an increase in the logic temperature and consequently a lower maximum logic power. The memory temperature at the other hand decreases for decreasing values of the conductivity since the in plane thermal coupling is reduced. This results in an increase of the allowable logic temperature. If the memory heating is included, an increase of the memory temperature can be observed for very low conductivity values.


Most applications for interposers combine high power components (logic) and temperature sensitive components (memory). Since the components are thermally coupled in the package, the logic power will be limited by either the temperature limit of the logic or memory, whichever is reached first. This means there is a trade-off between the logic self-heating and the thermal coupling which are impacted differently by the interposer material and thickness choice. It is shown that the Si interposer has a better thermal performance than the glass interposer in case only the logic temperature limit is taken into account and that the Si interposer package thermally outperforms the single chip package, the package-on-package configuration (PoP) and the 3D stacked configuration. In case the memory temperature limit and self-heating are taken into account as well, the glass interposer package has a better thermal performance for cases where the memory temperature limit memory is sufficiently lower than logic temperature limit.

For all the latest in 3DIC integration and other advanced packaging, stay linked to IFTLE…

IFTLE 196 2014 Symp on Polymers: Fraunhoffer IZM; ASE, Hitachi Chem

The 16th biennial Symposium on Polymers was held this May in Wilmington DE. Keynote speakers included Steve Bezuk, Qualcomm, James Lee, Strategic Foresight Investments, John Hunt, ASE and Mark Poliks SUNY Binghamton.

Frauhhoffer IZM

Michael Toepper of Fraunhoffer IZM continued a theme we saw from Ted Tessier at the IMAPS Device meeting in March [see “IFTLE 189, “IMAPS DPC part 3: FCI; GF/Amkor; Corning; Namics”] namely photo processing vs laser ablation for WLP.

In the 1990s, photo materials won out over dry etch materials because of lower COO. The processes are compared below.


The question now is  – Can we do even better with laser processing ? Laser is compared to photo processing below:


High absorption of UV radiation by polymers and poor thermal conductivity of the polymer result in etch depths per pulse in the 100 nm range with little thermal diffusion.  Scanning ablating allows for ablation of areas of 50 x 50mm at a time.

Materials suitable for Excimer ablation include:


Much finer vias can be produced with laser ablation, i.e 5um vias in 5um dielectric. Also since the ablation is done after cure, no polymer shrinkage occurs after the via is formed. A low cost polymeric cover layer is applied to catch debris during processing and is dissolved away after ablation.

With laser ablation non photo polymers which exhibit better thermal, mechanical and electrical characteristics than photo polymers can be used and such materials can use high loadings of nano-fillers which cannot be made photo-imageable.


John Hunt of ASE detailed “Polymer Innovations for Advanced Packaging Applications.”  John pointed out that every component and interface in the package must be carefully engineered. The variety of interfaces are shown below.


Multiple disciplines are necessary to develop materials for advanced packaging as shown below for underfills:


Many polymers are required for a single application for instance for 2.5D interposers:

blurb 2

There is still significant room for improvement as shown below:

blurb 3

Hitachi Chemical / HD Microsystems

Daisaku Matsukawa of Hitachi Chemical described their attempts to produce a low temp curable, positive tone photo PI. For many years PI has been known to have excellent mechanical properties but very high curing temperatures. In the 1990s, curing temperatures of the most popular grades were 350˚C+ .

Crosslinking a copolymer of preimidized PI and a phenolic containing moiety (see below) resulted in low temp cure PIs.

HD 1

While x-linking with aliphatic and aromatic di-epoxides resulted in poor films, they found that heterocyclic epoxides resulted in materials with good PCT resistance and adhesion at low cure temperatures, i.e. 150 – 200˚C. Material properties are shown below:

HD 2

IFTLE notes: while the curing temperature has gone down into todays preferred range of less than 200˚C the mechanical properties, once the main PI benefit, now look a lot like BCB and the Tg of the material now more resembles low Tg epoxy than PI or BCB. It will be interesting to see if such a material gains acceptance in the marketplace.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 195 STATS in Play ?…What Consolidation means to you… Micron and TSMC for 3DIC?

By Dr. Phil Garrou, Contributing Editor

STATS Status?

The hottest rumor at the 2014 ECTC in Orlando was that STATSChipPAC (SCP) was “in play” (about to be acquired). One version of the rumor had at least 3 bids on the company including GlobalFoundries (IFTLE finds it hard to imaging GF could swallow both IBM and SCP at the same time), ASE and “a group of un-named mainland China companies.”  Inquiries to SCP contacts substantiated the rumors although they had no knowledge of the details.

Sure enough the Wall Street Journal on May 16th indicated that SCP was “considering an offer for all its shares.”

When I went straight to the source and asked for a response, SCP sent me a copy of the response they sent to the Singapore stock exchange (the rumors evidently caused the stock shares to jump.

STATS ChipPAC Ltd (the “Company”) refers to the questions from Singapore Exchange

Securities Trading Limited (the “SGX-ST”) dated 15 May 2014, regarding the unusual price and volume movements in the shares of the Company.

 The Company has received a non-binding expression of interest from a third party, with a view to a possible acquisition of all the shares in the Company subject to a number of conditions. The Company regularly conducts strategic reviews of, and considers various proposals in relation to, its business and operations with a view to maximizing shareholder value. The Company is accordingly considering this approach. There is no assurance that this approach will result in any definitive agreement or transaction. Save as set out above, the Company is not aware of any other possible explanation for the trading and the Company confirms its compliance with the listing rules, in particular, Rule 703 of the SGXST Listing Manual.


The Company will make an appropriate announcement in the event that there are any material developments on this matter. Shareholders of the Company and investors are therefore advised to exercise caution when dealing in shares in and other securities of the Company. “


IFTLE has written many blogs detailing how we are in a period of consolidation and how Economics 101 tells us that there is no way to stop it. Let’s take a look at what this really means. I watched this occur in the chemical industry, and I am now watching it again in the electronics industry. For those of you that are business majors, I forgive you if you skip this and go on to something else. For those of you that are “techies” working for IDMs, foundries, material or equipment suppliers, pay attention please because this concerns you.

The 4 stages of a Business Cycle (extracted from GK Deans “The Consolidation Curve,” Harvard Business Rev., 2002.):


Stage 1: In stage 1, the combined market share of the three largest companies is between 10 percent and 30 percent. Companies in stage 1 industries aggressively defend their first-in advantage by building scale, creating a global footprint and establishing barriers to entry, i.e. protecting proprietary technology or ideas. Stage 1 companies focus more on revenue than profit, working to amass market share.

Stage 2: Stage 2 is all about scaling. Major players begin to emerge, buying up competitors.  The top three players in a stage 2 industry will own 15 percent – 45 percent of their market, as the industry consolidates. The companies that reach stage 3 must be among the first players in the industry to capture the most important markets and expand their global reach.

Stage 3: Stage 3 companies focus on expanding core business and continuing to aggressively outgrow the competition. The top three industry players will control between 35 percent and 70 percent of the market with five to 12 major players remaining. This is a period of large-scale consolidation plays. Companies in stage 3 industries focus on profitability and pare weak businesses units. The well-entrenched in this phase will attack underperformers. Recognizing start-up competitors early on allows market leaders to decide whether to crush or acquire them. Stage 3 companies should also identify other major players that will likely survive into the next, and final, stage and avoid all-out assaults on them which could leave both players injured.

Stage 4: In stage 4, the top three companies claim as much as 70 percent to 90 percent of the market. Large companies may form alliances with their peers because growth is now more challenging. Companies in stage 4 must defend their leading positions. They must be alert to the danger of being lulled into complacency by their own dominance.

Stage 4 companies must create growth by spinning off new businesses or buying into aligned fields to broaden their market presence.

Let’s take a look at a few examples to bring this closer to home. First, let’s look at DRAM memory consolidation.  In 1980, there were 41 listed suppliers [1] whereas after the recent acquisition of Elpida by Micron we are left with 3 suppliers having > 90 percent of the market [2].








[1] M Durcan, “Leveraging Capital Efficiency for Global Leadership”, Semi ISS , 2011

[2] C Chan, “DRAM Industry Outlook Rational Competition, not a Cartel”, Semi Taiwan, Sept 2013.

How many foundries do we expect to see moving past 22nm? TSMC, GF, Samsung and maybe. That’s it.

Some front-end IC equipment markets have recently been examined. [3] Each color below represents a different vendor and the dark grey area represents multiple small suppliers. Many of the market segments already have one to three suppliers with combined > 80 percent market share; several segments have 2 suppliers with > 90 percent market share and two segments have 1 supplier with > 75 percent share. All signs of a mature market.

Lentz front end












So, the front end is nearing full consolidation. With 450mm stalled and scaling coming to an end this means fewer and fewer fabs moving forward with the latest equipment. What’s a front-end equipment supplier to do?

“Stage 4 companies must create growth by buying into aligned fields to broaden their market presence”

We have all watched as Applied Materials has made their move into the backend equipment sector and even tried to spread their wings a little further into the PV market (ouch!)

Will anyone be surprised as we see LAM and KLA Tencor attempting to do the same? Since the front end suppliers have the deeper pockets IFTLE has expected for a long time that they will eventually buy out back end suppliers as consolidation continues.

Lastly, let’s look at some breakouts of market share in the back end equipment space. Below I am showing a Yole look at equipment market shares in 2011 with names and percentages removed (sorry but they sell this info). We can see consolidation has already begun there as well. As stated above IFTLE expects many of these players to be bought out by the front end players over the next few years.

back end Yole











So whether we find out next week that SCP has been acquired, or not, my message is the same: CONSOLIDATION is underway and will likely affect you and your current employer.

Micron and TSMC?

Josephine Lien at Digitimes is reporting that “TSMC reportedly to tie up with Micron to develop 3D ICs” According to these reports, TSC will integrate Micron’s hybrid memory cube-based DRAM chips with TSMC’s logic chips “through TSV technology.” Lien continues “A successful development of the chip stack technology between DRAM and logic chips will enable TSMC to extend this technology to integrate mobile application processors and DRAM chips, and therefore will help TSMC further expand its client base.”

During the summer months ahead, IFTLE will be giving you full coverage of:

2014 Symposium on Polymers ; 2014 ECTC; 2014 iTherm; 2014 Confab and Semicon West and more…

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 194 More on IBM / GF ; SEMI Singapore part 3: Nanium, Fujitsu, EVG

By Dr. Phil Garrou, Contributing Editor

The Latest on IBM and GF

Craig Wolf of the  Poughkeepsie Journal reports confirmation from Global Foundries that 150 to 200 IBM’ers will move from IBM’s East Fishkill chip plant to GlobalFoundries’ plant in upstate Saratoga County. GF has confirmed a contract with IBM in which “technical workers” based at the East Fishkill will work for eight months at GF’s Fab8 chip plant. IBM refused comment on the deal.

While one cannot conclude that his confirms the imminent sale of the IBM Semiconductor division to GF (which IFTLE has predicted for several years) , it certainly indicates that things are slow in the IBM plant.

Continuing our look at the recent 2.5/3DIC Forum at SEMI Singapore.


Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology and that eWLB offers an alternative with sufficient capability for many applications in high volume at reasonable cost.

PoP structures such as those shown below are being readied for portable applications where less than 1mm thickness is required.

Nanium 1

Nanium is working with AT&S to develop technology for reconstitution in laminate vs traditional eWLB which forms a wafer out of molding compound.

nanium 2


Fujitsu presented on “Highly reliable chip to chip Cu wiring technologies for 3D/2.5D interconnection.” Their premise is that as interconnect gets finer and finer traces will need full barrier layer protection similar to what is done on chip with dual damascene, especially when the interposer is a high density PCB. This is shown by HAST failures as shown below.

Fujitsu 1

Their proposed failure mechanism is:

- Halide ions and organic acid accumulate around the anode Cu

- Anode Cu dissolves and Cu ions are formed

- Cu ions diffuse and drift into insulating materials

- Cu dendrite growth on cathode surface triggers dielectric breakdown

fujitsu 2

A barrier layer is needed to prevent Cu corrosion. SiN failure is due to cracking due to the CTE mismatch.

fujitsu 3


Thorsten Matthias reviewed EVG solutions for interposer manufacturing.


Of special interest was his review of the work of GaTech and Zeon looking at the insulation of interposer TSVs with polymers instead of oxide. Oxide liner is usually less than 1μm thickness and the cost scales with thickness whereas polymer liners can be much thicker and the cost is independent of thickness. The GaTech simulations show the polymer liners will give superior electrical performance. FEA shows the polymer liners should show a Reduction of thermal induced mechanical stress.

EVG proposes spray coating as the technique to get the TSV insulated with polymer as shown below. EVG wafers were processed on an EVG NanoSpray coater with JSR Micro WPR 5100 positive resist and BCB for polymer insulation.

IFTLE notes that cross sections were shown for 40um dia TSV but not for the more common 10 x 100um TSV.


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