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IFTLE 176 2013 IEDM; Micron, TSMC, Tohoku Univ., NC State, ASET

By Phil Garrou, Contributing Editor

The 2013 IEEE IEDM was held in WDC the 2nd week of Dec. Let’s take a look at some of the key 3DIC presentations there.

Micron

Chamdrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking. He does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.

micron

Micron proposes that “…3D integration faces several equipment and fundamental technology challenges. Bonding dicing and packaging equipment have not evolved to the same level of control capability as front end equipment technologies.” In terms of fundamental technologies they see challenges in thin wafer handling, thermal budget management and stress constraints.

New techniques will be required to test the silicon interposers with TSV and 3D devices keeping  test costs low. Ability of probe technology to handle finer pitch TSV tips, eliminate probe created scrub mark defects, and handling of thinned wafers are all viewed as significant challenges.

3D stacking also introduces intra die defects due to several processing steps, which needs to be detected and understood. Thinned die and multiple materials with different thermal expansion coefficients also create thermo-mechanical problems that can lead to test and probe issues.

TSMC

Doug Yu and the TSMC packaging group described the integration of Rf chip and array antennas using FO-WLP packaging technology.

Low dielectric constant and thick substrate are two essential factors for a wide-bandwidth patch antenna. The band for 60 GHz system in US is from 57-64 GHz, which can be achieved with mold cmpd. (MC) dielecric constant of 4 and MC thickness of MC, h1, is chosen to be 300 μm

LTCC and PCB substrate are currently used for integration of mm-wave antenna with RF chip but there are power consumption issues. The high power dissipation results from interconnect losses from chip to antenna through bumps or balls. “Antenna-on-chip” is other proposed solution to reduce the signal loss, but silicon is lossy and degrades the antenna efficiency.

The TSMC antenna structure is depicted in the figure below. It consists of two RDLs sandwiching mold compound. One is for patch radiator with the size of w × l = 890 × 1020 μm2 on the top of MC and the other one is for feeding structure embedded in the polymer on the bottom of MC as shown in the figure.

TSMC 1

This FO-WLP array antenna integrated technology has been approved for millimeter wave system applications. High gain array antennas of 14.7 dBi, low-loss interconnects of 0.7 dB and small form factor of 10 × 10 × 0.5 mm3 can be achieved with the technology. So called “InFO-WLP” is reported to be an excellent technology for system scaling of low power millimeter wave applications on high-data-rate wireless communication.

Comparison of power savings, parasitics and system performance/size is shown below.

TSMC 2

NC State

Paul Franzon presented on applications and design styles for 3DIC. When comparing 2.5D interposers vs 3DIC stacking . While 3DIC technology offers a substantial advantage in interconnect power efficiency and bandwidth density (effective wiring density * bit rate), their thermal flux is higher, complicating cooling. On the other hand, interposers add more cost than just TSV processing, which will keep them out of lower cost markets such as mobile. Two big advantages for interposers are that they reduce the need for power/ground feedthroughs

and physical standards. This was a significant barrier to the adoption of Wide IO but can be overcome through adoption of appropriate standards.

franzon 1

ASET

 

Aoki of Hitachi and collegues at ASET described activities on IC stacking using vias last / backside. Compared with the “via-middle”, the “backside-via-last TSV” can reduce process cost because TSV revealing is unnecessary. The via-last TSV process has two main advantages: first, modification of the BEOL process is unnecessary and, second, reliability concerns such as the “copper extrusion (pop-up) problem” do not arise.

ASET studied a process flow using the thinning after bonding approach. This is the process used by Tezzaron. With this method, temporary bonding is not necessary, so process cost should be reduced.

The process flow of thinning-after bonding is shown below . First, copper bumps embedded with polymer are formed on three wafers. Co-planarization of the copper/polymer surface by CMP is used to form a flat bonding surface. The step height between the copper bump and polymer was kept to below 50 nm across the entire wafer surfaces. The wafers (“LSI-wafer 1” and “Si-IP”) are then subjected to face-to-face (F2F) bonding.  Copper-copper bonding was achieved by applying hydrogen-radical cleaning. Next, the bonded wafer is subjected to wafer thinning and backside-via-last TSV processes Total-thickness variation (TTV) of the thinned wafer was kept to around 1.4 μm. A backside-via-last TSV was connected to copper/low-k interconnects. The diameter and length of the TSV were respectively 7 and 25 μm. After that the backside-via-last TSV processes, the bottom wafer “LSI wafer 2” is directly bonded to the previously bonded wafers in back-to-face (B2F) configuration. A three-layer-stacked CMOS wafer was successfully fabricated by the above-described processes.

ASET 1

To maximize interconnect resources, contact of the TSVs with the copper/low-k interconnects should be restricted to the lowest interconnect level possible. Cross-sectional SEM images of the stack is shown below.

ASET 2

Fabricated  devices exhibit high TSV yield of at least 99.2% and low TSV capacitance (about 40 fF). The transmission performance of the TSVs is 15 Tbps/W. Copper/low-k damage is reportedly negligible after via-last TSV formation. TSV-contact wiring needs only two interconnect levels. The estimated KOZ is up to 2 μm from a TSV because of low silicon stress (less than 50 MPa).

Tohku Univ.

Koyanagi’s group at Tohoku Univ reported on “Reliability Issues Related to TSVs.

 Mechanical Stress Induced by TSVs

It is known that a compressive stress is induced in the Si substrate next to Cu-TSV. Mechanical stresses decrease as the TSV size decreases whereas they increase as the TSV spacing decreases.

Cu Pop-up from TSVs

Cu extrusion (pop-up) occurs at Cu-TSV surface when Cu-TSVs are annealed at higher temperature. Cu extrusion increases as the TSV size increases and the annealing temperature increases.

Cu Diffusion from TSVs

It is very important in order to suppress Cu diffusion from TSVs that a barrier metal layer is uniformly formed with a high step-coverage within Si trenches before Cu electroplating for Cu-TSV formation. Step-coverage of barrier metal depends on the size and aspect ratio of Si trench.

Minority carrier lifetime was seriously degraded by Cu diffusion from Cu TSVs as the blocking property of barrier layer in TSV is not sufficient.

Reliability Issues in Thinned Wafer

Cu diffusion from backside surface of the surface of Si substrate is more significantly influenced

as the Si thickness is reduced. A dry polish (DP) treatment produced a superior extrinsic gettering (EG) layer to Cu diffusion at the backside.

DRAM Retention Degradation by Si Thinning

The retention characteristics of DRAM cell are degraded depending on the reduction of the chip thickness. The retention time of DRAM cell in the 20-μm thick chip is dramatically shorted by approximately 40% compared to the 50-μm thick chip.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 176 2013 IEDM; Micron, TSMC, Tohoku Univ., NC State, ASET

The 2013 IEEE IEDM was held in WDC the 2nd week of Dec. Let’s take a look at some of the key 3DIC presentations there.

Micron

Chamdrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking. He does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.

micron

Micron proposes that “…3D integration faces several equipment and fundamental technology challenges. Bonding dicing and packaging equipment have not evolved to the same level of control capability as front end equipment technologies.” In terms of fundamental technologies they see challenges in thin wafer handling, thermal budget management and stress constraints.

New techniques will be required to test the silicon interposers with TSV and 3D devices keeping  test costs low. Ability of probe technology to handle finer pitch TSV tips, eliminate probe created scrub mark defects, and handling of thinned wafers are all viewed as significant challenges.

3D stacking also introduces intra die defects due to several processing steps, which needs to be detected and understood. Thinned die and multiple materials with different thermal expansion coefficients also create thermo-mechanical problems that can lead to test and probe issues.

TSMC

Doug Yu and the TSMC packaging group described the integration of Rf chip and array antennas using FO-WLP packaging technology.

Low dielectric constant and thick substrate are two essential factors for a wide-bandwidth patch antenna. The band for 60GHz system in US is from 57-64GHz, which can be achieved with mold cmpd. (MC) dielecric constant of 4 and MC thickness of MC, h1, is chosen to be 300μm

LTCC and PCB substrate are currently used for integration of mm-wave antenna with RF chip but there are power consumption issues. The high power dissipation results from interconnect losses from chip to antenna through bumps or balls. “Antenna-on-chip” is other proposed solution to reduce the signal loss, but silicon is lossy and degrades the antenna efficiency.

The TSMC antenna structure is depicted in the figure below. It consists of two RDLs sandwiching mold compound. One is for patch radiator with the size of w × l = 890 × 1020 μm2 on the top of MC and the other one is for feeding structure embedded in the polymer on the bottom of MC as shown in the figure.

TSMC 1

This FO-WLP array antenna integrated technology has been approved for millimeter wave system applications. High gain array antennas of 14.7 dBi, low-loss interconnects of 0.7 dB and small form factor of 10 × 10 × 0.5 mm3 can be achieved with the technology. So called “InFO-WLP” is reported to be an excellent technology for system scaling of low power millimeter wave applications on high-data-rate wireless communication.

Comparison of power savings, parasitics and system performance/size is shown below.

TSMC 2

NC State

Paul Franzon presented on applications and design styles for 3DIC. When comparing 2.5D interposers vs 3DIC stacking . While 3DIC technology offers a substantial advantage in interconnect power efficiency and bandwidth density (effective wiring density * bit rate), their thermal flux is higher, complicating cooling. On the other hand, interposers add more cost than just TSV processing, which will keep them out of lower cost markets such as mobile. Two big advantages for interposers are that they reduce the need for power/ground feedthroughs and physical standards. This was a significant barrier to the adoption of Wide IO but can be overcome through adoption of appropriate standards.

franzon 1

ASET

Aoki of Hitachi and collegues at ASET described activities on IC stacking using vias last / backside. Compared with the “via-middle,” the “backside-via-last TSV” can reduce process cost because TSV revealing is unnecessary. The via-last TSV process has two main advantages: first, modification of the BEOL process is unnecessary and, second, reliability concerns such as the “copper extrusion (pop-up) problem” do not arise.

ASET studied a process flow using the thinning after bonding approach. This is the process used by Tezzaron. With this method, temporary bonding is not necessary, so process cost should be reduced.

The process flow of thinning-after bonding is shown below. First, copper bumps embedded with polymer are formed on three wafers. Co-planarization of the copper/polymer surface by CMP is used to form a flat bonding surface. The step height between the copper bump and polymer was kept to below 50 nm across the entire wafer surfaces. The wafers (“LSI-wafer 1” and “Si-IP”) are then subjected to face-to-face (F2F) bonding.  Copper-copper bonding was achieved by applying hydrogen-radical cleaning. Next, the bonded wafer is subjected to wafer thinning and backside-via-last TSV processes Total-thickness variation (TTV) of the thinned wafer was kept to around 1.4μm. A backside-via-last TSV was connected to copper/low-k interconnects. The diameter and length of the TSV were respectively 7 and 25μm. After that the backside-via-last TSV processes, the bottom wafer “LSI wafer 2” is directly bonded to the previously bonded wafers in back-to-face (B2F) configuration. A three-layer-stacked CMOS wafer was successfully fabricated by the above-described processes.

ASET 1

To maximize interconnect resources, contact of the TSVs with the copper/low-k interconnects should be restricted to the lowest interconnect level possible. Cross-sectional SEM images of the stack is shown below.ASET 2

Fabricated devices exhibit high TSV yield of at least 99.2% and low TSV capacitance (about 40 fF). The transmission performance of the TSVs is 15 Tbps/W. Copper/low-k damage is reportedly negligible after via-last TSV formation. TSV-contact wiring needs only two

interconnect levels. The estimated KOZ is up to 2 μm from a TSV because of low silicon stress (less than 50 MPa).

Tohku Univ.

Koyanagi’s group at Tohoku Univ reported on “Reliability Issues Related to TSVs

 Mechanical Stress Induced by TSVs

It is known that a compressive stress is induced in the Si substrate next to Cu-TSV. Mechanical stresses decrease as the TSV size decreases whereas they increase as the TSV spacing decreases.

Cu Pop-up from TSVs

Cu extrusion (pop-up) occurs at Cu-TSV surface when Cu-TSVs are annealed at higher temperature. Cu extrusion increases as the TSV size increases and the annealing temperature increases.

Cu Diffusion from TSVs

It is very important in order to suppress Cu diffusion from TSVs that a barrier metal layer is uniformly formed with a high step-coverage within Si trenches before Cu electroplating for Cu-TSV formation. Step-coverage of barrier metal depends on the size and aspect ratio of Si trench.

Minority carrier lifetime was seriously degraded by Cu diffusion from Cu TSVs as the blocking property of barrier layer in TSV is not sufficient.

Reliability Issues in Thinned Wafer

Cu diffusion from backside surface of the surface of Si substrate is more significantly influenced

as the Si thickness is reduced. A dry polish (DP) treatment produced a superior extrinsic gettering (EG) layer to Cu diffusion at the backside.

DRAM Retention Degradation by Si Thinning

The retention characteristics of DRAM cell are degraded depending on the reduction of the chip thickness. The retention time of DRAM cell in the 20-μm thick chip is dramatically shorted by approximately 40% compared to the 50-μm thick chip.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 175 2013 IWLPC; 450mm on Hold?

First things first:

A message from Hannah (9) and Madeline (5):

H&M

2013 IWLPC

The 2013 IWLPC Conference was held in San Jose CA this past fall. Lets look at a few of the key packaging papers.

Rudolph Technologies

Klaus Ruhmer of Rudolph Technologies addressed the convergence of front end (FE), back end (BE) and flat panel Display technologies that is happening in order to meet the requirements of mid end packaging technologies such as 2.5D  on interposer, 3D stacked chips or very thin fan-out packages.

Back-end patterning demand is moving well into the single digit micron range (< 5μm L/S) for current high density applications. One way of reducing cost while achieving such dimensions  is to take advantage of economy of scale brought about by larger format processing.

Glass interposers for 2.5D lend themselves to diverge from traditional round wafer form-factors and move to small rectangular panel sizes used early on by the FPD industry. It is thought that processing such panels will require manufacturing techniques which have previously been utilized for Flat Panel Display manufacturing.

A cost analysis by Rudolph concludes that a 1.7X cost reduction in lithography can be achieved  by going from a 1X stepper and 300mm glass wafers to a 550 x 650mm glass panel (gen 3 LCD panel) using their panel lithography systems (all other things being equal).

fig 2

Nanium

Nanium has been recently involved with establishing 300mm production of FOWLP [see IFTLE 124 “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP?”]

At the IWPC they announced the 300mm scale up of FCI’s (Flip Chip Int) Spheron fan-in WLP technology. They were able to show process capability and reliability on a 500um pitch test vehicle. They are in the process of evolving this to 350u pitch.

Deca

We have discussed the Deca adaptive patterning technology previously [see IFTLE 124 “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP?”]

At the IWLPC Boyd Rogers presented the reliability results for a  4X4mm2, 0.4mm pitch 72 IO test vehicle shown below.

Click to view full screen.

Click to view full screen.

They are in the process of doing board level cycling and drop testing.

450mm on Hold??

Several reports including Paul Van Gerven of Bits & Chip and Charile Demergian of Semiaccurate are reporting that ASML has stopped 450mm litho development.

Van Gerven reports that customers  Intel, Samsung and TSMC do not appear to be on the same page moving forward. Demergian reports that he has heard that Intel “…was delaying 450mm production by a considerable amount.”

Starting in July, ASML minority equity investments by its largest customers. Intel was the first acquiring 15% equity ownership. Part of the deal was a contractual commitment from Intel for advance purchase orders for 450 mm and EUV development and production tools. In August, TSMC took a 5% stake in ASML ( $1.04 B) and  TSMC committed  $341 million to ASML’s R&D programs.

While it has been widely reported that volume production at 450-millimeter was scheduled to start in 2018 at the 10nm node, these recent announcements could indicate that this 2018 start date might be optimistic.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 174 DARPA ICECool Efforts for 3DIC Stack Cooling

At the IEEE 3DIC in SF in October, DARPA program manager Avi Bar Cohen presented the history of device cooling at DARPA and how it has evolved to the embedded cooling of 3D stacks.

It is well known that microprocessor frequency stopped increasing around 2005 when air cooling met its limits.

fig 1

Traditional cooling involves heat rejection to a remote fluid involving thermal conduction and spreading in substrates across multiple material interfaces as shown below.

fig 2

Such technology cannot:

- limit  the device “junction” temperature rise

- selectively target the thermally-critical devices

- extract heat efficiently from a 3D package or 3DIC stack

What is needed to take us to the next level is an embedded cooling solution at the die level. As we have discussed before [ see IFTLE xxx ] the DARPA ICECool program is divided into fundamental and applications phases with the goal of providing “… the fundamental thermofluid building blocks for the utilization of Intra and Interchip evaporative cooling in 3D DoD electronics.” It was envisioned that inter and/or intrachip cooling would be used to bring the cooling function directly to the site of the temperature rise on the device.

fig 3

Fundamental programs addressing the cooling of 3D stacks include :

GaTech / Rockwell  – STAECOOL

Click to view full screen.

Click to view full screen.

IBM / Stanford – Integrated Silicon Two Phase Cooling

fig 5

The 3D focused portion of the ICECool applications program has a goal of “enhancing the performance of embedded high performance computing systems through the application of chip-level heat removal with kW-level heat flux and heat density with thermal control of local submillimeter hot spots.”

At the December ICECool Applications kick off meeting in WDC Bar Cohen introduced the two 3D focused program winners GATech / Altera and IBM:

GaTech / Altera – SUPERCool which has the goal of bringing microfluidic cooling to the Altera FPGA.

fig 6

IBM will also participate in this phase of the contract focusing on “bringing embedded chip cooling to a high ed server and showing the extendability to 3DIC stacks.”

Click to view full screen.

Click to view full screen.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

fig 8

 

 

IFTLE 173 IMAPS 2013 – Materials Advances; Namics, Towa, Dow; Wiley VCH reading Vol. 3 of 3D Integration Handbook

The IMAPS National meeting was recently held in Orlando, FL. Let’s first take a look at some of the materials papers that were presented.

Namics 

Namics presented their latest data on available underfill solutions for 2.5/3DIC. Below we see several opportunities for epoxy underfill materials.

Namics 1

Vacuum underfilling is replacing CUF due to decreased voiding which improves reliability. Underfill must have a high enough Tg to insure the modulus is high enough to protect bumps during thermal cycling but low enough not to crack the die.

Namics proposes that in the near future it might be possible for substrate suppliers to apply a B staged underfill prior to shipping. The customer would then perform a thermo-compression bond.

Despite the obvious benefits, the drawbacks of both NCP (non conductive paste) and NCF (non conductive film) at present include required additional capital, cost more and have a longer bonding time.

Application methods for Various Underfill Solutions

Application methods for Various Underfill Solutions

Towa – Compression Molding for High End Packaging Solutions

Traditional transfer molding  has been challenged to mold 2.5/3D stacked die structures since these structures have limited space for resin flow. It is also difficult to transfer mold large wafer or panel substrates.

Compression molding was developed to mold packages with minimum resin flow. The blue layer, in the figure below , is a release film which is sucked down flat to the mold. A vacuum is subsequently pulled to remove air, gas and moisture from the cavity and molding cmpd.

Towa 1

Dow Chemical – toughened BCB

BCB has been commercially used by the packaging community for more than 20 years. Although it has various superior properties such as low curing temp, low water absorption and low dielectric constant, being a thermoset resin, toughness and elongation are not one of them.  A toughened BCB has been a “holy grail” in the BCB user community.

A new toughened BCB product has now been described by Dow. Comparative properties are shown below. As one can see most properties have been maintained while elongation has been improved 3X and shows a 2X increase in fracture toughness from 0.3 to 0.4 to 0.6 – 0.9 MPa m1/2  vs standard BCB.

dow 1

A cross section of a via in this toughened BCB is shown below.

dow 2

Volume 3 of 3D Integration Handbook being readied

It was 2008 when the Handbook of 3D Integration was published by Wiley VCH.  Since then it has been the most referenced 3D treatis on the market. Much has happened since 2008 and we, the editors, felt that rather than update the first two volumes , we would rather issue further volumes updating some chapters and adding others as required and Wiley VCH agreed.

Volume 3, due to be published 1st quarter of 2014 will be focused on processing and will include chapters on 2.5D interposers, TSV formation, bond/debond, thin, reveal and backside processing, reliability and metrology. Authors in this volume, in addition to the editors, include  Eric Beyne (IMEC),  (EVG);  Hiroaki Ikeda (ASET); James Lu (RPI); Thorsten Matthias (EVG); Rama Pulligadda (Brewer); Sesh Ramaswami (Applied Materials); Fred Roozeboom (TNO); Rao Tummala (GaTech); Larry Smith (Sematech); Doug Yu (TSMC).

wiley cover

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 172 Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013

By Dr. Phil Garrou

Many of us can recall 2008 when Toshiba commercialized the first CMOS image sensor with TSV last /backside. We called these the first 3DIC products, when in reality they were only 1 layer devices.  More recently we have discussed Sony’s plans to release CMOS image sensors where the circuitry and sensors are fabricated on separate wafers and joined by TSV – i.e. true 3DIC structures. [see IFTLE 112,”TSMC Staffing up for 2.5/3D Expansion ; Semi 3D Standards; Sony shows off 3D stacked Image Sensors” and IFTLE  137, “CMOS Image Sensor market update”]

Somehow IFTLE missed detailing the actual product technology release of the Sony ISX014 (link)  at the ISSCC earlier in the year. This is important enough in terms of 3DIC product introductions that we will cover it now.

The Sony ISX014 8MP sensor features 1.12um pixels and integrated high speed ISP.The pixel layer and logic layer part are manufactured as separate chips and stacked by using TSVs. Previously the pixel and logic circuit of Sony’s back side  illuminated (BSI) CMOS image sensor were formed during the same fabrication process. This is compared below.

SOny 1

Actual layers are shown below:

Sony 2

Using separate pixel and logic layers allows the use an optimal process technology for each separate layer. Sony fabricated the pixel chip and logic chip using 90nm and 65nm process technologies, respectively. Stacking the chips, reduced chip area by 30%, compared with the previous image sensor made using 90nm process technology.

TSVs are used connect the row drivers on the pixel chip with the row decoders on the logic chip and connect the comparators on the pixel chip and the counters on the logic chip. TSVs are formed in areas to reduce the influence of noise.  For example, comparators are arranged on the pixel chip, which can be manufactured by using Sony’s matured process technology, rather than on the logic chip.

The stacked vs conventional technologies are compared below:

Sony 3

Since the logic chip can be manufactured at Si foundries, Sony does not have to invest in advanced logic process technologies.

Sony is in volume production of the new CMOS image sensor for its smartphone, other companies’ tablet computers, etc. The size, pixel count and pixel pitch of the sensor are 1/4 inch, 8.08 million and 1.12μm, respectively. Characteristics of the CMOS device are shown below:

sony 4

Sony has not disclosed details on TSV processing. The total number of TSVs is a few thousand. The following figure shows the stacked chips cross-section.The insulators of the upper and lower chips are attached together. It seems that TSVs are formed later to connect the circuit layers of the chips. IFTLE assumes they are using the Ziptronics oxide bonding technology that they licensed previously [ see IFTLE 65, “Samsung’s 32GB RDIMM DDR3, GLOBALFOUNDRIES Packaging Alliance, Ziptronix Licensing News”.

sony 5 X sect

A recent cross section produced by chipworks helps us understand the interlayer connections done with 6um pitch TSV [link].

sony 6 chipworks

IFTLE would expect other CIS manufacturers to move in this direction shortly.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………………………….

Coming soon:

- An end of year update from Lester the Lightbulb         – more on IMAPS 2013

- more on the GIT Interposer Workshop                           – coverage of IWLPC

- more on IEEE 3DIC                                                              – coverage of RTI’s 3D ASIP

- Christmas coverage of Hannah and Madeline

 

IFTLE 171 Semicon Taiwan Part 3: Disco, Namics, Amkor

The last of our looks at September 2013′s Semicon Taiwan.

Disco

Disco claims to have 73%of the edge trim business and 90% of the back grinding business.

Disco offers trimming before or after bonding as shown below. Trimming after bonding shows faster blade wear and lower throughput. Trimming before bonding requires additional cleaning before bonding.

Disco trimming

Lowering the TTV (total thickness  variation) of temp bonding materials improves the TTV of the thinned silicon wafer. One option is to surface planarize the temp bonding material.

PLANAR

Cleanliness during the grind and CMP operations can be handled by integrated grind / CMP / clean units.

grind - polish

Disco offers both Blade and Laser Dicing.

dicing

Namics

Namics gave an update on CUF underfills for 2.5/3DIC. The Namics roadmap for capillary underfill is shown below.

semi CUF

Only fine filler underfills can be used with TSV stacked packages. Higher filler loadings are needed to reduce filler CTE.

thermal load

Higher thermal conductivity CUF can be made by increasing the filler content.

filler load

Vacuum assisted process or pressure assisted process can both be used to decrease voiding in CUF.

vacum cuff

Amkor

Choon Lee of Amkor gave a presentation on “From Advanced Packaging to 2.5D/3D.”

Interestingly, Lee predicted a silicon interposer cost of 2.7-4$/cm sq (100 sq mm) and expectations of organic interposer costs at 50% cost reduction.

Lee showed the following example of converting a silicon interposer to PCB.

Amkor1

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 170 GIT Workshop Debates Substrate Impact on 2.5/3DIC Costs; Altera 2.5D

At this week’s GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive  HVM (high volume manufacturing) applications. Certainly conference chair Rao Tummala, industry visionary whose name is synonomous with microelectronic packaging, feels the time is right to take a serious look at glass interposers both for their superior electrical performance and their promise of lower costs. The PB substrate manufacturers are also taking a serious look at this market and proposing that they can drive their technology to the required dimensions and electrical performance, though many skeptics including IFTLE are taking a “show me” attitude about these claims.

Status in Silicon

The Yole Developpement presentation pointed out that while 2.5D silicon interposer technology was fully underway at TSMC and GlobalFoundries, UMC and SPIL supposedly are near initiation, all of the rumored “driver applications,” like the Apple A7, the next gen Qualcomm phone, the Sony PS4, ST Micro’s “Wioming” application processor, wide IO memory and the next generation Altera FPGA (see discussion below) have been, at the very least, postponed. While no one would openly reveal what the current and proposed future costs are, it is believed that all of these postponements are due to cost which certainly is not yet meeting the mobile phone requirements of less than 1 cent per sq mm proposed by Qualcomm’s Matt Nowak (i.e this is roughly $550 for a 300mm wafer of interposers).

While Yole has identified at least 10 products moving towards commercialization, all of them currently require so called high density interposers (i.e. 1um L/S and as small as 10um TSV). Currently these dimensions  can only be fabricated using front end dual damascene type processing available only at silicon foundries and more recently the OSAT, SPIL.

While Yole is still projecting a greater than $1B in revenue from 2.5D TSV activity by 2017 (activity revenues including TSV etching, filling, RDL, bumping, wafer test & wafer level assembly), these projections only hold if the current “postponed applications” are quickly commercialized.

(Click to view full screen)

(Click to view full screen)

During the Amkor presentation Ron Huemoeller indicated that lowering cost could come from elimination of backside RDL on the interposers by arranging pin out on the top side high density interconnect.

Huemoeller sees high end applications being dominated by silicon, mid end applications like graphics possibly using glass and the low end applications (yet unidentified) being wide open. He sees GPU + HBM (high bandwidth memory) being adopted in 2015 and tablets and processors adopting interposer solutions the following year.

In terms of organic “interposers” he indicates that Shinko and Semco are in limited sampling of  2/2 (L/S) and Kyocera 5/5. He labels Unimicron as in “early development.”

After making the standard IFTE argument that 2.5/3DIC was needed to combat the costs of continued scaling and that system level cost savings could pay for interposer costs,  Dave McCann of GlobalFoundries indicated that GF was achieving near 100% yields with reticle sized interposers having 4 layers of high density interconnect.

McCann predicted we would see voltage regulator function on future interposers. He also described a program between Global (chip and silicon interposer), Open-Silicon (design), Cadence (EDA tools) and Amkor (assembly and test), which produced a functional processor vehicle featuring two 28nm ARM Cortex-A9 processors connected on a 2.5D silicon interposer built on a 65nm manufacturing flow. The program demonstrated first-time functionality of the processor, interposer, substrate and the die-to-substrate assembly process. The design tools, process design kit (PDK), design rules, and supply chain are now in place for other activities.

What will be the Glass Interposer Infrastructure?  

Inherently most believe that all things being equal, glass should be a lower cost interposer solution since it can be processed in large format. However, one interesting question from the audience was “…why are silicon and glass wafer the same price then ?”

Although the data from experts like Professor Kim from KAIST confirms that glass is a better electrical performance solution, especially for Rf applications, the major issue is that a complete infrastructure is not yet in place to manufacture such glass interposers.

The big 3 glass producers ( Corning, Asahi Glass and Schott) have been listening to Tummala for several years now and all 3 are involved with his GaTech interposer consortium which has been promoting the use of glass. They each have their own technologies for forming TSV, but the infrastructure appears to stop there. While Corning’s Windsor Thomas said they are nearly ready to ship rolls of glass containing TSV, the question expressed by many in the audience was “ship to who?” Schott is in the same position.

Corning TSV (Click to view full screen)

Corning TSV (Click to view full screen)

Asahi Glass (AGC), however, appears to be a step ahead, having announced the formation of Triton, to produce and deliver circuitized glass interposers (link). This certainly will help AGC better understand the market and what the technology limitations are.

Neither the “panel of experts,” the speakers or the audience had a convincing argument as to whether traditional flat panel LCD manufacturers or PCB houses would be better at handling the metallization and singulation issues that still remain with glass panels (or rolls). LCD manufacturers use aluminum, not copper and we are told by Thomas of Corning, “Have absolutely no interest in this technology at all.” The PCB industry appears interested (certainly by their presence at this meeting) but would have to change nearly every unit operation and material that they currently use in order to meet the advanced requirements of 2.5D interposers.

What can PCB based Interposers Deliver

PCB’s are of course the first interposers, i.e most of the BGA substrates that exit today are PCB technology. So really the question that is being asked is “ …can PCB technology ever produce thin film silicon dimensions?”

Hu of Unimicron indicated that moving toward 2/2 (L/S) in polymeric PCB technology was doable but would require a move from wet processing to dry processing, the use of stepper lithography, embedded copper lines  and a change of core material to minimize warpage. Even if 2um lines and spaces were possible, this would have to be done in a class 100 clean room (more cost !) and does not address the TSV and catch pad dimension issue which really determines how many layers of interconnect are needed. If materials are changed and a move to thin film processes and equipment and facilities are needed, IFTLE questions whether costs will be considerably lower.

Unimicron embedded lines (Click to view full screen)

Unimicron embedded lines (Click to view full screen)

Koizumi of Shinko showed data on a 200um glass core PCB with a 5/0/5 build up process ( 30um polymer/18um thick Cu per layer) . When diced such structures resulted in what they called “Se-wa-re” (loosely translated back split) which was fracture through the glass core layer due to the stresses built up on both sides of the core.

GIT Conclusions

Enough encouraging data was shown to reasonably conclude that both glass and PCB should continue to be examined to fully understand their ultimate capabilities and costs.

Altera 2.5D Postponed

For those of you who haven’t noticed, the move of Altera to Intel to build FPGAs using its 14-nm FinFET process technology [link] basically terminated the intentions of Altera to commercialize FPGAs using the TSMC CoWoS process as previously disclosed [link].

This is certainly another setback for 2.5D commercialization.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 169 EMPC – Grenoble part 3: Fine Pitch RDL; Handling Ultra-thin Die; Backside Passivation as Stress Compensation

Leti / ST Micro – Interposer Fine Pitch RDL

Passive interposers redistribute the electrical lines from the attached upper dies down to the organic substrate through μPillars, RDL, TSVs and solder bumps, thus somehow acting as a pitch adapter between dies and substrate.

Backside RDL on a passive interposer can be created by either damascene integration or “conventional”  integration as shown in the figure below.

Damascene approach mainly consists in full wafer copper plating over etched trenches followed by a CMP, allowing to retrieve at the end, a fully planarized surface. This integration allows an easy access to sub-micron line/space widths but at a higher cost, mainly due to CMP steps.

leti 1

Leti / ST Micro have investigated investigate the minimum pitch that could be achieved with the conventional approach. Under their conditions they were able to achieve 8um l/s with high uniformity and reproducibility.

BESI/IMEC – Handling Ultra-thin Die

The use of ultra thin die (thickness less than 50um) requires specially designed handling solutions due to their fragility and flexibility.

BESI and IMEC have examined several tape types (UV vs thermal release), ejection systems, die size (5 x 5mm; 40um thick) and bump configurations.

Click to view full screen.

Click to view full screen.

They also examined both face up and face down to the wafer tape:

Besi 2

Their conclusions include: (1) proper dice/grind and stress relief needed to maximize die strength; (2) some UV tapes resulted in residues; (3) thermal release tapes gave larger process window; (4) stable and reliable picking of ultra-thin die can be achieved with throughputs greater than 3000 units per hour using several different hardware, maerial, process combinations.

SPTS – Low Temp Via Reveal Passivation with Stress Compensation

2.5 and 3DIC wafers require backside processing including thinning to reveal the TSV, passivation, RDL and creation of copper pillar connections. Before the wafer reveal process CMOS devices are usually temp bonded to carriers (Si or glass) and thinned to ca. 50um. The temperature stability of the temporary bonding adhesive sets a limit on the upper temp of subsequent processing steps. The current goal for this temperature would be ca. 190 C.

The backside passivation also serves to maintain the bow of the thinned wafers to a manageable level (ca. ~ 10mm) to allow subsequent processing steps. Full thickness 300mm wafers (770um) typically have incoming bow in the range of 100 – 200um. If thinned to  50um and released from the carrier the 300mm wafer would show a bow of several cm making them unprocessable and potentially lead to cracking after debond. Backside passivation stress can be tailored to compensate for the incoming wafer bow. CMOS cu/low-K wafers usually show tensile stress and thus backside stresses must be net tensile to compensate.

Compressively stressed SiN films generally give the best diffusion barrier properties. For the via reveal passivation stack compressive SiN with stress of – 100 MPa was used.

SiO films deposited using TEOS based chemistry is tunable from -200 to +200 MPa, but are must be taken since tensile SiO has a limited thickness cracking threshold.

SPTS

TEOS Cracking Threshold (left) and SiN Electrical Characteristics

The final solution was to develop a 190 C SiN film with a tensile stress of +200 MPa and a cracking threshold of 7um (deposited onto compressive SiN barrier).

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

 

Hope to see you all at this years RTI ASIP. It is the 10th Anniversary of this 3D focused meeting.

RTI ASIP

 

 

IFTLE 168 EMPC Part 2: FC Market; BLR of BoP WLCSPs; Chip Embedding; Temp Stability of Molding Compounds

Yole – FC Market & Tech Trends

Rozalia Beica, newly appointed CTO of Yole Developpement, examined the FC marketplace. The FC market is currently growing at CAGR of 19% as a result of expanded use in memory, consumer electronics and mobile phones. In 2012 bumping capacity of 14MM 300mm equiv. was in place accounting for 81% of all “mid end” capacity.

FC technology is being reshaped by the demand for Cu pillar bumping (CPB) and microbumps which are both quickly becoming mainstream. CPB is expected to show 35% CAGR over the period 2010 – 2018.

FC capacity is expected to grow in the next 5 years in response to demand from (1) 28nm CMOS application processor (APE) and baseband (BB) applications;(2) next gen DDR memory and (3) 2.5/3DIC.

FC Bumping and CPB Forecast 2010 – 2018 (Click to view full screen)

FC Bumping and CPB Forecast 2010 – 2018
(Click to view full screen)

 

ASE – Board Level Reliability of BoP WLCSPs

There hsas been reduction of  the production cost for WLCSP packages for the past years. Today, many OSATs are working on further cost reduction with customized WLCSP package designs that are optimized for specific market needs.

For example, omitting the UBM layer on smaller WLCSP devices can reduce costs and may still meet the market requirement on package quality and reliability. Omitting the UBM requires 25% less process steps, from 4-mask process to 3-mask process.

ASE reports on the BLR performance of a 3-mask bump on polymer (BoP) WLCSP design vs  a 4-mask BoP WLCSP design for 0.4mm and 0.5mm ball pitch using  tin/silver/copper ( SAC) and SACNi (Ni doping) solders and reports on failure analysis.

WLCSP (a) 4 mask process with UBM; (b) 3 mask process without UBM; (c) failure modes for 3 mask process (Click to view full screen)

WLCSP (a) 4 mask process with UBM; (b) 3 mask process without UBM; (c) failure modes for 3 mask process
(Click to view full screen)

 

The polymer material can be polyimide (PI) or Polybenzobisoxazole (PBO) with thickness of  5um to 7.5um. In most BOP WLCSP packages, ASE states that PBO is the preferred material for better stress compliance, and hence better board level reliability.

For 3-mask WLCSP design, there is no UBM. The solder ball is directly attached to the redistribution layer, using polymer 2 to define the pad opening. Therefore, the electrolytic plating copper thickness for RDL needs to be sufficiently thick to avoid any problems due to Cu consumption during SnxCuy intermetallic (IMC) formation during thermal ageing. For these reasons the Cu RDL thickness is increased from 4um, on 4-mask WLCSP, to about 8um on the 3 mask process to ensure a reliable solder joint. the thickness of polymer-2 also needs to increase to 12um polymer-2 thickness to ensure line coverage. A 12um thick polymer-2 layer creates processing challenge for PI or PBO, and the thermal stress or residual stress after high temperature curing needs to be carefully controlled to guarantee the integrity of package structure.

After board level reliability test, failure analysis was performed to confirm the failure mode. The failure modes were classified as failed at PCB side Mode A, failed at component side Mode B and solder fracture Mode C. In the failure analysis, we found that BLR failure modes are governed by shear rate applied to the tested samples. High shear rate test, like drop test, tended to fail at the component side with IMC fracture (Mode B2) or residual solder on pad (Mode B3). But, for slow shear rate test, like temperature cycling test, the fail tended to occur at the solder joint (Mode C). They concluded that 3-mask the WLCSP does not change the failure mode in either temperature cycling test or drop test.

They conclude:

- BLR temperature cycling performance is governed by the WLCSP device size (DNP). The bigger the DNP, the worse temperature cycling lifetime. This was evident for both solder materials used in this study, even though the larger device has a larger solder joint size, and there was a larger difference between SAC405 devices than SACNi devices.

-  In general, the 3-mask WLCP has worse BLR performance than 4-mask WLCSP.

-  SACNi solder gives improved BLR Drop test performance (characteristic life, and first fails) for both 4-mask and 3-mask WLCSP devices.

-  They found the same failure mechanism and failure modes on 3-mask WLCSP as 4-mask WLCSP.

 

Chip Embedding at IMS

Ultra-thin chips (less than 50 μm thick) can be assembled by either on flexible films; i.e. chip-on-foil technology or by embedding them inside the foil. Initial work by the Institute for Microelectronics Stuttgart (IMS CHIPS) dealt with attempts to glue attach Chipfilm dies onto flexible foil substrates. They have now described research with less than  20μm thickness die with a two polymer (BCB and PI) ultra-thin chip imbedding approach.

Polymers used for embedding should be flexible and at the same time strong enough to keep the chip firmly embedded. To achieve an optimal solution for the desired process IMS used a combination of polymers where BCB serves as the embedding polymer for ultra-thin chips and the PI as the  reinforcement polymer. The X sectional structure is shown below.

Two Polymer Embedding of Ultra-thin Chips

Two Polymer Embedding of Ultra-thin Chips

The PI reinforcement layer provides strong yet bendable reinforcement for the entire chip stack. The BCB embedding polymer provides excellent electrical properties, low moisture absorption, compatibility with the interconnect metals and fine pitch patterning compatibility.  The process flow is shown below. An initial “adhesion lowering layer” is initially coated on the wafer to allow for package removal once the process is complete.