Category Archives: Uncategorized

IFTLE 190 TSMC Focus on Packaging; Samsung Licenses “3D” to GF; More on IBM and the Cloud

TSMC Packaging Plans

Digitimes reports that  TSMC plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016 [link] . Based on this roadmap, TSMC would  become the 3rd leading  packaging company in Taiwan by 2016, trailing  only ASE and SPIL.

At the TSMC NA Technology Symposium April 222nd in San Jose,  TSMC described a wide range of  packaging offerings including  an integrated fan-out wafer level packaging (InFO-WLP) process which will start production by the end of the year and  an InFO PoP configuration which will enable stacking a wire-bonded multi-die package on top of an InFO-WLP. They also have a more standard WLCSP ( Wafer-level Chip Scale Package) that  will support devices with up to 800 pins.

Samsung licenses 3D chip manufacturing tech to GlobalFoundries

As I headed out of town to spend Easter with the grandkids last week, my phone pinged me with the following Reuters headline. “Samsung licenses 3D chip manufacturing tech to GlobalFoundries to win more orders” [link]

“Wow that’s great” I thought as I boarded the plane. A few hours later, now in Houston, I turned on my phone and quickly found the article. Down in paragraph three we find that they call their 3D technology “finFET.” Nothing in this article was incorrect and it’s not like we are the only community who are allowed to use the term 3D, but it sure does make things confusing. Recall the EE Times headline in 2011 “TSMC May Beat Intel to 3D Chips” where 3DIC was unknowingly being compared to FinFet. [See IFTLE 62, “3D and Interposers – Nomenclature confusion; Equipment Market Shift to Pkging Continues”]

Glad to report that EE Times learned its lesson and this time came out with a more appropriate headline than Reuters namely “Samsung, Globalfoundries Prep 14nm Process” [link]


More Info on IBM and the Cloud

IBM just reported its lowest quarterly revenue in 5 years on Wednesday as Reuters reports “…the company struggles with falling demand for its storage and server products.”[link]

We have recently discussed IBM semi business being for sale and their proactive move into the “cloud” space [ see “IBM Continues to evolve: Semi business up for sale, moving into the clouds”]

Revenue from their hardware business, which includes servers and systems storage, felled 23 percent to $2.4 billion. IBM warned that the hardware business may continue to face issues with their CFO commenting, “As we look to the balance of 2014, …our overall revenue growth will be impacted by the challenges in our hardware business.”

IBM has also lost its position as number two software make behind Microsoft Corp. with Oracle recently claiming that position.


As IFTLE has told you, IBM looks like they are betting the farm on cloud computing which allows their customers to stop using (and replacing) servers by moving to remote data centers run by 3rd party companies. They have recently bought two companies to expand their cloud business, Silverpop, a developer of cloud-based marketing software, and cloud-based database software startup Cloudant.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 189 IMAPS DPC Part 3: FCI, GF/Amkor; Corning; Namics

By Dr. Phil Garrou, Contributing Editor

Flip Chip Int (FCI)

FCI and Suss Microtec examined the use of lasers in the manufacturing of WLP.

Commercial dielectric via formation today used in WLCSP, RDL and flip-chip products typically rely on standard photolithography processing using stepper and 1x aligner equipment and processes.  Interest in using laser via drilling (ablation) centers on the following reasons.

- Reduced via dimensions

-  Simplified process flow

- Reduced process time

- Cost reduction

- Enable a broader range of  dielectric materials (i.e., non photo dielectrics and mold compound)

- Eliminate organic solvents used in many pholithography process

FCI 1With PBO via dimensions as small as 7.3um are demonstrated on PBO with an application desired sidewall angle around 60 degrees. Sidewall angles can be adjusted by changing the laser fluence and other settings.

- Higher fluence: Steeper wall-angle

- Lower fluence: Shallow wall-angle

Underlying metals (> ~1µm) can be used as a laser stop for via formation. By controlling the fluence and other settings the process has the ability to also stop at a certain depth in the dielectric without a metal backstop.

Since laser via ablation can produce smaller via dimensions compared to standard photolithography methods, using a laser via ablation technology can improve the design rules for next generation RDL layouts.  In addition, the ability to utilize non-photosensitive organic dielectrics can enable better mechanical and thermal properties as the bump diameter and pitch shrink, improving end product reliability.

Global Foundries / Amkor / Open SIlicon

GF, Amkor and Open Silicon described their 2.5D ARM dual core product demonstrator which consists of 2 ARM die on a high density  silicon interposer. A schematic of the module and he process flow are shown below . It was noted that “…extensive UF material development was needed”  for the u-bump pitches that were used. A cumulative yield of 93.7% was achieved.

GF 1-1

They used the following assembly flow:

GF 2


Corning is beginning to show results of the multiple glass interposer programs they have instituted at sites such as RTI in RTP NC, GaTech and ITRI. One interesting proposal from Corning is that starting with 100um glass substrates should eliminate the need for backside grinding  for via reveal . The 100um “Willow glass” with TSV is temp bonded to another glass layer  and the TSV are filled . The interposer “panel” or wafer is then removed from the temp bonding substrate.  It will be interesting to learn exactly how that is done (both the metallization and the release).

Work with RTI is showing the filled TGV can survive ( defined as less than 15% increase in initial resistance) greater than  700 thermal cycles of -55 to 125 ˚C and 20 x 20 arrays of TSV on 100um pitch are showing > 99.9% yield.  The RTI team has also begun to show assembly of chip to glass using copper pillar bump technology.


Namics is developing their underfill products to meet the following roadmap for FC BGA and FC CSP.

Namics 1

Underfill materials can be classified as follows:

namics 3

Their FEA modeling shows that Cu pillar and lead free bumps require a higher Tg underfill to protect from bump fracture during TCT, however low Tg may can assist with warpage, delamination and failure.

Modeling also showed that stress on low K of the IC is increased when using fillers that show filler separation (settling).

Underfill void elimination can be reduced by either using  vacuum assisted CUF  or curing in pressure oven.

namics 3 Untitled

For all the latest in 3DIC and advanced packaging technology, stay linked to IFTLE…



IFTLE 188 IMAPS Device Packaging Conf Part 2: AMD, SCP

Continuing our look at the recent IMAPS DPC with several key presentations.


AMD’s keynote presentation by Bryan Black updated us on their thoughts about “Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!”

As we have discussed on IFTLE many times, Black agrees that future nodes will NO LONGER bring down transistor costs which has been a longstanding premise of Moore’s Law.


Die Stacking Motivation

  • Process complexity is increasing and yield is dropping as mask count increases
  • Large die sizes will continue to have yield challenges


Black adds that die partitioning is challenging and there is significant microarchitectural research to be done since the buss to connect partitioned chips is very complex.

As we heard from Hynix at the RTI ASIP conference in December 2013 [see “AMD and Hynix announce joint development of HBM memory stacks,” the first generation of Hynix high bandwidth memory is now sampling.]


This results in a 3X improvement in bandwidth per Watt.


Black envisions silicon interposers replacing SoC for high end platforms in the future.


Black announced that AMD AND Hynix were looking for partners to begin immediate development of such products.


In an attempt to expand the usage of their eWLB technology, SCP announced FlexLineTM as a “breakthrough manufacturing method for Wafer level packaging”.

Tom Strothmann of SCP pointed out that OSATS have traditionally been forced to use wafer processing equipment sets for both 200 and 300mm wafers, that typically have higher cost and capability than needed.

Currently, separate equipment sets are required to manufacture WLCSP from 200 or 300mm wafers whereas the FlexLine process allows them to be manufactured on the same equipment set.

The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process [ see IFTLE 124, “Status and the Future of eWLB…”]. Single and multi die fan-out package solutions have been in HVM since 2009 with more than 500MM units shipped. SCP eWLB have passed all standard component and board level reliability tests.

FlexLine uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.

fig 2 SCP

The following 2D/2.5D products can be fabricated on the same FlexLine using a  standard process flow.

fig 3 SCP

Process Flow:

- Dice the wafer to dimensions slightly larger than nominal die size

- Process through reconstitution, redistribution and ball drop

- singulate removing the mold compound from the side of the die and reducing the die size back to the nominal size

To create an encapsulated WLCSP (eWLCSP):

- Dice the wafer at nominal die size

- Process through reconstitution, redistribution and ball drop

-Final singulation is done larger than the die size, leaving a protective layer of mold compound on the sides of the die

- The end product here  is a e-WLCSP that cannot be made with conventional WLCSP processes

Strothmann indicates that SCP COO studies conclude that the added cost of reconstitution is offset by the larger panel size that is processed. CTO BJ Han adds “…with FlexLine we are able to help our customers achieve at least a 15-30% cost reduction using the optimum design requirements for their WLCSP devices.”

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…


IFTLE 187 More IBM rumors; Altera FPGAs, IBS Addresses Transistor Costs, ASE / Inotera 3DIC JV

IBM Semiconductor

According to the Wall Street Journal GlobalFoundries (GF) “…has emerged as the leading candidate to buy IBMs semiconductor operations.” [link]  According to these reports IBM who initially asked for $2B has met with TSMC, Intel and GF. The reports continues that  and that TSMC has dropped out of the bidding which exceeded $1B but appears contingent on how much intellectual property IBM includes.

IFTLE readers already knew that GF was the lead candidate [ see “IBM Continues to evolve: Semi business up for sale, moving into the clouds”]. Maybe the WSJ is reading IFTLE ??

Intel / Altera / TSMC

Recent reports indicate that Altera had expanded their foundry deal with Intel to include “multi-die” devices that combine Altera’s Stratix 10 FPGAs and SoCs with DRAM, SRAM, ASICs, processors, and analog chips in a single package.” [link]

This announcement left some in the industry confused.

Let’s review some background…

Recall in March 2012 Altera announced that they were working with TSMC on 2.5D FPGA program (much like their already commercial competitor Xilinx). [“Altera and TSMC Jointly Develop World’s First Heterogeneous 3D IC Test Vehicle Using CoWoSTM Process”]

Then in Feb 2013 Altera announced a foundry agreement with Intel to access their 14nm technology for FPGA production, probably meaning no need for 2.5D.

[see IFTLE 170, “GIT Workshop Debates Substrate Impact on 2.5/3DIC Costs; Altera 2.5D” ]

…but then, in Feb 2014, Intel announced the 14nm technology program was being postponed to 4Q2014/1Q215  [“Intel postponed Broadwell availability to 4Q14”].

…and then there were reports March 5th 2014 that Altera was “… expected to have TSMC fabricate its next-generation FPGA chips using TSMC’s 16nm FinFET+ process, instead of producing the chips using Intel’s 14nm tri-gate transistor technology”

So, I hope that is now clear (tongue-in-cheek) …


Those of you that stay linked to IFTLE know that I have been quoting Handel Jones of IBS for years (literally since 2009) since his analysis of what is happening to the economic infrastructure Re: Moore’s Law makes the most sense of anyone out there. The article he just wrote for EE Times, “FinFETs Not the Best Silicon Road” should be of interest to us all.

His premise is that semiconductor industry growth has historically depended on a reduction in cost per transistor but next-generation chips will not deliver this cost reduction. While next-generation 20nm bulk CMOS and 14nm FinFET process will deliver smaller transistors they will have a higher cost per gate than today’s 28nm bulk CMOS.


Cost will remain higher even as the processes mature.  IBS predicts that the traditional cross-over point for the newer generation technology will not happen  (point at which newer not becomes cheaper, per transistor, than older node. The cost per gate for 28nm bulk CMOS will be much lower than FinFETs even in the fourth quarter of 2017. A similar pattern will occur for 20nm bulk CMOS in 2018 or 2019 when depreciation costs decline.


Jones indicates that the 20nm node issues include:

- difficulty achieving low leakage due to challenges in controlling doping uniformity

- line edge roughness

- the need for double patterning

The 16/14nm FinFET node:

- uses the same interconnect structure as 20nm, so the chip area is only 8-10% smaller than 20nm

- faces yield issues related to stress control, overlay, and factors related to the step coverage and process uniformity of 3D structures.

Jones concludes that “..FinFETs can be used for high-performance or ultra-dense designs but are not cost effective in mainstream semiconductors “

ASE, Inotera reportedly to set up 3D IC packaging joint venture

Digitimes has reported that ASE and Inotera are reportedly setting up 3D IC packaging joint venture for handling TSV 3D IC packaging. ASE and Inotera are expected to finalize the deal soon, said the sources, adding that the joint venture is likely to be set up either at a Inotera’s idle plant or at a ASE plant in Chungli, Taiwan.

Initial production goals are reportedly 10,000 3D IC chips a month,  and should include Aps (application processors) and mobile RAM chips.

DIgitimes sources add that they expect the JV  to compete with TSMC in the 3DIC packaging sector.

Inotera, incorporated in 2003, is a joint venture between Nanya Tech (an affiliate of the Formosa Plastics Group) and Micron.

Inotera has two 300mm fabs with a combined capacity of approximately 120 thousand wafer starts per month providing 300mm DRAM foundry services. According to the supply agreement between Inotera and Micron Technology, Inotera sells substantially all of its manufacturing output to Micron.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 186 IMAPS Device Pkging Conf: Qualcomm, Prismark

This year’s IMPAS Device Packaging Conference in Ft McDowell, AZ had a series of excellent keynote talks. We’ll first take a look at some of those and then look at several key presentations from the conference.


Steve Bezuk, Sr. Dir. of Package Engineering for Qualcomm discussed “challenges and directions in mobile device packaging”. Qualcomm expects 7 billion smartphone units to be shipped between 2012 and 2017.

Handset thickness continues to be reduced and is now approaching 6mm. Since the battery and the screen are not shrinking chip packaging and the substrate board must make up the difference. Most of these packages are FC and WLP. Bezuk commented that 5 years ago very few of the packages were WLP but now this category accounts for near 50% of the packages IC.

Molded FC die on thin core or coreless substrates are approaching 750um thick and warpage issues are becoming significant.  Warpage is dependent on :

- core thickness, CTE and modulus

- EMC thickness over die

-  die thickness (ratio of Si/EMC).

Solder balls have become a significant fraction of the total package height.

qualcomm 3

Tighter pitch requirements ( < 140um) have necessitated  a move to copper pillar connections which in turn need thermocompression bonding to overcome warpage/flatness issues in such structures.

Thinner packages require thinner EMC above the die which results in increased warpage and requires EMC with higher mold shrinkage and higher modulus.

qualcomm 4

Bezuk reports that typical HVM substrate properties in 2014 are as follows:

Current 2014 HVM

Patterning Method (µm)

SAP (15/15)

Min FC pitch (µm)


Core material CTYE (ppm)


Decouling solution

Embedded caps

Buildup dielectric

Prepreg, ABF

Having reached a core CTE of 3, reduction in substrate core CTE is no longer an option so the industry is turning to develop materials of increased modulus.

Bezuk proposed that the next move (time undefined) will be from today’s FC PoP structures to 2.5/3D moving first to wide IO DRAM on logic and next to logic-on-logic. Although he added that there was no clear infrastructure answer for where interposers will be coming from.


Brandon Prior of Prismark continued on the theme of “Mobile packaging and Interconnect trends.” Their analysis of the Apple 5S smartphone confirms the Qualcomm comments about increased use of WLP as can be seen in the fig below.

prismark 1

Despite all the talk about high density laminate technology approaching < 5um L/S, Prior indicated that the Apple 5S was the first device to use 50um L/S and CSPs on a 0.4mm pitch. It is also interesting that caps continue to shrink. 01005 is 0.4 x 0.2 x 0.13mm which is extremely hard to assemble.

The Apple A7 processor is packages in PoP with the memory package being 1Gb of LPDDR3. The substrate has 27um L/S and 150/170um bump pitch. Memory chips are Ag WB which is a lower force assembly process than Cu WB. While these memory chips are still WB, Prismark stated that they expect performance DDR to go FC at the big 3 memory suppliers and expect 5B units shipped by 2018.

prismark 2

Prior showed the following application processor roadmap for phone/tablet low end vs high end products.

prismark 3

Transition to 0.4mm packages

FBGA and WLP are in high volume production at 0,4 and 0.35mm pitch. Wafer CSP moving to 0.3mm and below. Prismark forecasts > 28% of CSP/WLCSP to be 0.4mm or less by 2018.

prismark 4

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 185 Lecturing the Packaging Community on Nomenclature

The word “lecture” is one of those wonderful English words with multiple meanings. Lecture can mean “a talk or speech given to a group of people to teach them about a particular subject,” but it can also mean “a talk that criticizes someone’s behavior in an angry or serious way.” In IFTLE 185, lecturing means both!

Those of you that are regular followers of IFTLE know that every once-in-awhile, I’ll stop reviewing the latest technology presentations to try to bring home a point. The latter is necessary right now.

Some may call this one of my “rants” but the online dictionary defines a rant as “…an argument fueled by passion and not shaped by facts.”  I can assure you this rant will be shaped by both passion and facts.

What triggered IFTLE 185 was a panel session held at the recent IMAPS Device Packaging Conference in Ft McDowell AZ. A good panel session experts discuss controversial topics but that is not exactly what happened here.  This panel session degraded into a school yard verbal battle (panel members and audience) over what certain terms mean. If you really want to follow the chronology of the discussion you can here [Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel].

It is simply amazing that the assembled group of technical practitioners could not agree on what certain packaging terms mean but….they couldn’t. At first I chose to sit quietly in the audience amused at the miss speak…but then… my good friend Bob Patti, a panel member,  spotted me in the corner of the room and called me out …” Phil what do you think “…it was at that point , no longer able to hold back, that I unleashed my tirade […a long angry speech of scorn and criticism…]

Let me attempt to articulate my position on several of the topics that came up that night …

INTERPOSER – for some reason, be it ignorance, youth or a combination of both, some in the audience continue to believe that the term interposer was invented for 2.5D.

All 1st level packages are interposers, The purpose of an interposer is to spread a connection to a wider pitch. Interposer comes from the Latin, interpōnere, meaning “to put up between.” A BGA substrate is an interposer ! This is clearly shown in the Infineon slide that they have been showing for nearly 20 years.

infineon 2

SYSTEM-in-PACKAGE – there was mass confusion on what this meant and what is included in this definition. Several experts felt that 2.5/3D were NOT included in the definition of SiP. I think some of these disagreements come from the fact that corporations do not divide things up in their business units based on definitions so all things SiP may not be in the same business unit and this influences their thinking.

In the 1990s multiple chip packages, MCMs as they became known, were sets of chips that were connected on high density Si, laminate or ceramic substrates by WB or C4. In the early 2000’s it became vogue to call these system-in-package as industry focus became delivering functions for portable devices in separate modules. Need more history on MCMs try the Multichip Module Technology Handbook [link] which Iwona Turlik and I edited in 1998.

Let’s look at another Infineon slide, below. Whether its side by side, stacked, through hole or embedded, these multiple chip solutions are all versions or categories of SiP.

Infineon 1

2.5D, 2.1D and 5.5D: Please stop the madness!

3D packaging defines the various ways of stacking chips in the z direction whether it be WB them to a common substrate, package-on-package stacking, embedded chip stacking (in laminate or EMC ) or direct connection with TSV.

The term 2.5D is usually credited to ASE’s Ho Ming Tong who ~ 2009 (or even earlier)  declared  that we might need an intermediate step towards 3DIC since the infrastructure and standards were not ready for 3DIC stacking yet.  Tong felt the silicon interposer would get us a major part of the way there, and could be ready sooner than 3DIC technology.  He used the term 2.5D, which immediately caught on with other practitioners. Tong was not trying to create a new nomenclature, he was making a joke that we were not ready for 3D but this silicon interposer with TSV would get us close. He actually got laughs when he called it 2.5D at the RTI ASIP conference fall of 2009.

We are now starting to hear the laminate community use the term 2.1D for high density laminate and some in the silicon interposer community using the term 5.5D  for a 3D memory stack on an interposer. To all this, all I can say is “STOP – Enough-is- enough…it’s no longer funny..”

At one point during Bryan Black’s AMD talk at the conference he said “3D” and the audience interrupted him to ask whether he meant 2.5D. His response was something like “Oh yeah…well they both mean the same thing to me..” meaning we are talking about stacking technology with TSV.  Bryan is correct!


LAP is being held out as the solution to everything that is not economical these days. FOWLP not low enough cost to break into commodity applications ? …don’t worry we’ll use LAP and the price will come down. Glass interposers not looking like the price will be low enough for mobile products?…don’t worry we can manufacture on LAP lines and the price will come way down.

Certainly our microelectronics educations have taught us that larger usually means cheaper, i.e. chips from 300mm lines ARE cheaper than the same chips from 200mm lines. This is true as long as the equipment and technology is available to give you high yields, i.e. see the current 450mm situation.

My point to the audience was that PCB are made in large panels because they can be…higher density BGA substrates are made in much smaller strips because they have to be!

I actually have hands on experience at what we called LAP back in 1995-1997, as we had a major DARPA contract to try to manufacture MCM substrates  on a sq 400mm format. Check out my chapter “High Density, Large Area Processing (LAP) in the Multichip Module Technology Handbook [link]. By the way our program with MMS and others to manufacture high density MCM substrates made for a great magazine cover (see below)…too bad it didn’t yield!


Do I think that pursuing high density LAP is a worthy R and D goal ?…certainly, lets just not act like it will be easily accomplished.

Other problems with today’s nomenclature?? Let me know …

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE !


IFTLE 184 SEMI Europe 2.5/3DIC Summit : Gartner; GlobalFoundries; TSMC; IMEC

By Garrou

Let’s take a look at some of the key presentations from the SEMI Summit that took place in January in Grenoble.

Gartner – 3D Market Forecast

Stromberg of Gartner gave a market forecast of greater than 1.5M 300mm wafer equiv per month or 2B units / year of 2.5/3D (non MEMS non CIS) by 2018 but then listed several pages worth of technical issues that could affect the forecast.


Editorial Comment:

In emerging technologies like 2.5/3D  guaging market timing and size is an art, not a science but I’m not sure what numbers like this are worth if you preface them by saying they could be inmpacted by thermal issues, yield issues, design issues and  competitive treats by PoP and  WB devices. Of course all those things are true, but then what kind of confidence do we have in the nubmbers / timing ?  This is true for al lthe marketing houses not just Gartner.


GF has been detailing their imminent commercialization of 2.5/3D IC for several years. Their current status report is shown below.


Their response to Interposer TSV formation, front side routing and backside reveal and RDL  issues are shown below. High IO counts require dense interposer frontside routing (i.e. over 1600 wires for a HBM port.


The GF supply chain for 2.5D productization is shown below:



Miekei Leong , VP TSMC, gave the standard TSMC CoWoS pitch but did offer a definition of their supply chain model where OSATS are now integrated as part of the supply chain.


Another interesting roadmap showed TSMC demonstrating HBM (high bandwidth memory) on CoWoS by 4Q 2014.

tsmc 2

IMEC – Cost Analysis

Eric Beyne of IMEC presented data on a cost breakdown of their 5 x 50µm TSV full flow 3DIC process (without stacking) showing the TSV middle fabrication process and the thin and backside eveal processing are about equivalent in cost.


They find that a lot of cost is invested in CMP processing which can be improved by reducing the Cu overburden after TSV fill.

imec 2

This can be compared to the 10 x 100µm TSV costs presented by Ramaswami of Applied Materials shown below:


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 183 RTI ASIP: Tezzaron; Suss / EVG; Packaging of Apple A8

RTI- Architectures for Semiconductor Integration & Packaging (ASIP) is always held in Burlingame, CA at year’s end. It is focused on commercial 3DIC technology and applications and is always a good indicator for the status of the industry.

In the next few blogs we’ll take a look at some key papers from this years conference.

Tezzaron acquires Ziptronix facility outside RTP NC

As we have discussed previously Tezzaron has purchased the former Sematech fabs in Austin and is running the operation as a subsidiary Novati [ see IFTLE 146, “TSMC Apple…Novati” and IFTLE 166 “IEEE 3DIC part 1;….Novati” ]

Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing [link].

In addition Tezzarons Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly. [link]

Tezzaron, known for its fine featured TSV showed the following process status and an interesting X section of a W TSV connected at M5.

suss 1

Suss and EVG

Suss and EVG examined their processes and equipment available for thin film handling of 2.5 & 3DIC wafers, namely temp bonding and debonding.

They are both working with a number of materials suppliers as shown in the Table below. All of them now supply room temp (RT) debonding solutions

 Temp bonding materials supplier



Brewer Science








Dow Corning



Thin Materials AG




Shin Etsu


HD Micro





Typical thickness requirements for temporary adhesives are dependent on the interface that is being bonded as shown below.

Suss 2

Both Suss and EVG have recently  introduced eximer laser assisted RT debonding which was first introduced by 3M years ago. [ref]

suss 3

EVG is also touting a laser-initiated debonding process flow.

Brewer has introduced a new UV absorbing release layer which is stable up to 350 ˚C.

suss 4

Amkor, STATS ChipPAC and ASE to package  Apple A8

DIGITIMES is reporting that Amkor  and STATS ChipPAC will each package  40% of the Apple A8 processor, with the remaining 20% by ASE.[link]

They report that Apple’s A8 chip will be a package-on-package (PoP) SoC solution comprising processors and mobile DRAM in a single package.

(TSMC, which is believed to have landed foundry orders for Apple’s next-generation A8 chip, has reportedly also secured wafer bumping orders for the processor as part of its turnkey solution.  TSMC reportedly will start ramping up production using 20nm process technology for Apple’s A8 chip in the second quarter of 2014.


The recent Semi Industry Strategy Symp (ISS) occurred in Half Moon Bay CA a few weeks ago. In the past this has been a treasure trove of information on how and why the IC industry is making the moves that it does. Let’s take a look at some of the key papers from this conference.


IBM fellow Jon Casey examined “System Scaling Technologies and Opportunities for Future IT Workloads and Systems” He notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.

Volumetric scaling will be critical to future performance enablement

– Tightly coupled modules and components

– 3D stacking and interposer integration

Casey examined the current state of interposer substrates and showed the following comparison:











Linx consultants looked at “Chemicals and Materials in Semiconductor Devices.” IFTLE notes that an examination of materials suppliers shows that while chip production is moving out of Japan due to cost, Japan still has quite a few of the major materials suppliers on its shores.

linx 2











Linx lists 3DIC among the major 5 challenges for the IC industry in the future.

Linx 3


Like many other prognosticators, Linx points to the cost of 450mm fabs as the main cause of the ever shrinking customer base.

linx 4


An Steegen, Sr VP, IMEC examined “Scaling Beyond 10nm.” She offered the following roadmaps for 3D applications and TSV dimensions.


And the following CoO Analysis for their  3D process flow.



IHS examined semiconductors in the electronics value chain.  An unexpected piece of data is that consumers are spending more on hardware (HW) than content i.e.:



Our friends at Int. Business Strategies (IBS) who in the past have contributed significant data to IFTLE arguments that 3DIC makes economic sense in light of the other scaling options, addressed They indicated that growth in 2013 was mainly due to an increase on memory pricing. They expect Capex decreases in 2014 (small decline)  and 2015 (large decline).

While there is uncertainty in the timing for scaleup of 20 and 16 nodes, by 2020 they expect greater than ½ semi sales will come from 32nm and below.


They also conclude that low power and low cost will dominate the application space for 32nm or less devices.

They continue to predict that cost/gate will no longer be a cost driver.

IBS 10

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…



IFTLE 181 IEEE 3DIC contd: Tohoku Univ; Fujitsu; ASE; RTI

Finishing up on the IEEE 3DIC meeting from Oct 2013 in San Francisco lets look at some of the remaining key papers from the conference.

Tohoku Univ – Lattice Distortions in Thinned Silicon

Professor Koyanagi and coworkers at Tohoku Univ and GINTI [ Global Integration Initiative – see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati” ]

It is accepted that to achieve compact-sized 3DIC each functional wafer should be thinned to 50μm or less. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping and local deformation in the stacked die .  Moreover, the weak mechanical strength of the extremely thin die/wafer itself has a potential concern lead to die breaking for 3DIC integration, because thin LSI chip with high density TSVs is highly fragile and more easily damaged. Hence, it is important to understand the impact of chip’s mechanical strength on device reliabilities decreasing die thickness, especially below 50μm thickness.

Koyonagi and co-workers have found that the Young`s modulus (E) of Si substrate begins to noticeably decrease below 50μm thickness. The Young`s modulus in 30μm thick Si is 30% of the modulus of 50μm thickness. In 30μm Si the lattice structure is highly distorted which induces the Young`s modulus reduction and consequently weakens the mechanical strength.


DRAM chip of 200μm thickness were bonded to a Si interposer and thinned down to 50, 40, 30 and 20μm respectively. The measured retention characteristics of DRAM cell on these thicknesses of silicon are degraded dramatically below 50-μm thickness, i.e. the retention time of DRAM cell in 20μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip.


They assume that the band-gap energy in the thin chip is affected by the distortion of the lattice structure, hence effect on a minority carrier lifetime, consequently shortening the retention time of DRAM cell.

Fujitsu – Influence of Wafer Thinning on Backside Damage

Fujitsu is known for their ultrathin WOW process [ see  “Development of Multistack Process on  Wafer-on-Wafer (WOW)

Ultra-thinning to 10 microns or less of Si wafer is expected to realize small TSV with low aspect ratio and coupling capacitance. Subsurface damage following wafer thinning from the back of 300 mm wafers using three different types of thinning process was investigated by means of Raman spectroscopy, XTEM, and Positron annihilation analysis, respectively. A coarse grinding generates significant rough subsurface ranged several micron and damage layer including amorphous and plastic-deformed Si along grinding topography. Fine grinding, second step of thinning, reduced those surface roughness and almost removed after thinning at least removal of 50 microns. However, plastic-deformed subsurface layer with a thickness of 100 to 200 nm are still remained which leaves an inside elastic stress layer ranging up to about 10 microns in depth. Chemical-Mechanical Polishing (CMP) process as a final step of thinning enables to remove residual damages such as structural defects and lattice strains after 1-5 microns thick polishing while vacancy-type defects only remain.


The authors acknowledge that further investigations are necessary to find “hidden residual defects” and to understand the influence of thinning on memory devices (see Tohoku discussions above).

ASE / Chiao Tung Univ – Low Temp Bonding

ASE and National Chiao Tung Univ  have studied three types of bonding, including Cu-In, Sn/In-Cu, and Cu/Ti-Ti/Cu, for application of 3D interconnects.

Cu-In bonding and Sn/In-Cu bonding can form intermetallic compounds at the bonding temperature lower than 180 C. Cu and In samples were bonded face-to-face with a bonding pressure of 1.91 MPa, followed by a heating temperature of 170 C for 50 min. Sn/In and Cu samples were bonded face-to-face with a bonding pressure of 1.91 MPa, at bonding temperature of 180 C for 50 min.

Cu/Ti samples were bonded face to face with a bonding pressure of 1.91 MPa, at a heating temperature of 180 C for 50 min.  They add that Cu can be protected from oxidation by capping Ti on Cu surface before bonding. This last structure is especially significant if one can really do such bonding at 180 C . Their EDX investigation of the interface shows that “…apparently there is a Cu layer at the bonding interface instead of Ti layers…due to lower activation energy at the surface, Cu tends to diffuse towards the surface  …”  IFTLE feels this combination certainly deserves further study.

All bonded structures have shown excellent electrical performance and reliability characteristics. Based on bond results, these structures can be applied for low temperature bonding in 3D interconnects.

RTI – 10um Pitch Bonding of Hetero Materials

Matt Lueck of RTI Int described their successful demonstration of the use and reliability of Cu/Sn microbumps for the fine pitch interconnection of heterogeneous semiconductor die. InP die have been bonded to Si substrates using a 6.4 mm × 5.12 mm area array of alloyed Cu/Sn microbumps on 10 μm pitch.

A key technological challenge facing the 3D integration of heterogeneous semiconductors is the formation of high density metal interconnects between dissimilar substrates, such as compound semiconductors (CS) and Si. Due to the difference in the coefficients of thermal expansion (CTE), one can expect: 1) some misalignment between microbumps fabricated on the CS substrate and the Si substrate during bonding at an elevated temperature; and 2) bond interconnects will experience shear strain as the bonded die pair is cooled to room temperature and during any subsequent thermal excursions.


To estimate the magnitude of the misalignment, they calculated the relative change in distance between corner microbumps in a 10 μm pitch 640 × 512 array on CS die vs. Si die. Operability was determined by electrical testing of long daisy-chains of bumps.

The average channel yield was approximately 97% for both InP-Si and Si-Si die pairs translating into the array operability greater than 99.99%. The reliability of InP-Si and SI-Si die pairs was compared after 500 thermal cycles of -40 – 125 C. No significant change in yield was seen for the homogeneous Si-Si die pairs. The InP-Si die pairs that were underfilled showed a 2.8% decrease in channel yield whereas those not underfilled showed a 13.9% decrease.


They conclude that Cu/Sn micro bumps can be successfully and reliably used for integration of InP and Si die.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…