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IFTLE 213 What’s New in Permanent Polymer Dielectrics: Dow, HD Micro, Zeon

By Dr. Phil Garrou, Contributing Editor

It’s been awhile since we looked at what is new on the dielectric market so we checked with a number of dielectric suppliers and asked what was new in their product lines.

Dow Chemical

The old Rohm & Haas organization has been running the Dow Electronics Materials business for a while now, basically since they were acquired by Dow. I knew they would do well when I observed them make the ill advised low-K SILK product quietly go away.

They certainly have beefed things up in the BCB product line as follows.

  • Toughened BCB has been developed with 3X the elongation at some expense to CTE
  • A Dry film grade is being developed with thicknesses up to 100um
  • A positive-tone, aqueous developable product, BCB, 6505 is fully commercialized
  •  A BCB based temp bond adhesive, XP-130215,  for wafer thinning and 3D stacking is being sampled

I have compared the properties of a few of these new products to standard photo BCB 4000 below.

Property Cyclotene 3000/4000 Cyclotene 6505 (aq dev) Toughened BCB  BCB Dry Film
Cure temp (˚C) 210-250 210-250 210-250   200-250
Tg 350 350 350   250
Dk 2.7 3.2 2.7   2.6
CTE (ppm) 42 45 70   63
Tensile Strength (Mpa) 87 99 93   80
Elongation (%) 8 13 25   13
Residual stress 28 29 24   28
H2O uptake (%) 0.25 1.1 0.3   0.1


The PI community has not been standing still either. PIs always known for their high temp stability and their superior mechanical properties has had some catching up to do when it came to curing temperature amongst other properties.

HD Micro offers the following product lines.

C-4 flip chip RDL layers:

–        HD 4100 negative tone photo PI

–        HD8800 positive tone photo PBO

–        HD 8900 positive tone low cure temp photo PBO

2.5/3D Adhesives:

–        HD 3000 non photo temp adhesive

–        HD 7000 photo PI permanent adhesive

Stress Relief and Passivation Layers:

–        PI 2545 non photo wet etch PI

–        HD 8800 positive tone photo PBO

–        HD 8900 positive tone photo PBO low cure temp

Properties of these materials are compared below:

fig 1


Zeon is introducing the new positive tone photo “olefin based” Zeocoat  CP 3010 designed to deliver a low cure temp, low stress coating. Below are the properties of the polymer determined after a 180 C cure.

Property Zeocoat CP3010 (cured at 180 C for 1 hr)
Water Abs (ppm)

(130 C;98%RH;100 hr)

Mod (GPA) 2.9
CTE (ppm) 51
Stress (MPa) 23
Tensile Strength (MPa) 97
Tg ( C) 196
Dielectric constant (1MHz) 2.9
Leak current (A/cm2) @2 MV/cm 1.0 e -10
Breakdown Voltage (MV/cm) 6.5


For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 212 A Little More Patience Required for 2.5/3D

By Dr. Phil Garrou, Contributing Editor

There is an old proverb that states “All things Come to Those Who Wait.” It is exemplified by the French cartoon (below) showing a cat patiently waiting for a mouse to exit his hole in the wall. I personally am not the waiting type wanting to get things done ASAP but most civilizations look at patience as a virtue.

fig 1

We’ve discussed the leading edge before. The leading edge is where the money is made. So while you don’t want to be too early, you certainly don’t want to sit back and wait to see if something is going to happen and let others drain all the profit from that early period of introduction.

Now having said that, let me counter by saying that “All things don’t come to those who wait”. I waited for thin film  MCMs to take off in the 90’s and early 2000’s and they never did.  A lot of us gambled and in that case – lost. Life is a gamble !

TSV technology and 2.5/3D has had its own  dichotomy. We couldn’t sit back and allow others to get there first so we all anteed up our time and money without any assurance that there is big money to be made on this technology. Like the cat, we have been waiting (some more patiently than others) for 2.5/3D to enter HVM when in fact there has been no assurance that the mouse wasn’t going to exit from another wall (i.e another technological solution as happened in thin film MCMs).

Anyone who understood what TSV technology could bring to the party, knew that HVM and actually new product design itself could not expand until foundry technology was available (since TSV were/are clearly going in during chip fabrication) and memory stacks were available, since foundries don’t make DRAM. Of course it all has to be at the right price, but if its not even available, what matters the price?

In terms of foundries TSMC [see: IFTLE 122, “TSMC officially ready for 2.5D….”, ] was the first to announce and GlobalFoundries is not far behind [see; IFTLE 142,  “GlobalFoundries 2.5 / 3D at 20nm…” or IFTLE 164, “Semicon Taiwan contd: GlobalFoundries Manocha Interview”  ] so those at the leading edge can now design in 2.5D. But what about memory ??

While UMC [see: IFTLE 135, “UMC / SCP Memory on Logic…” and a few others have made noise about entering the 3D market space they appear to be significantly further behind.

The status of memory

Memory, as IFTLE has noted several times, has been slower coming.

The DRAM industry has been undergoing significant consolidation in the last few decades. The recent acquisition of Elpida by Micron has left 3 major players in the DRAM business as shown below.

DRAM Mkt Share of the Big 3 [Source: Gartner 2014]

DRAM Mkt Share of the Big 3 [Source: Gartner 2014]

Moving forward the main roadmaps for DRAM suppliers all address: (1) reduce power consumption, (2) satisfy bandwidth requirements and (3) satisfy density requirements , all while maintaining low cost.

With DDR architecture running into a brick wall the memory suppliers have been focusing on new architectures that will deliver lower power, higher bandwith memory solutions.  These include wide IO-2, HBM (high bandwidth memory) and HMC (hybrid memory cube).

Definition, standardization and scale up of these memory technologies has simply taken longer than any of us would have liked, but these are the new architectures what will take advantage of TSV stacking technology.

TSMC has recently compared the different memory architectures relative to DDR and one another  in terms of bandwidth vs power and price.

Memory Architectures vs bandwidth, power and price. [TSMC]

Memory Architectures vs bandwidth, power and price. [TSMC]

I compare the technologies below.


Memory Std

Bandwidth        (GBps)




Wide IO 2



JESD 229-2

High end smart phones




HMC consortium

High end servers, networking, graphics


128 (gen 1) 256 (gen 2)



High end graphics, networking and HPC

Comparison of New Memory Architectures

As we head into the fall of 2014 the last probably most important of the big 3 memory suppliers, Samsung,  has now announced production of TSV based memory stacks [see: IFTLE 209, “Samsung announces TSV based DDR4 ….” ].

So we are about to have HBM for graphics modules, wide IO-2 for mobile products and HMC for HPC and high end servers. Now there can be no more excuses.

Within the next 18 months, if we do not see product introductions announced,  2.5/3D will begin to fade away until it is only remembered as another one of the bad bets we made attempting to stay on the leading edge…

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 211 Semicon Taiwan part 2: Unimicron, Yole, Micron

By Dr. Phil Garrou, Contributing Editor

Continuing our look at 2014 SEMICON Taiwan.


YH Chen of Unimicron addressed “Panel Level Embedded Substrate Technology.”

Unimicron puts forth a proposal that embedded packaging saves cost because it (a) decreases the substrates used,(b) decreases the area of HDI board needed, (c) better electrical performance due to the proximity of the chips.

Unimicron 1


Unimicron started embedded passives technology (EPS) in 2009 and moved to HVM in 2012. This is based on burying MLC (multilayer caps).

Buried chip technology called EAS has the following roadmap:

unimicron 2

They are also looking at embedded hea “slugs” to increase thermal performance.

Line Embedded technology (LE) uses lasers to creat fine fetures that are then plated up and CMPed to give L/s as low as 8/8um.

unimicron 3

In another cost reduction development project, they are looking at combining the non organic interposer and the organic substrate into what they call “flip chip embedded intrposer carrier” as shown below.

unimicron 4

Yole Developpement

Azemar of Yole Developpement looked at “Fan-out & Embedded Dies Technologies and market trends.”

Azemar explained again that 2 different approaches are developing for Embedded packages, i.e. FOWLP based on reconfigured molded wafers and embedded die based on PCB laminate materials and infrastructure.

Currently Nanium and StatsChipPAC hold > 80% of the FOWLP market though this is expected to change when TSMC fully enters the market with their InFo-WLP technology.

yole 1

A generic embedded die packaging flow is shown below.

yole 2

For embedded die packaging, a new supply chain is required since the die embedding will be done by the PCB manufacturer who is making the substrate.

AT&S appears to hold ~ 80% of the embedded de market. They initiated this space with the TDK DC_DC converter package but Yole reports very little HVM since then.

yole 3


At the CFO Executive Summit Strohbecke of Micron  looked at “Micron Technology and the Changing Dynamics of the Memory Semiconductor Industry: Their 2014 vs 2018 assessment of DRAM demand vs application shows an increase in mobile and server/networking at the expense of PC memory.



For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 210 IBM Global Foundries reaching closure?; Semicon Taiwan 2014 part 1: Hitachi Chem & SPIL

IBM / GlobalFoundries – On Again ??

When last we discussed the soap opera that is called the IBM Global Foundries negotiations, I confirmed that IBM was actually paying for GF to take the semiconductor operation (which has been losing ~ $2B/yr) off their hands.

Since then the media had announced that the deal was off. But this made no sense, IBM had gone to far and their Semi employees would be leaving on their own since this was no longer a site to develop a semiconductor manufacturing career. Indeed GF began hiring IBM employees.

On 9/19, the Poughkeepsie Journal reported that “a source involved in the negotiations” indicates that “they are headed to arbitration as early as next week in the latest effort to strike a deal for IBM to sell its semiconductor manufacturing operations.”

SEMICON Taiwan 2014

SEMICON Taiwan is always a gathering that produces Major packaging announcements.

The Advanced Packaging Technology Symp was chaired by C. S. Hsiao, Vice President, Engineering Center, SPIL.

The SiP Global Summit and 3D Technology Forum was chaired by CP Hung VP of corporate R&D for ASE and DC Hu Sr VP of R&D and new business development for Unimicron.

CP Hung DC Hu


Hitachi Chemical

Toba of Hitachi Chemical described their embedding insulation sheet (EBIS) for FOWLP and FCCSP. The process flow for FO WLP is shown below using PBO ( HD 8940 ) as the RDL dielectric.

hitachi Chem 1


Proper  EBIS CTE and modulus and/or  die thickness was shown to reduce warpage by as much as 60%.

EBIS was also used for FC CSP packaging:

hitachi Chem 3


Using EBIS as a laminated MUF replacement (mold and underfill) resulted in center voids in the package. Compression molding was necessary to achieve void free structures.


M Lu of SPIL addressed “The Next Wave of 2.5D Applications”.

As IFTLE has stated in the past, the composition of future interposers will depend on the density requirements of the applications. Right now the only technology available to satisfy “G1” requirements is silicon substrate technology.



SPIL has optimized the following processes in order to be able to address this market space.

spil 2


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…


IFTLE 209 Samsung announces TSV based DDR4; What is Intel eMIB?; Amkor says the wait for 3DIC is not over yet

By Dr. Phil Garrou, Contributing Editor

Samsung finally announces commercialization of TSV based DDR4

IFTLE has been reporting for awhile that a Samsung announcement of stacked memory based on TSV technology was imminent. [ see IFTLE 123 “Intels Bohr on 3DIC;Samsung DDR4 roadmap…” especially since similar announcements have already come from Micron and Hynix.]

On Aug 26, Samsung finally announced that it has started mass producing 64 GB DDR4, dual Inline memory modules (RDIMMs) that use 3D TSV technology. The new memory modules are designed for use with enterprise servers and cloud base solutions as well as with data center solutions [link]. The release is timed to match the transition from DDR3 to DDR4 throughout the server market.

Samsung has started operating a new manufacturing line dedicated to TSV packaging, for mass producing the new server modules. The new RDIMMs include 36 DDR4 DRAM chips, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dies. The low-power chips are manufactured using Samsung’s most advanced 20-nanometer (nm) class* process technology and 3D TSV package technology.

The new 64GB TSV module reportedly performs twice as fast as a 64GB module that uses wire bonding packaging, while consuming approximately half the power.

Samsung believes that in the future it will create even higher density DRAM modules by stacking more than four DDR4 dies using 3D TSV technology.

Samsung has been working on improving its 3D TSV technology since it developed 40nm 8GB DRAM RDIMMs in 2010 [see IFTLE 65, “Samsung’s 32GB RDIMM DDR3…” ], and 30nm 32GB DRAM RDIMMs in 2011 using 3D TSV.

Fig 1

Amkor’s Liang says 3DIC will take another 3 yrs to get to HVM

At a press event held prior to the official opening of Semicon Taiwan 2014, Mike Liang, president of Amkor Technology Taiwan, announced that “demand of 3D ICs may take another 3 years due to concerns of high production costs.” He added that “…at present, only a few specific applications that require extremely high performance ICs require the use of 3D ICs, but the amount of such 3D ICs is not sufficient enough to support a full production line.” I’m sure this served to pour cold water on the subsequent 3DIC tech forum!

Intel Announces Embedded Multi die Interconnect (EMIB)

Intel recently announced that a new technology “Embedded Multi-die Interconnect Bridge” or EMIB will be available to 14nm foundry customers [link].

They claim it is a “… lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package.” While neither Intel nor any initial press reports gave any indication of exactly what this means.

It is highly likely that this is tied to the issuance of patent application publication US 2014/0070380 A1 published March 13 2014 [link].

In simplified form interconnect bridges (“silicon glass or ceramic”) are embedded in a laminate substrate and connected with flip chip as shown below:

Bridge Interconnect as described in recent Intel patent.

Bridge Interconnect as described in recent Intel patent.

A cross section of the package is more revealing showing connections through the laminate and connections through the bridge substrate (316) which would be TSV in the case of a silicon bridge substrate. The underside of the bridge substrate (314) may be connected to another bridge substrate for further interconnect routing as shown below.

While there is no silicon interposer, there do appear to be TSV in the embedded interconnect substrate as shown below. While removing complexity from the IC fabrication by eliminating TSV from the foundry process, the packaging operation becomes much more complex.

Since the 2.5D interposer has been reduced in size to the interconnect bridges, this may reduce cost, but will increase signal length vs a true 3D stack or a silicon interposer 2.5D

Intel EMIB Module in Cross Section

Intel EMIB Module in Cross Section

While Intel released the following description: “Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed,” IFTLE thinks this is somewhat misleading.

The packaging analogy to what they have done is as follows:

A high density bumped chip could be put down on to a high density build up PWB,  but in most cases the high density bumped chip is placed on a smaller BGA substrate which is then put onto a lower density, lower cost PWB.  The latter is the lower cost solution. In this case, large expensive high density interposers are avoided, and the much smaller emib are used for the high density interconnect. It will be interesting to see what if any the cost differential will be here.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 208 ECTC part 3: Thermal Compression Bonding – STATS, Toray, Qualcomm

By Dr. Phil Garrou, Contributing Editor 

SCP Status

Before we continue our look at key papers from the 2014 IEEE ECTC Conference, the latest on the potential sale of STATSChipPAC (SCP). In June SCP, announced  that it ended talks with one party (thought to be ASE) while discussions with other potential bidders were continuing.

Bloomberg now reports that the Chinese chip-testing companies Jiangsu Changjiang Electronics Technology and Tianshui Huatian Technology are considering bids for SCP and that a deal for SCP, valued at ~ $ 1B could be reached early next month.  [link].

Semiconductors have been labeled a  “strategic industry needed for China’s economic development and national security” by the Chinese Govt. China announced increased financial support for the industry and plans to set up a national investment fund according to Bloomberg.

Continuing our look at key papers from the 2014 IEEE ECTC conference

Thermo-compression Bonding

The advent of 2.5 and 3DIC has caused revisions in the way area array bump interconnect is carried out. The packaging hierarchy has traditionally been for BGA balls (~ 500um) to connect packages t boards and for C4 bumps (100-150um) to connect chips to packages.

Chip stacking with requirements for tighter pitch would prefer to have copper to copper connection, but such thermo-compression bonding currently requires 350-400C, 200kPa and most importantly 30+ minutes which makes high volume manufacturing impractical. Therefore the industry has adopted the   micro-bump and the copper pillar bump for such mating.

Sematech has put out the following cartoon to show approximately when technologies have to be changed based on required pitch.



Most OSAT roadmaps show that standard solder reflow can be used down to ~ 40um after which compression bonding must be used to avoid shorting.



A closer look at these mucro bumps (see below) usually reveals a Ni barrier layer on a copper pillar capped with Sn/Ag solder.



Such fine pitch connections make it difficult to underfill and have driven the refinement of pre applied underfills [both film (called non conductive film, NCF) and paste (called non conductive paste, NCP) ]. These technologies only work when one has good manufacturing control over both solder reflow and underfill cure.

Let’s look at some issues concerning such interconnect that came up during ECTC 2014.


Y. Jeong detailed the “Optimization of Compression Bonding Processing Temperature for fine pitch copper column devices.”     They examined thermal compression with non-conductive paste which they call TCNCP. The heat transfer from heating source to bumps must be tightly controlled in order to achieve the optimized bump temperature for the purposes of melting and soldering. To minimize voiding issues such as air entraps, a very short time window for curing has to be used in the NCP process. They determined the key parameters as shown below.



They concluded that “to have a successful bond, one of the most important keys is to obtain an optimized temperature profile which considers the ramp up/down speeds and times. The ramp up/down speeds and times affects the NCP flow behavior, void creation, and residual stress of the final product. In this regard, the peak and dwell time shall be precisely controlled to provide enough time for melting and soldering of bumps with substrate pads.”


Y. Liu of Qualcomm examined “Filler entrapment and solder extrusion in 3DIC Thermo-compression uBumps.”  Qualcomm indicates that filler entrapment could negatively impact electromigration in the solder joint.

The main reason for filler entrapment is reported to be premature cure of the pre-applied underfill caused by not fully optimized process condition and/or bump geometry. Once curing initiates, solder wetting is no longer able to push out filler and underfill from the joint due to the increased viscosity of underfill.

They also find solder extrusion from the side of the ubumps and conclude through examination of large arrays of bumps that the extrusion appears to be random.




T. Nonaka of Toray described “High Throughput thermal compression NCF Bonding.”  Torray points out that thermo compression bonding suffers from throughput issues because of the process flow shown below which requires the bonding head to cool between chip placements.



They propose a logical process change where the die are all placed and then cured and reflowed at once (gang bonded) as shown below.



For all the latest in 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 207 IEEE ECTC part 2: Advances in Fan-out Packaging

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the “Fan Out” papers that were presented at the 2014 ECTC.

STATSChipPAC (SCP) and the totally encapsulated WLP

Tom Strothman from SCP presented an update on their fan-out technology to produce fully encapsulated WLPs. Strothman reminded us that the WLP was invented, patented and commercialized by Flip Chip Technologies (FCT) in 1998 when they released the “Ultra CSP”. Tom was part of that FCT team along with Pete Elenius.  I recall that well, since I was at Dow Chemical in those days working with FCT on the program with my team which included current industry veterans Boyd Rogers and Andy Strandjord.

Luu Nguyen, then at National Semi, and a licensee of the FCT technology  was the first to coat the backside of the WLP with a layer of molding compound both for protection and to enable laser marking.

SCP has now taken this to the next level by developing their eWLCS (an acronym I assume for Wafer Level Chip Scale)  which is the only WLP to offer protection on all sides of the package.

The process starts with a high volume manufacturing flow developed by STATS ChipPAC for fan-out products. In this manufacturing method the wafer is diced at the start of the process and then reconstituted into a standardized wafer (or panel) shape for the subsequent  process steps. The basic process flow for creating the reconstituted wafer is shown below. The singulated die are accurately placed face down onto the carrier with a pick and place tool. A compression molding process is used to encapsulate the die with mold compound while the active face of the die is protected. After curing the mold compound, the carrier and adhesive foil are removed in a de-bonding process resulting in a reconstituted wafer where the mold compound encapsulates all exposed silicon die surfaces.

After the reconstitution process, the reconstituted wafer is processed with conventional wafer level packaging techniques for the application and patterning of dielectric layers, thin film metals for redistribution and under bump metal, and solder bumps. In the final dicing operation a thin layer of mold compound, typically < 70um, is left on the side of the die as a protective layer as shown below.


One would assume that the process flow shown above would have higher cost since there are additional steps required for reconstitution at the start of the flow. SCP contends that there are two key factors that offset the cost of the additional steps. 1) In the case of the 300mm reconstituted panel used here the cost is very competitive for silicon wafers with a diameter of 200mm and below. SCP claims the cost of processing a 300mm reconstituted panel is approximately 1.7x the cost of processing a 200mm silicon wafer in WLCSP, however the units per panel (wafer) increases by a factor of 2.3x, effectively offsetting the cost of reconstitution. 2) Since known good die can be selected at the start of the process, advanced devices that have a lower electrical yield can be tested in wafer form prior to the process. If the incoming wafer has a probe yield of 85%, then 15% more units per reconstituted panel can be processed to offset the cost of the reconstitution process.

Since the reconstituted panel size is no longer linked to the incoming silicon wafers size, the panel size can be increased over time and provide further cost reduction.

Because of the presence of molding compound, the RDL on these structures cannot use the typical PI, BCB or PBO dielectrics, but rather must use a as yet unnamed low temp cure material.

TCT (thermal cycle tsting) passes 500 cycles ( -4o to 125 C) and drop testing passes the JEDEC 30 drop requirement.

Siliconware (SPIL) panel fan-out packaging (P-FO)

Chang of SPIL discussed their efforts to commercialize he panel fan-out package concept  by combining  PCB, semiconductor back-end, semiconductor WLP and LCD Gen 2.5 glass processing technologies. This effort requires high accuracy die bonding and die shift compensation at film lamination, lower warpage sheet form film lamination, good copper trace plating uniformity control at large panel area and also precise photolithographic technique.

Known good die are reconstructed on the LCD Gen 2.5 (370X470mm) size glass carrier with adhesive temporary bonding material.

Processing issues are identified as warpage, die shift “coordinates compensation at lithography” and Cu plating uniformity.

They claim that warpage can be controlled to +/- 0.5mm after carrier debonding. They describe die shift compensation as a “compensable patterning method” which is not described but probably is similar to techniques recently described by Deca [see “Adaptive Patterning for Panelized Processing”]

Little detail is given on how they are going to achieve these requirements.

Nanium – eWLB Dielectric Selection

In eWLB technology  the reliability of the package is a balance of the capability of the different layers that constitutes the package in absorb shocks and mechanical stress from the different materials CTEs. In IC packaging interfaces, the dielectric material, plays a significant role absorbing thermal stress and mechanical shocks slowing down cracks propagation. A wide range of material classes has been considered including PBO, PI, nano-filled Phenol resin, BCB, Silicone, Epoxies, Siloxanes ,  Polynorbornenes and Acrylates. Fifty six56  dielectrics from seventeen manufacturers were compared based on physical, mechanical, thermal, electrical and chemical properties.

They found the most significant material properties are the elongation to break, the tensile strength and the Young’s modulus as they are an indicator of how a polymer will perform under mechanical stress caused by CTE mismatch between the die and the molding compound in thermal cycling and in mechanical shock drop tests.

A PI precursors formulation was selected based on its low curing temperature compatible with eWLB FO-WLP products and processing temperature restrictions. The unidentified PI precursor formulation is NMP/NEP solvent free. It is compatible with copper and all the other chemicals used in production process like solvents, bases and acids. Thus, the PI precursor formulation was selected to be used as buffer layer and also as RDL top layer.

Use of this dielectric reportedly allow  NANIUM to exceed 1,000 cycles in component level based Temperature Cycling Test (TCT -55ºC to 125°C) and 500 to 1,000 cycles, in board-level based Temperature Cycling on Board Test (TCoB -40ºC to 125 °C) according IPC-9701 and JEDEC JESD22-B111 Drop Testing.

Google / Novartis – Wearable electronics for diabetics ?? 

Google and Novartis, announced that  they will create a smart contact lens that contains a low power microchip and an almost invisible, hair-thin electronic circuit. The lens can measure diabetics’ blood sugar levels directly from tear fluid on the surface of the eyeball. The system sends data to a mobile device to keep the individual informed.



The Mountain View CA Google team involved in this program is the stealth  “Google X” group which focuses on “finding new solutions to big global problems” in healthcare and other areas.

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 206 COSMOS and DAHI Herald the Era of 3D Heterogeneous Integration

By Dr. Phil Garrou, Contributing Editor

For about a decade now, we have been awaiting the full commercialization of 3DIC. From the beginning most practitioners laid out a roadmap where CMOS Image sensors led the way followed by memory stacks, memory-on-logic, logic on logic and lastly the holy grail of heterogeneous integration where we could combine advanced semiconductor materials and different  functions, with high-density silicon CMOS technology.

Indeed CMOS image sensors have led the way [ see IFTLE 199,  “Omnivision Roadmaps 3D stacking for CMOS Image Sensors…” ] and DRAM memory stacks from Hynix and Micron are on the verge of full commercialization [ see IFTLE 202, “ConFab 2014: Novati, Lumileds; Chipworks; IEEE CPMT Packaging Panel”].

A lesser publicized fact is that we are actually very close to functional heterogeneous integration thanks to the efforts of many participants in the DARPA sponsored COSMOS and DAHI programs.

The development of non SI based semiconductor (compound semiconductors, CS) electronics has been motivated by their superior materials properties relative to silicon. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with fmax above 1THz. The wide energy bandgap of GaN has enabled large voltage swings as well as high breakdown voltage RF power devices and the excellent thermal conductivity of SiC makes tens of kilowatt-level power switches possible [1]

[1] S. Raman, “The DARPA Diverse Accessible Heterogeneous Integration (DAHI) Program: Towards a Next-Generation Technology Platform for High-Performance Microsystems”, 2012 CS Mantech Conf.

DARPA proposes  that the future of CS electronics depends not on displacing Si, but rather on heterogeneous integration of compound semiconductors with silicon technology in a way that will take advantages of the two technologies when combined.

Past attempts at heterogeneous integration has been at the module level, i.e Multichip Modules [see “Multichip Module Technology Handbook” , P. Garrou, I Turlik Eds., McGraw Hill, 1998].

However, MCM techniques have been limited by I/O parasitic effects between chips in such modules and by device and interconnect variability issues. Many of the limitations including I/O parasitics and phase mismatch are governed by the length of separation between CS and Si CMOS devices, and as such, reduction of this separation is expected to yield dramatic improvements in performance of heterogeneous integrated circuits.

The COSMOS [ Compound Semiconductor Materials on Silicon] program began in 2007 with teams led by Northrup Grumman, Raytheon and HRL (Hughes Research Labs).  They have demonstrated three different approaches (see below) to achieving InP BiCMOS integrated circuit technology featuring InP HBTs and deep submicron Si CMOS for RF and mixed signal circuits.



The Northrop Grumman technology starts with a completely fabricated standard CMOS wafer. A separately fabricated InP HBT wafer (thinned to approximately 55u m) is mounted to a glass carrier. An InP wafer is etched to form individual chiplets (still attached to the carrier wafer). The CMOS wafer is prepared for integration with the InP chiplets by depositing gold (Au) micro bumps (3-10um and 2um thick). The glass carrier containing the singulated InP chiplets is then aligned to the CMOS wafer, and the bonding operation performed using standard wafer bonding equipment with controlled time, temperature, and bonding force. The glass carrier wafer is then released, leaving the singulated InP chiplets connected to the base CMOS wafer. This is shown schematically below.



DARPA is also pursuing the integration of GaN transistors with Si CMOS on a Si substrate.  For example. the Raytheon team has recently demonstrated a monolithically integrated RF amplifier circuit  using heterogeneously interconnected GaN HEMTs and pMOS gate bias control (see below).

Raytheon GaN


DAHI (Diverse Accessible Heterogeneous Integration)  initiated in 2013 is based on its predecessor COSMOS and is composed of several design, technology and manufacturing thrusts including :

  • Si CMOS for highly integrated analog and digital circuits
  • GaN for high-power/high-voltage swing and low-noise amplifiers
  • GaAs and InP HBT and HEMT for high speed/low-noise circuits
  • Compound semiconductor optoelectronic devices for direct-bandgap photonic sources and detectors, as well as or silicon-based structures for modulators, waveguides, etc.
  • MEMS components for sensors, actuators and RF resonators
  • Thermal management structures

Program teams include:

  • Teledyne/Tezzaron/UC Santa Barbara
  • MIT/Raytheon/Stanford
  • IBM/Columbia U/MIT/Veeco
  • NG/Novati/Nuvotronics/MOSIS/ON Semi
  • HRL/ UC San Diego/U Mass/U FLA
  • Raytheon/Novati/IBM
  • Rockwell/Tower Jazz/UCSD

At the recent DAHI program review in Boulder participants shared their technology progress to fabricate multilayer circuit structures (i.e InP, Si, GaN) on substrates such as SiC using 3DIC technologies such as TSV and oxide-oxide bonding.

The  goal of DAHI is to establish a manufacturable, accessible foundry technology for the monolithic heterogeneous co-integration of diverse (e.g., electronic, photonic, MEMS) devices, and complex silicon-enabled architectures, on a common substrate platform for defense and commercial users. By enabling the ability to ‘mix and match’ a wide variety of devices and materials on a common silicon substrate, circuit designers can select the best device for each function within their designs.  This integration would provide DoD systems with the benefits of a variety of devices and materials integrated in close proximity on a single chip, minimizing the performance limitations caused by physical separation among devices.

As these technologies become public, IFTLE will keep its readers apprised of the results.

For the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 205 2014 ECTC part 1: Controlling Warpage in Advanced Packaging

By Dr. Phil Garrou, Contributing Editor

We are a bit out of chronological sequence, but as usual the ECTC was chuck full of materials worthy of coverage. Since the presentation is in six parallel sessions it takes time to go back and read all of them, and, since the papers are published in IEEE Explore, I do not have the power point presentations to summarize for you.

Let’s start off with some papers concerned with warpage issues.

Hitachi Chemical

As we continue to miniaturize, warpage remains the main problem encountered in all areas of advanced packaging. Kotake of Hitachi Chemical addressed “Ultra low CTE core materials for next generation thin CSPs” They describe ultra low CTE (1.8) core materials (E-770G) which are used to reduce warpage in PoP packages. Hitachi simulations show that the CTE of core materials has more impact that the modulus.

Hitachi 1


Best results are obtained when using the new material E-770G for both core and prepreg.


Kim and co-workers at Amkor reported on “Strip grinding Introduction for thin PoP.” Typical PoP used in mobile products consists of a logic function In the bottom package and a memory function in the top package. The most difficult barrier to fabricate the thin PoP is warpage control. Amkor TMV (through mold via) PoP structures can be overmolded or exposed die (to allow for heat sinking). When trying to thin the package, there is a limit to the  thinness of the overmold and a limit to the silicon die thickness since thinner die result in die chipping or cracking during handling. In the thin mold cap case, it’s not easy to control the package warpage. The warpage can be controlled with a thicker substrate, but this increases the package thickness.

The concept of strip grinding is to grind the mold compound and die together. The advantage of strip grinding is to use normal die thickness and mold cap thickness, thus reducing the risk of thin die handling and narrow mold clearance. Mold flash is eliminated through the grinding methodology. By applying a strip grinding process, we can easily generate a very thin die and mold cap.

amkor 1


Double side molded structures are possible, which help make a balanced structure on top and bottom which tends to improve the warpage performance. Bottom side mold is difficult, because the BGA ball is mounted on the bottom area.

For the double-sided mold process flow, chip attach on the top side and BGA ball attach on the bottom side need to be done first followed by double side mold. The bottom molding is ground until the bottom ball is exposed. To remake a BGA, a second ball attach needs to be performed to generate a proper BGA standoff.

amkor 2


Warpage simulations were done for a variety of die/substrate/mold thicknesses, as shown below.

amkor 3


Warpage is minimized when (a) thin die is double-side molded, i.e leg 6; (b) very thin die i.e leg 3 or (c) thick substrate to balance mold, i.e leg 1.


Bchir of Qualcomm discussed “improvement of substrate and package warpage by copper plating optimization.”

While substrate warpage is typically approached through modification of dielectric material properties (such as CTE, Tg, modulus), layer thicknesses (core, prepreg, solder resist and Cu thickness), and Cu areal density per layer there is also an impact from the Cu plating process. Electroplated Cu thin films have porous grain boundaries, wherein grain boundary volume is strongly dependent on electroplating conditions and subsequent thermal processing.  During thermal processing, Cu grains grow and merge, eliminating grain boundaries and causing shrinkage. The residual stress in the initial deposit, coupled with shrinkage during subsequent thermal processing, strongly impacts the warpage of the substrate and package. This is compounded by the inherent front-to-back Cu density imbalance which is typical in substrate design.

Choice of electrolytic Cu plating solution has significant impact on the magnitude of package warpage. The influence of Cu plating solution on warpage is related to the resulting grain size distribution and stress state deposited from a given chemistry. Plating additives can be co-deposited as impurities into the Cu layer, and have been shown to strongly impact residual stress and grain coarsening behavior of the Cu deposit.

They found that reducing the plating current density for a given plating solution led to substantial reduction in package warpage. Also,  an increase in the plating current density causes a reduction in the deposited grain size, hence a reduction in current density would lead to larger deposited grains and thus larger grains would mean reduced grain boundary volume, less “shrink” in the Cu layer and lower residual stress in the Cu.


Eric Beyne’s group at IMEC detailed their work on “Minimizing Interposer Warpage by Process Control and Design Optimization.” Imec’s silicon interposer technology consists of 10×100μm TSV, four thick damascene BEOL layers, Cu bumps and redistribution layers (RDL) front side and back side.



They calculated and measured 300mm wafer bowing at different stages of interposer BEOL processing, as shown below. There is good agreement between simulation and measurement. For a 10mm x 20mm interposer, bowing is measured as 30um (short side) x 130um.



Bowing mitagation was investigated by:

–  Replacing standard Pre-Metal-Dielectric (PMD) layer by a thicker and more compressive insulator

– The use of thinner Metal1 and Metal2

– The use of a more compressive oxide in the BEOL

– Replacing the standard PMD layer (300 nm/80 nm SiO/SiC layer) by a thick PECVD oxide with -170 MPa compressive results in a bow reduction of around 150 um (-37% bowing).

At die level,  bowing value of around 45 μm (-59% bowing) is predicted by the model for a 20 x 20mm  interposer.



The use of thinner Metal1 and Metal2 will increase the sheet resistance of the two layers and consequently may impact the electrical performances of the interposer. The figure below shows that reducing the thickness of M1 and M2 effectively reduce the bowing and that a thickness of around 0.4μm could be a good trade-off between bowing and performance decreases.



Small modification of the stress of the oxide can be very efficient to decrease the bowing at wafer but also thin die level.



They conclude that “the use of a more compressive and thicker PMD insulator layer, a reduction in Metal1/Metal2 thickness, the use of more compressive oxide within the BEOL, are promising and easy to implement solutions to reduce interposer bowing with a limited impact onto its performances.”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 204 IBM / GF Semi Deal: the drama continues; Leti Studies Monolithic 3D

By Phil Garrou, Contributing Editor

Reports a week ago indicated that “It appears that IBM’s sale of its microchip manufacturing business to GlobalFoundries had fallen apart.” [link]

The local paper, the Poughkeepsie Journal, citing “anonymous sources with knowledge of the inner workings of IBM”, said the deal had been known under the codename  “Project Next.” Reportedly IBM managers at East Fishkill were told July 15th that the deal to sell its microchip unit to GlobalFoundries was off. The Journal quoted consultants who felt that such a deal would likely need clearance from federal agencies since IBM is a so-called “trusted foundry” for the U.S. military and GlobalFoundries is owned by the government of Abu Dhabi [link].

Perhaps, but…

 Bloomberg reported on Aug 5th that “according to a person familiar with the process”, it was  IBM offering to pay GlobalFoundries to take on IBM’s money-losing chip-manufacturing operations [link].

According to Bloomberg contacts, IBM was offering about $1 billion to entice Globalfoundries to take the unit but  Globalfoundries wanted $2 billion. Recall it has been reported that the IBM Semi business has been losing ~ $1.5B / year for several years.

It is likely that IBM requested GF continue operation of the two facilities to maintain supply of chips that they are using in IBM products. To do so GF would likely continue to incur similar losses and that may have outweighed acquisition of whatever IBM IP was to be included in the deal. IFTLE’s  understanding is that Burlington could be made to operate as an analog / specialty division, but East Fishkill (which reportedly cost $2.5B to build) should just be closed down because it is old and outdated.

With IBM semiconductor employees understanding that their division is no longer wanted by IBM corporate, many are jumping to GlobalFoundries which is actually setting up “job fairs” in the IBM factory communities [link].

It appears to IFTLE that IBM does not have much leverage in all of this, but we will see as the drama continues.

Leti Continues to Study Monolithic 3D

In Dec 2013 Qualcomm, in a move that appeared to show impatience with the development of 2.5/3DIC infrasructure, announced an agreement with CEA-Leti, to assess the feasibility and the value of Leti’s sequential (monolithic) 3D technology. In comparison with 3D-TSV technologies which  stack separate die, sequential 3D technology proposes to process all the functions in a single semiconductor manufacturing flow. Thus, the technology allows connecting active areas at the transistor level, at a very high density as it uses a standard lithography process to align them.

According to Leti, this technology is expected to produce a 50% gain in area and a 30 percent gain in speed compared to the same technology node in 2D. They expect the  sequential 3D technology will be much less complex and expensive to implement than sub 22nm nodes , making this technology a potential alternative to conventional planar scaling.
At the recent Semicon West event in San Francisco, Olivier Faynot, devices department director at CEA-Leti updated the community on their results thus far. According to Faynot the design kit is ready since technology is standard CMOS processing.

Leti 1
As expected, the issues are all thermal due to the sequential processing.

leti 2

It is hoped that advanced laser processing will allow proper dopant activation without disturbing lower layers.

Leti 3


They report that initial results show thermal stability demonstrated up to 500°C at 28nm and 14nm SOI nodes.

Key points ae reportedly silicide stability and dopant deactivation for NMOS.  On going process work includes:

• W implantation    • NiPt deposition    • Silicide formation    • F implantation

• RTP at various durations and T°

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…