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IFTLE 260: IMPACT Taiwan 2015 – Altera, iNEMI, SPIL


The IMPACT conference claims to be the largest gathering of packaging and PCB professionals in Taiwan. It is organized by IEEE CPMT, ITRI, IMAPS Taiwan and the Taiwan Printed Circuit Association. The Technical Chair for IMPACT 2015 is CT Liu, of ITRI.


Charlie Lu of Altera discussed his reasoning for the new term “ViB” to describe Via-interconnect Ball-Grid-Array.

Traditionally we all learned that there are three types of interconnect: WB, FC and TAB. Lu defines ViB as a ball-grid-array package whose chip-to-package electrical interconnect is achieved by direct interconnection through the vias. Some wafer level packages and fan-out packages, he contends, belong to this category.

Traditionally, chip-to-package interconnect is done by wire bonding (WB), flip-chip bonding (FC), and to some extent, tape-automatic bonding (TAB). There are two steps for via-interconnect process: (1) via formation and (2) via filling or via bottom and sidewall metallization. Via formation could be done by laser ablation or photolithography process, or by other techniques. Via filling and metallization is usually done by mixed techniques of Ti/Cu sputtering and Cu or Ni/Cu plating. Thus, the process of via-interconnect technology is unique from that of WB, FCB, and TAB.

Lu compares the interconnect technologies in the table below.


The industry has begun using the term WLP for so called fan in packages fabricated on wafer, “FO-WLP” for fan out packages formed from reconstituted wafers, and “FO-PLP for fan out packages formed by panel level processing. Lu correctly points out that all packages except fan in WLP are FO packages. He prefers the term ViB as a category to cover both FO-WLP and FO-PLP. If it is necessary to spell out the process applied for a given ViB, an additional suffix could be added, like ViB-D, D stands for “dry”, meaning that the ViB is made by wafer Fab-like process. Likewise ViB-W means the ViB is processed by “wet” process, i.e. PCB-like process. It is no longer necessary to emphasize a package is fan-out or fan-in, because WLP already implies itself a fan-in package, apart from WLP, all others are fan-out packages.

Those of you who follow IFTLE closely know I’m a stickler for nomenclature and not a fan of terms like 2.1D which have no real meaning or “interposer” since all packages are interposers. In this case Lu is attempting to clarify the categories and I can see some logic in his presentation. Whether we all pick up on ViB or not in the end will depend on all of you.


iNEMI updated their program on “recent trends in package warpage”. Below we see a comparison of the warpage for various packages with various pretreatments.


  • Dynamic warpage of POP package varies according the construction.
  • There is insignificant dynamic warpage difference between “As I” vs Bake and MET.
  • Majority of the POP package received kept the high temperature warpage below 100um.

POP Memory:

  • There is insignificant dynamic warpage difference between “As Is” vs “Bake” and “MET”.
  • Majority of the POP package received kept the dynamic warpage below 100um.


  • There is no observable dynamic warpage difference between As Is vs Bake.
  • Different Lid attachments can yield different dynamic warpage characteristic.
  • Ceramic substrate with Lid demonstrate similar dynamic warpage behavior as like organic substrate but with lower magnitude for the package size considered.


  • The effect of “Bake” and “MET” on dynamic warpage is more apparent in PBGA package.
  • The “Bake” generally shows lower high temperature while “As Is” and “MET” shows the tendency to elevate the warpage by 20-50um. Take note that this depends on the mold material used.


Max Lu, deputy Director of SIliconware, discussed WLP innovations such as molded WLCSP, Fan-Out WLP and NTI (No TSV interconnection).

Molded WLCSP

Potential for greater board level reliability.

Passes: component level – 1000hr TCT ; 96hr HAST and 1000hr HTS PASS

Board level – 1000x TCT cycle and 30X Drop test.

IFTLE260_fig3Fan Out PoP

Thinner FOWLP results in thinner PoP packages. Passes: component level – 1000hr TCT ; 96hr HAST and 1000hr HTS PASS and Board level – 500x TCT cycle and 30X Drop test.

IFTLE260_fig4No TSV Interconnect (NTI) Platform

SIliconware was one of the first to describe a chips last interconnect technology which they call SLIT (see IFTLE 215, “STATS Acquisition; Will SLIT replace TSV?”).

SPIL proposes the merits of NTI Platform are:

  • Shortening interconnection distance than traditional TSV interposer.
  • Reducing interposer process cost without TSV related process cost.
  • Processing by all existing MEoL/BEoL equipment.

The following shows the unit operations done by SPIL and those done in foundry.


For all the latest in 3DIC and other advanced packaging stay linked to IFTLE…

IFTLE 259: IEEE 3DIC 2015 part 2 – DARPA , Xilinx, Tohoku Univ, IMEC/Samsung, Nikon, Chuo Univ., Torray


In his presentation “Path to 3D Heterogeneous Integration” Dan Green, DARPA program manager described their motivation for heterogeneous integration.

Modern RF systems are under pressure to make use of the spectrum in sophisticated ways, while working within limited power budgets on platforms with reduced size and weight. The compound semiconductor (CS) electronics industry is well-positioned to address these challenges, due to the superior properties and diversity of CS materials. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with fmax above 1THz . Wide energy bandgap GaN has enabled large voltage swings as well as high breakdown voltage RF power devices. The excellent thermal conductivity of SiC makes tens of kW power switches possible. On-chip high-Q micro-electromechanical resonators and switches in materials such as AlN, have been demonstrated that potentially can be used for clock references and frequency selective filters.

The DARPA view is that the future of CS electronics depends not on displacing Si, but rather on heterogeneous integration of compound semiconductors with silicon technology in a way that will allow the advantages of the two technology types to be optimally combined.

The DAHI Foundry Technology thrust was initiated in 2013 to advance the diversity of heterogeneous device and materials available in a silicon-based platform and make this technology available to the greater DoD and commercial microsystems design community through the establishment of an accessible, manufacturable foundry offering for device-level heterogeneous integration. Recently, a DAHI multi-project wafer run was demonstrated utilizing 0.25um InP HBTs, 0.2um GaN HEMTs heterogeneously integrated with 65nm Si CMOS. A chiplet assembly approach was chosen as the primary path at the DAHI Principal Foundry because of reported advantages in flexibility and processing of dissimilar materials.


Xilinx updated the audience on their 2.5D FPGA program. Xilinx has participated since 2006 in 3D-IC technology development. Today there are more than (7) 3D-IC products from 2 generations of FPGA family nodes in shipping to customers. The figure below compares the different technologies available for high density interconnect.

IFTLE259_Fig1 Tohoku Univ

Rittinon and co-workers reported on the stability of electroplated copper thin film interconnect.

The mechanical properties of electroplated copper thin films, such as Young’s modulus and tensile strength vary drastically compared to those of conventional bulk copper. The reason for the variation and fluctuation of these mechanical properties is that the electroplated copper thin films mainly consist of fine columnar grains with porous grain boundaries as shown in the figure below. This micro texture changes the mechanical properties of the electroplated copper thin films significantly from those of bulk copper.

IFTLE259_Fig2The existence of porous grain boundaries is the main reason for the high resistivity and local high Joule heating in the electroplated copper interconnections. Therefore, the crystallinity of the electroplated copper thin-film interconnection has significant effect on the long-term reliability of the interconnections. They find that high Joule heating appears at grain boundaries with low crystallinity.

It is well-known that the crystallinity of electroplated copper interconnections is improved by high temp annealing. Since recrystallization and/or grain coarsening occurs during annealing, however, high tensile stress remains in the annealed interconnection because the shrinkage of the film is strictly prohibited by the surrounding silicon in a TSV structure. Such high tensile stress is the main reason for stress-induced migration in the interconnection resulting in the formation of a lot of voids in it.

Since the lattice mismatch between tantalum (the Cu migration barrier layer) and copper is about 18%, these researchers feel it is necessary to introduce an intermediate layer as the seed layer material between them. They report that a thin layer of ruthenium is an effective material for minimizing the lattice mismatch. It decrease the lattice mismatch from 18% to 6% thus lowering the overall stress formation.


It has been known for several decades that low temp oxide wafer bonding can be enhanced by plasma treatment of the oxide surfaces by process flows such as the one shown below.

IFTLE259_Fig3Researchers at IMEC and Samsung have now studied the potential for low temp bonding by dielectric films other than SiO2. The figure below shows the results of the surface roughness and bond strength measurements for SiOx, SiOxNy and SiCxNy surfaces that were treated with O2, Ar or N2 plasmas. Among those three dielectric films, the SiCxNy film had the best bonding strength in the same low temperature annealing condition for 2h at 250°C.



Sugaya and co-workers reported on a new “precision” wafer bonding technology for 3DIC. The technology includes a new precision alignment methodology and a unique thermo-compression bonding procedure. Experimental results show that the alignment capability is 100nm or better, and permanent bonding accuracy of 260 nm (|mean| + 3σ) in 300 mm Cu wafer bonding.

Chuo Univ.

3D memory with TSV has been proposed as a candidate for the next generation integrated solid-state drive (SSD) with storage class memory (SCM). Such a 3D-TSV SSD is expected to have advantages of fast speed, low power consumption, and high endurance. The table below summarizes the comparison of simulated write performance, energy and required minimum I/O data rates by using the SSDs with and without 3D-TSV. The write energy reduces 68% by applying 3D-TSV in the SCM/MLC NAND hybrid SSD.


Toray has examined increasing the productivity of IC stacking by thermos compression by a “collective” process as shown below.

IFTLE259_Fig6When NCF is used with TCB, enhancement of productivity is an important issue, because it takes about 10 sec to cure the NCF and at the same time melt a solder and connect to an electrode on the substrate. They propose one technique to solve the problem, is by using “collective bonding”. In a pre bonding process, chips are placed quickly at low temperature. Pre bonding of the four layer on a Si substrate was performed in the condition that the stage temperature is 80°C and the head temperature is 150°C for 0.8 s. Post bonding was performed by the equipment which has an improved stage for 3D stacking. As the post bonding condition, the peak temperature of second step of bonding head was set to 280oC so that the temperature in the NCF of the lowest layer was 240°C which was enough to melt a solder. The stage temperature was set to 80°C.

Another technique to speed up the overall process is gang bonding where several chips are placed onto the substrate and bonded at one time.


For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…


IFTLE 258: IEEE 3DIC Sendai Japan; GINTI

By Dr. Phil Garrou, Contributing Editor

The official IEEE 3DIC meeting started in 2009. It rotates from the USA to Europe to Asia on an annual basis. I say official because we all know that “3DIC” has been a buzzword, so every electronics conference in the world has sought 3DIC content, including competing IEEE conferences.

This year’s conference was in Sendai Japan and headed up by Mitsu Koyanagi from Tohoku University. Many of you may not know that Koyanagi-san is viewed as one of the fathers of 3DIC based on his early work in the late 1980s, such as his famous paper “Roadblocks to Achieving Three Dimensional LSI”. He has been working on the three key technologies for 3DIC (thinning, TSV, and bonding) since that time. He will be receiving a “Pioneering Award” for his 3DIC activities this fall at the 3D ASIP Conference which I will be chairing. [Link]


IFTLE has discussed GINTI previously (see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati”).

One of the plenary presentations at this year’s IEEE 3DIC conference was “Advanced 2.5D/3D Hetero-Integration Technologies at GINTI, Tohoku University” by KW Lee, Koyanagi-san, and co-workers, detailing the activities at the University and the prototyping spin-out.

The Global Integration Initiative (GINTI) is 8/12-inch R&D foundry fab for the R&D of 2.5D/3D integration technologies and applications. GINTI provides a process development infrastructure in a manufacturing-like fab environment and “low cost”, prototyping of proof of concepts using commercial/customized 2D chip/wafer, and a base-line process. The figure below shows their 8/12-inch 2.5D/3D integration process equipment

State-of-the technologies include design, layout and mask making to wafer thinning, forming of TSV on chip/wafer (front side/backside TSV), redistribution routing, both side micro-bump formation, chip/wafer stacking, failure analysis, and reliability testing.

GINTI can provide 3D prototype LSI stacking using commercial 2D chips by die-level 3D hetero-integration, backside TSV formation and various stacking (C2C C2W, W2W, and self-assembly) technologies.

IFTLE258_Fig1GINTI mainly focuses on via-last backside TSV approach, because they feel it is a better solution for heterogeneously integrating different function, size, and material devices, with better flexibility for commercial chip/wafers.

Their process flow for via-last backside TSV fabrication is shown below. The incoming LSI device wafer with metal bumps is temporarily bonded onto a support wafer. Then the Si substrate is thinned to target thickness from the backside by grinding and CMP. After via patterning on the ground surface, the deep Si trench is formed from the backside by RIE processing until the first level metallization layer (M1) is exposed. Oxide liner is deposited via holes and the bottom oxide liner in via hole is selectively etched by dry etching to re-expose the M1 layer. Next, the deep trench is filled with Cu by electroplating after dep of barrier and seed metal layers. Re-distribution layer (RDL) is then formed on the backside and metal bumps are formed on the RDL by electroplating. Finally, the support wafer is de-bonded from the thinned LSI wafer.

IFTLE258_Fig2To create new 3D hetero-integrated systems, they have developed die-level 3D integration technology as shown below. Commercially available 2D chips with different functions and sizes, such as those of sensor, logic, and memories which were fabricated by different technologies, are processed to form TSVs and metal micro-bumps and integrated to form a 3D stacked chip in die level.

IFTLE258_Fig3The image below shows a 3D stacked image sensor chip comprising three layers of CIS, CDS, and ADC chips for high-speed image sensor systems.

IFTLE258_Fig4For all he latest on 3DIC and other advanced IC packaging solutions stay linked to IFTLE…


IFTLE 257: IC Insights’ McClean Report Forecast Revisions

By Dr. Phil Garrou, Contributing Editor

IC Insights’ fall revisions to the 2015 Forecast

For nearly two decades, the industry has eagerly awaited the yearly release (early in the first quarter of each year) of the so called “McClean report” issued by IC Insights, which documents and projects the status of our industry.

A fall forecast seminar was just held in Sunnyvale detailing how global economic conditions and emerging developments have reshaped sales forecasts unit shipments and pricing trends for the balance of the year through 2019.

The major message was that semiconductor industry growth, initially pegged at 7% at the beginning of the year, will be closer to 2% and will rise only 4.9% on a compound basis by 2019 to $450B.

Although IC unit sales are expected to increase ~6%,  ASP are falling ~5%, leaving the market flat.

Although IC unit sales are expected to increase ~6%, ASP are falling ~5%, leaving the market flat.

We are basically mimicking the GDP, which is what market segments do when they are mature. And recall IFTLE has been telling you that most market segments are now late in category 3 or already in category 4 (mature).

McClean was quoted by EE Times as saying: “We won’t have a big cycle in semiconductors till there is a big cycle in GDP growth, and it doesn’t seem like its coming” adding that “In general IoT doesn’t look like the savior for returning this industry to 10% growth rates…something could hit with tremendous impact very quickly … [but] the world’s still looking for the next big thing in technology,” and when discussing 450mm wafers, “Five years ago I was 95% sure it would happen in about five years, now its 50/50 whether it happens at all.

Their new assessment of top growing IC Markets is shown below:

IFTLE257_TableWhen looking at the next gen logic/foundry process roadmaps, McClean points out that Intel has just pushed out the 10nm node to 2017.

IFTLE257_Fig2IFTLE has noted several times that the money is made on the leading edge and that’s the main reason to make sure you are keeping up. Well McClean’s latest plot of TSMC’s revenue ramp shows this is spades. At the 45 node it took eight quarters to achieve 20% of total sales, five quarters at the 28 node, and just three quarters at the 20 node.

IFTLE257_Fig3For all the latest in 3DIC and other advanced packaging stay linked to IFTLE…

IFTLE 256: Semicon Taiwan part 3 – substrate and panel processing by Unimicron, Fraunhoffer IZM & J Devices

By Dr. Phil Garrou, Contributing Editor

This week lets finish our look at the substrate and panel level processing activities at Semicon Taiwan 2015’s Embedded and Wafer Level Package Technology Forum.


DC Hu reviewed Innovative Substrate Technologies including glass as a candidate material for high density substrates and interposers.

When it comes to the impact of panel level processing on the cost of high density substrates most would agree that while large glass and PCB panels are available at a reasonable cost, it is not yet clear that current equipment can produce the required densities and thus meet the low cost expectations. Never the less, it is certainly worth the effort to develop the data and sort this issue out.

IFTLE256_Fig1For glass, one of the main questions has been can you make electrically and mechanically functional vias and fill them with conductive metals. Hu compares the current via forming capability of Va Mechanic, LPKF and Corning as is shown below. It appears that the most advanced systems are currently developing < 100um glass thickness, ~25um holes at a throughput of > 2000 holes/sec.


Laser & Electronics AG (LPKF) is a German equipment manufacturer that focuses mainly on PCB prototyping and micromachining solutions for SMT stencils. Via Mechanics, previously known as Hitachi via mechanics Ltd has been engaged in manufacturing, printed wiring board (PWB) manufacturing systems.

Unimoicron is also developing a laminate using glass as core as shown below. Glass has a 3X better flatness (R < 0.5mm) than an organic core given he same core CTE (i.e. 3 ppm/°C). Such technology is currently being demonstrated at 508 x 508mm; 100-200um glass thickness; with 8/8um L/S on ABF dielectric.


They have demonstrated sub 2/2 L/S on test vehicles.

Fraunhoffer IZM

Tanja Braun and co-workers at IZM/TUB detailed their studies on fan out panel level processing. They listed the following as the most obvious challenges:

IFTLE256_Fig4The equipment they have put in place for ~600 x 450 panel level processing line is shown below.


J Devices Panel Level Processing (PLP)

Reasons for wanting to develop pane level processing are obvious. A 500 x 400mm panel has 3X the area of a 300mm wafer.

IFTLE256_Fig6The standard PLP process flow is shown below:


J Devices is equipping a PCB facility to manufacture the PLP technology.

J Devices makes the point that required RDL technology depends on the application. For example Application processors require wafer photolithography while modules for RF/PMIC only require PCB photolithography.

For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…


IFTLE 255: Consolidation continues; ASE acquires SPIL stock; Semicon Taiwan part 2: MediaTek Antenna on Package

By Dr. Phil Garrou, Contributing Editor


One may say that IFTLE has been obsessed with consolidation for the last few years. The reasons for this become obvious when one looks at the increase in recent activity. There are typically ~25 or so acquisitions a year. In 2015, there will 2X that number and the deals, in general are ~10X larger than in the past.

IC Insights has recently pulled together the major M&A activity over the last year.

IFTLE255 Table

In addition, several large M&A agreements announced last year have closed in 2015 including:

  • RF Micro Devices and TriQuint Semiconductor officially completed their Qorvo merger
  • Qualcomm completed its acquisition of CSR in August 2015
  • Cypress completed its acquisition and merger with Spansion in March 015
  • Infineon completed its acquisition of International Rectifier in January 2015
  • IBM completed the sale of its Microelectronics business to GlobalFoundries in July 2015

IC Insights notes that the unprecedented M&A activity is indicative of IC suppliers experiencing slower sales in their existing market segments and the need to broaden their businesses to stay in favor with investors. IFTLE favors the explanation that we have published previously, i.e. many of the segments of our industry are entering late stage 3 and stage 4 where consolidation is the norm. (See IFTLE 241, “Simply Obeying the Laws of Economics”.)

ASE Buys 25 percent of SPIL Stock

Following up on our story about ASE attempting to purchase 25 percent of SPIL (see IFTLE 252, “ASE makes bid for SPIL shares…”), ASE announced on September 22 it has purchased 25 percent shares of SPIL shares, achieving its acquisition goal.

SPIL reiterated that a SPIL-ASE tie-up would not create much synergy, since 85 percent of its customers overlap with ASE’s. “… the acquisition will cause order losses as customers will allocate some orders to a third supplier rather than put all their eggs in one basket,” SPIL stated.

ASE noted that now being a major shareholder of SPIL, the company will be exploring avenues of cooperation with SPIL but otherwise, “ ASE will not intervene in SPIL’s operations and therefore, cannot affect the rights and interests of SPILs current employees.” [Link]

Embedded and Wafer Level Package Technology Forum at Semicon Taiwan

IFTLE255 fig 1Continuing our look at Semicon Taiwan 2015, let’s begin our look at the Embedded and Wafer Level Package Technology Forum led by Mr. Albert Lan (left), Senior Director, SPIL. The theme of the forum was System Integration & Package Solutions for Portable/Wearable/IoT Devices. Mediatek discussed “Packaging Breakthroughs in Wearable Devices”. Unimicron gave a great review of “Innovative Substrate Technology …”;  J Devices discussed their panel level processing efforts and Fraunhoffer IZM discussed results of their fan out panel level processing.



Overall Mediatek sees IoT wearables as requiring:

  • miniaturization which can be achieved with embedding;
  • being substrate less for low cost which is achieved by fan out packaging; and
  • being manufactured on a panel process to minimize cost.

IFTLE255 fig 2Mediatek discussed Aster (MT2502A) a monolithic low-power CMOS chip integrating power management unit, analog baseband and radio circuitry. Based on an ARM RISC processor, it provides a platform for class 12 MODEM and leading-edge multimedia applications.

It also features a Bluetooth transceiver and an FM receiver supporting both audio broadcast de-modulation and RDS/RBDS data decoding. The MT2502A device is offered in a 5.4mm×6.2mm, 143-ball, 0.4mm pitch, TFBGA package. MT2502A provides always-on mode to optimize the low power performance for wearable device. [Link]

IFTLE255 fig 3

Another interesting development is their antenna on package (AoP) technology which they claim offers smaller form factor, better performance and faster time to market, although one must be careful about a properly designed keep-out-zone and proper design to minimize EM interference.

IFTLE 255 fig 4

We’ll finish up with Semicon Taiwan 2015 next week.

For all the latest in 3DIC and other advanced packaging stay linked to IFTLE.

IFTLE 254 Semicon Taiwan Part 1; GaTech Interposer Workshop

By Dr. Phil Garrou, Contributing Editor

System Integration by 3D SiP

cp hungThe forum chairman was CP Hung, who is currently the VP of Corporate R&D for ASE Group, responsible for next generation products development. The System Integration by 3D SiP forum invited global experts to discuss the development of 3DIC and 2.5DIC packaging and alternative solutions. Presentations were made by Cisco, AMD, SK Hynix, ASE, Altera, Amkor, Teledyne and Cadence.



Bryan Black detailed the commercialization of the AMD “Fiji” GPU which has been in development for 8.5 years. It “required the collaboration of 20+ companies and government research organizations”. The four that were key included Amkor, ASE, SK Hynix and UMC.

IFTLE254_Fiji 1

Some of the obstacles that they ran up against are listed below:

IFTLE254_fuji 2

SK Hynix is in production with HBM memory in support of “Fiji”. HBM benefits include:

  • 4096-bit memory interface with four stacks creating 512GB/s of bandwidth
  • 60% higher memory bandwidth6 for 60% less power7 than GDDR5
  • 4X bandwidth per watt improvement from Radeon (TM) R9 290X

SK Hynix

Hongshin Jun of SK Hynix detailed their high bandwidth memory development. Each application has different memory requirements, but most common are high bandwidth (HBM) and low power consumption.

Mass production of their HBMPower consumption and bandwidth are compared for DDR and HBM below:


HBM 2 will show the following properties:


The stacked memory features 25um bumps on 55um pitch.


Min Yoo of Amkor presented their SLIM and SWIFT package architectures. Basically, these are interconnected first technologies with no TSV. SLIM uses back-end foundry technology for <2um L/S, whereas SWIFT uses 2-10um OSAT RDL technology.

IFTLE_amkor 1

GaTech Global Interposer Workshop coming in November

The fifth annual GaTech Interposer workshop is coming Nov 4-6. With 2.5 and 3D being buzzwords, many conferences have interposer presentations. But the GaTech conference does the best job of bringing together practitioners from silicon, laminate and glass segments of this leading edge technology. This year’s conference is led by Rao Tummala (the Godfather of packaging) and Matt Nowak of Qualcomm, and Subu Iyer, who recently retired from IBM to teach at UCLA.

Highlight presentations include:

  • Bob Sankman (Intel) – EMIB packaging
  • Dave McCann (Global Foundries) – ASIC and RF with 2.5D technology
  • Doug Yu (TSMC) – InFO
  • Suresh Ramalingam (Xilinx) – SLIT (a TSV-less interconnect technology)
  • Ron Huemoeller(Amkor) – Advance fan out: SWIFT and SLIM
  • Bryan Black (AMD) – The road to AMD’s Fuji dGPU Chip
  • DC Hu (Unimicron) – Glass manufacturing readiness
  • Tomoyuki Yamada (Kyocera) – Organic interposers

Hope to see you all in Atlanta!

For all the latest on 2.5/3D and other advanced packaging stay linked to IFTLE.

IFTLE 253 China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix; Tezzaron 8 layer 3DIC

By Dr. Phil Garrou, Contributing Editor

China targets GlobalFoundries

In IFTLE 238, we noted that China was the “wild card” when it came to global microelectronics consolidation – with plenty of cash and the government behind them. [link]

China’s National IC Investment Fund, Hua Capital Management, has reportedly approached GlobalFoundries, through an investment bank. Such an acquisition would allow China to secure 14nm FinFET foundry process technology [link 1]. GlobalFoundries’ 14nm process is licensed from Samsung [link 2].

Acquisition of GlobalFoundries would enable SMIC to enter volume production of 14nm FinFET products much earlier than originally planned. SMIC began volume production of 28nm chips in cooperation with Qualcomm and has signed an agreement with Qualcomm, IMEC and Huawei to develop 14nm process with volume production slated for 2020.

Abu Dhabi’s Advanced Technology Investment (ATIC), a major shareholder of GlobalFoundries, is reported to be willing to sell its interest in GF.

In July, China’s Tsinghua Unigroup put a bid in to acquire Micron. On the packaging front, in the last year, Chinese companies have purchased bumping house FCI in Phoenix and the #4 global assembly house STATSChipPAC.

Tessera to Acquire Ziptronix

Tessera Technologies announced the acquisition of Ziptronix for $39 MM [link].

Founded in 2000 as a venture-backed spinoff of RTI International, Ziptronix is a pioneer in the development of low-temperature direct bonding technology for 3D integration.

Ziptronix’s patented ZiBond direct bonding and DBI hybrid bonding technologies. Ziptronix has commercially licensed their ZiBond and/or DBI technologies to Sony Corporation for volume production of CMOS image sensors, to Raytheon and to Tezzaron / Novati.

In 2013, Ziptronix announced an agreement with Tezzaron and Novati Technologies, a wholly owned subsidiary of Tezzaron, selling its 3D IC development lab in Morrisville NC to Tezzaron, to be operated by Novati [link].

Tezzaron Announce 8 Layer 3DIC

At the IEEE 3DIC conference in Japan, Tezzaron and their manufacturing subsidiary, Novati announce the world’s first eight-layer 3D IC wafer stack containing active logic. Claiming “…the transistor and interconnect densities per cubic mm are far higher than achievable with 2D 14nm silicon fabrication.”

Each wafer has 10 layers of copper interconnect supporting high performance CMOS logic – a total of 80 layers of interconnect and 8 layers of transistors in a finished stack as thin as a single conventional die. Tezzaron’s 8-wafer stack contains active CMOS circuitry and tungsten vertical interconnect. Wafers are 20µm thick; SuperContacts are 1.2µm diameter, 6µm deep, and can be deployed at a pitch of 2.4µm. There are no wire bonds, copper pillars, bumps, or underfill between the layers. The wafers were bonded with DBI technology, invented by Ziptronix and now available from Tessera. (see discussion above)


For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 252 ASE Makes Bid for Siliconware Shares; TSMC/Huawei 2.5D Networking Processor; TSMC Closes Solar Business

By Dr. Phil Garrou, Contributing Editor

ASE seeking ~ 25% stake in SPIL

By now, you have seen the news that ASE has made an offer to buy up to 25% of the shares of competitor SPIL at a 34% premium. [link]

For those of you following IFTLE, this attempt at further industry consolidation should not come s a surprise [see IFTLE 163, 195, 231, 241], although some would have predicted that offers for the big 4 OSATS would come from foundries or China Inc, not fellow OSATS.

Although ASE is making statements like “…this is not a hostile takeover” , “…ASE is seeking cooperation rather than competition”, and that this “…is purely a financial investment, and ASE will not intervene in SPIL’s operations” this is the kind of move that clearly precedes a takeover attempt.

ASE and SPIL currently have 19.1% and 10.1% shares, respectively, in the global IC packaging and testing market. The planned ASE-SPIL integration will widen the market gap against rival companies, including Amkor Technology, which has a 12% share and China-based JCET with a 10% share [link]. JCET’s acquisition of STATS ChipPAC was the first major consolidation move amongst the top assembly houses. After acquiring STATS ChipPAC in 2015, JCET now has a production capacity almost equal to SPIL. If this ASE / SPIL goes through, the pressure will on Amkor to make a move beyond J-devices.

OSAT sales

Click to view full screen.

TSMC offered “ no comment ” on the ASE bid offer [link]. ~ 90% of the backend packaging for TSMC’s fabless clients is decided by their customers. Although TSMC works with both ASE and SPIL, many customers report that TSMC appears to have a closer relationship to ASE who they use, for instance, to backup to their internal bumping capacity.

With their recent major move into packaging, TSMC is becoming a competitor to both ASE and SPIL and rumors have circulated that TSMC could acquire one of the OSAT assembly houses.

By the end of the week Hon Hai Precision Industry (which some of us remember as Foxcon the board stuffer) and SPIL announced a strategic alliance via a share swap to reject this ASE hostile takeover of SPIL [link].

TSMC and Huawei develop 2.5D 16nm Networking Processor Module

Despite earlier delays [see IFTLE 228, “Samsung Goings On”] TSMC, during its Q2 earnings call, announced that the chipmaker has begun volume shipment of chips based on its 16-nm FinFET manufacturing process.

One of their first 16nm development projects has been with HiSilicon, the chip design division of China’s telecommunications company Huawei. They have produced an ARM-based 32-core, 64-bit networking processor using TSMC 16nm FinFET manufacturing process. [link].

TSMC has stated that HiSilicon’s processor is the first fully functional networking processor implemented on its 16nm FinFET manufacturing process. As well as using the 16nm FF process HiSilicon used TSMCs CoWoS silicon interposer 2.5D packaging technology to combine the 16nm logic chips with a 28nm logic chips.

The 32-core ARM Cortex-A57 processor is aimed at wireless communications and routers and achieves a clock frequency of 2.6-GHz for next-generation base stations, routers and other networking equipment. 

TSMC to cease solar manufacturing

Through the last decade TSMC has wisely expanded into packaging, MEMS and LEDs so it was to be expected that they would also try their hand at solar. Well that experiment looks like it is over. TSMC has announced that TSMC Solar, its 100%-owned subsidiary, will cease manufacturing operations at the end of August 2015 as TSMC believes that its solar business is no longer economically viable [link].

TSMC has come to the conclusion that despite what it considers as its world-class conversion efficiency for its CIGS [Copper indium gallium (di)selenide ] technology, TSMC Solar will not be viable even with the most aggressive cost reduction plan.

“Despite six years of hard work we have not found a way to make a sustainable profit,” said Steve Tso, chairman of TSMC Solar and senior VP of TSMC.

For all the latest in 3DIC and other advanced packaging, stay linked to IFTLE…


By Dr. Phil Garrou, Contributing Editor

A few years ago in IFTLE 62, we laughed when EE Times reporters got confused and unknowingly compared 3DIC to 3D finfets thinking they were the same thing. Well, things have now gotten even more confusing as the key NAND memory manufacturers have announced commercialization of vertical – NAND memory products which some are calling 3D NAND.

3D technologies

We have noted before that 3D ICs can be categorized as either (A) 3D Stacked ICs (3DIC), which refers to stacking and bonding thinned IC chips using TSV interconnects, or (2) monolithic 3D ICs [see IFTLE 177, Monolithic 3DIC….] which use sequential fab processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy which result in direct vertical interconnects between device layers. V-NAND is an example of the monolithic approach.

Toshiba TSV stacked NAND

Last week, in IFTLE 250, we noted that Toshiba had just announced the world’s first NAND flash memory packages, which stack eight or 16 dies of NAND flash memory devices and feature 128GB or 256GB capacities. Toshiba’s new stacked NAND flash packages integrate (16) 128Gb NAND memory devices connected together using through silicon vias. The multi-layer chips by Toshiba feature 1Gb/s data rate, 1.8V core voltage and 1.2V I/O voltage. The new packages use 50 percent less energy on write operations, read operations, and I/O data transfers than Toshiba’s current products.

The NAND flash memory chips are designed for low latency, high bandwidth and high IOPS/watt flash storage applications, including high-end enterprise SSD. For example, (64) 256GB multi-layer chips would provide 16TB of NAND flash storage, but in order to build such a drive a special controller and other peripherals would be needed.

Toshiba did not say if or when it plans to release its new TSV-based NAND flash memory devices commercially.

PMC Sierra had a working SSD demo at the 2015 Flash Memory Summitt which used the new Toshiba TSV stacked memory (see below). [link] They report that the upfront costs are minimal ( prices for these TSV stacked NAND chips have not been released publically) compared to the long term costs due to power consumption differences. PMC Sierra demonstrated a significantly higher power efficiency for the TSV flash vs standard non-TSV flash for high end enterprise storage. Such power efficiency would also positively impact consumer notebook battery life.

PMC Sierra SSD

PMC Sierra SSD


Vertical NAND memory devices, V-NAND, which some like Intel are calling 3D NAND, are fabricated sequentially and are connected on the cellular level as they layers are built.

Samsung has been working on V-NAND the longest (over a decade) announcing V-NAND based SSD, for use in enterprise servers and data centers, in 2013 and commercializing a 1 TB SSD last summer. Soon after Toshiba, SK Hynix and the Micron / Intel JV IMFT also announced V-NAND roadmaps.

From what has been publically reported, IMFT and Hynix have chosen to stack the current floating gate cell architecture ( the architecture for the vast majority of current 2D NAND) while Samsung and Toshiba have each chosen completely new vertical architectures for their V-NAND technologies. For those with interest, a comparison of these architectures has been published by NCTU Taiwan [link]

So, it looks like NAND can be manufactured both by TSV based 3DIC stacking and by 3D monolithic fabrication.

Are the advantages of TSV based NAND significant enough to compete with monolithic V-NAND which is being commercialized by all the key NAND suppliers ?

What applications would TSV stacked NAND be superior in?

Will Toshiba really commercialize two competing memory stack technologies at the same time?

As these answers become apparent, we will let you know.

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