Insights From Leading Edge


By Dr. Phil Garrou, Contributing Editor

This week, let’s take a quick look at the 12th annual Int. Wafer Level Packaging Conference (IWLPC) which was held in San Jose in October. But before we do, a Christmas message from my granddaughters:


IWLPC 2015

The 2015 IWLPC technical focus consisted of   1) fan-out WLCSP, 2) 2.5 and 3D IC packaging, and 3) MEMS. This conference is becoming a major player in the exhibition end of the packaging business this year having 65 booths set up in San Jose.



We have looked at the activity of Deca several times since their initial pronouncements in 2012 [see IFTLE 124, “Status and the Future of eWLB; Will Deca lower the cost of FO-WLP” and IFTLE 175, “2013 IWLPC; 450mm on Hold?”]

Cost, yield and reliability issues have effectively limited the widespread adoption of FOWLP. Placing singulated chips on the carrier to form the molded panel requires high placement accuracy. Any misplacements can lead to pattern overlay difficulties in the buildup process on the reconstituted panel. The requirement for high placement accuracy restricts throughput at the pick-and-place operation, leading to high process costs. During the molding operation and mold cure, die drift or movement can occur. This die drift can further complicate pattern overlay matching in the buildup process on the panel and can result in yield loss when the drift is excessive.

In the DECA process die with preformed Cu studs are placed face-up on a carrier, using a high speed pick and place tool. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs. A high speed optical scanner is used to determine the actual position of every die on the panel. This information is fed into a proprietary Adaptive Patterning design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. Adaptive Patterning works by dynamically adjusting one or more build-up layers to accurately connect to the Cu studs protruding through the mold compound for each individual die in the molded panel.

After the Adaptive Patterning design files are created, fan-out processing can commence. The build-up proceeds through polymer 1, RDL, polymer 2 and UBM layers, with the lithography system implementing unique designs at the polymer 1 and RDL layers on a per panel basis. Finally, ball attach and package finishing are performed to produce singulated fan-out packages.

deca 1

The board level reliability was examined for a 8mm X 8mm package with 324 IOs on a 0.4mm pitch. The packages were mounted to 1mm thick printed circuit boards (PCBs) with non-solder-mask defined PCB pads. Standard JEDEC conditions were used for temperature cycling and drop testing. First cycling failure occurred at 665 cycles and with no failures observed up to 250 drops.

SPTS – Plasma Dicing

Plasma dicing is attracting significant interest within the semiconductor industry as a viable alternative to conventional singulation methods using saw blades or lasers. Plasma dicing promises benefits such as increasing wafer throughput, die per wafer and die yields (due to low damage processing). For small die, in particular, where the time required for a high number of mechanical slices in “series” can be substantial, a “parallel” process such as plasma dicing which etches all dicing lanes simultaneously, can significantly increase wafer throughput.

Maximum benefits are gained when plasma dicing is “designed in” from the beginning. With dicing lanes defined by photolithography, these lanes can be narrower than the width of a dicing blade, saving valuable silicon real-estate which can be used to increase the number of die per wafer. Also, the designer can make sure that dicing lanes are free from metals and other layers which can hinder plasma etching. This is often quoted as the prime challenge which prevents implementing plasma dicing in an existing production scheme.

IMEC / KLA Tencor

IMEC / KLA Tencor shared their results on investigations to determine the best way to insure µbump presence and co-planarity. µbump dimensions are being scaled down to 20 um pitch (10 µm in width and 8 µm high). For die-to-die and die-to-wafer stacking, the need for highly accurate and repeatable measurement of µbumps at both die-level and wafer-level is a must for this technology to become a viable industrial option.

Bump co-planarity is defined as the difference between the heights of the tallest and the shortest µbump within a die as shown below.


A failure to properly characterize the co-planarity of each die and detect defects of interest such as damaged, missing or mislocated bumps can lead to the wrongful classification of the die as suitable for asembly. This may have a number of yield-affecting consequences during stacking, such as open and short circuits, die cracking and thermal sinks. As the number of die in a typical die stack increases, a single falsely classified die will affect the entire product.

One of the challenges in constituting a meaningful subset for measurement is to define a population of µbumps which is large enough to be statistically significant and to select µbumps from areas in the die which will represent height range and coplanarity of the full die.

Nanium / EVG

Nanium and EVG shared some information on Temporary Wafer Carrier Solutions for Thin FOWLP and eWLB-based PoP.

In order to achieve a cost competitive position related with other packaging technologies, FOWLP has been using 300mm diameter reconstituted wafers, which brings challenges related with its mechanical and thermomechanical properties like wafer bow, wafer warpage and wafer expansion. Nowadays, more FOWLP designs require reconstituted wafers with thickness below 400um. When wafer thickness drops below 400~450um, the reconstituted wafers acquires a flexible behavior that does not allow self-supporting handling anymore.

Adding to this challenge, the need for RDL processing on both sides of the eWLB wafer, for 3D and PoP constructions, requires the temporary protection of one RDL side while the other is being built. Solutions such as temporary wafer bonding for 2.5/3DIC technology , cannot be copied-exact for eWLB wafers because of the very high and non-linear thermomechanical behavior of such wafers and to the temperature limitations the molded material imposes. For example, Si wafers failed as carriers due to the mechanical mismatch to eWLB wafers and with adhesives with bonding process temperature above 200ºC . The selection of carrier wafer and adhesive material are key elements to the success of any temporary bonding and debonding technique for eWLB or fan out in general.

Based on their studies we are not told what the preferred carrier or temp adhesive are, but we are led through several solutions and told what properties lead to the best results.

For all the latest on 3DIC and other advanced packaging options, stay linked to IFTLE…

IFTLE 266 IMAPS Goes Searchable; GaTech Interposer Conf Part 3

By Dr. Phil Garrou, Contributing Editor

IMAPS now “Googleable”

Of upmost importance to researchers at Universities, Research Institutes and even Commercial Companies is the ability of others to find their publications.

For years, a pet peeve of mine with IMAPS (the International Microelectronics and Packaging Society) is that once your work was published it was …well…lost. Mind you I was Technical VP and then President of the Society in 1997 so I’m not some complaining outsider. I have been saying this for more than 20 years. Certainly their journal and proceedings are “archival” in the technical sense of the word. Both are bound and printed and available to individuals and libraries for posterity, but many of their conferences containing key publications are only available if you know they exist and go to the IMAPS web page to download them.

In the 1990s most of the key papers on multichip modules (MCMs) were put into the conference of the same name that many of us sponsored through IMAPS. It was a great Conference, but try finding those papers now unless you have copies of all those proceedings.

Nothing has changed more in my lifetime then how we write reports and share data. In 1975, my first year in industry, we wrote report drafts on yellow legal paper and gave them to the office secretarial pool to type for us. They went back and forth a couple of times (since they couldn’t read my handwriting) and figures were added after they were drawn on a draft board.

Literature searching was done in the library where you combed through books and journals till you found what you were looking for. Once you found a key paper you went through all the references in that paper and went backwards like that till you were pretty sure you had found everything that was worthwhile.

All that changed with the computer and the internet. The computer which we got individually in our offices ~ 1985 (best I can recall) caused the unemployment of a lot of young women in the secretarial pool, but it sure increased my productivity in terms of putting a report together. Internet searching of the scientific literature came a bit slower, but by the late 1990s, or certainly by the time Google Scholar came into being in 2004, most researchers simply put their queries into the Google and up popped more references than you could read.  Everything was now available, well everything that Google searched. You can also easily see where this leads. If everyone only references things that are searchable in Google, then after a few years the only references you can find are those that are searchable by Google. Not so great for scientists publishing in non searchable sources.

The Europeans caught on to this problem first and we saw IMAPS conferences in Europe requesting co-sponsorship of IEEE so that their work would be put into IEEE Explore (yes its Google searchable).

It has taken awhile, but after a lot of bitching by myself and others and a lot of hard work by IMAPS staff everything is now searchable back to 2010. Not only the journal and the annual fall meeting but also key conferences like the Device Packaging Conference (DPC). YES – all the slides presented at the DPCs (since 2010) are now searchable and downloadable. I have tested this out myself and sure enough Google now finds them. For more details try

Georgia Tech Interposer Conference (GIT 2015)

Finishing up our look at the GIT, lets look at Intels EMIB and the SPIL / Xilinx SLIT


Intel is still keeping design flow and ground rules for EMIB (embedded multi die interconnect bridge) close to the vest and I did not see much new from Bob Sankman.

emib 1

Certainly the EMIB eliminates a chip attach operation since there is no Si interposer, but the BGA substrate sure looks a whole lot more complex to me. It certainly is an elegant solution, but I’m not convinced it is the low cost solution till I hear from customers what these modules will really cost. It certainly is of interest that Altera has announced a Stratix 10 to be done with EMIB.

emib 2


Xilinx and SPIL were he first to announce TSV free high density interconnect more than a year ago. See IFTLE 215, “STATS Acquisition; Will SLIT replace TSV?”]

Xilinx indicates that the UMC/SPIL version of CoWoS, SSIT is ready for production.


SLIT offers

– 65nm BEOL design rules                                                                                                                                             – non TSV interconnection                                                                                                                                                    – reduced CAPEX                                                                                                                                                                              – less inspection metrology steps                                                                                                                                             – SLIT patent issued to Xilinx

Xilinx compares SLIT to other solutions below:

slit 2

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…


IFTLE 264 2015 GaTech Interposer Conf Part 2: The Status of Glass

By Dr. Phil Garrou, Contributing Editor

The GaTech group ad many of their members have been studying the applicability of glass as 2.5D interposers for several years now. Some of the papers presented at this year’s meeting updated the industries status in this area.

LPKF Vitrion

LPKF Vitrion updated the attendees with their latest Through Glass Vias (TGV) technology status which is shown below.



Shinko updated their 2014 presentation on the status of Glass interposer R&D and manufacturing. Shinko is looking at glass as an alternative to silicon interposers. Their proposed process flow is shown below.

shinko 1

An example of a fully assembled glass interposer is shown below.

shinko 2

Shinko points out that there are voids inside the TGVs and they are very difficult to avoid. These voids increase the via resistance ~ 8.5%. They are in the process of determining what the acceptable void content is.

shinko 3

They are capable of 2um L/S RDL on the glass. They are in the process of reliability studies and failure analyses.

They are currently examining 250mm sq panels which increase unit production 2.7X vs 200mm wafers.


DC Hu from Unimicron shared their perspective on glass technology readiness. Hu lists the following requirements for glass mass production readiness:

Based on 510 x 510mm panels and 2/2 L/S fine line capability

– glass process readiness

  • Thin glass handling
  • Via forming technology
  • Via filling technology

– production equipment readiness

– reliability

He compared TGV formation from Via Mechanics, LPKF, Corning, Schott and Asahi Glass and via filling by seed and plate vs screen printed paste technologies. The paste technologies appear capable of 20um vis on 50um pitch.

While plating can be done on a 500mm sq panel, fine line patterning (2um L/S) requires a large panel stepper.

unimicron 2

Technology status vs silicon is shown below.

unimicron 3


TDK discussed what they claim is the first glass based Rf modules. Rf integration is clearly the key enabler for next gen smartphones. Key technologies for Rf modules are shown below.


The glass Rf module concept, which is being developed with GaTech, is shown below.

tdk 2

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 263 GIT 2015: High Density Laminates and Lasers – Kyocera, ESI, Suss

By Dr. Phil Garrou, Contributing Editor

The Georgia Tech High Density Interposer Technology conference (GIT) held a few weeks ago in Atlanta. Traditionally it has been a great place to compare and contrast high-density interposers in silicon vs glass vs laminate. In the next few weeks, we will take a look at some of the key presentations.

Kyocera – Adv Laminate Packaging Design Rules

Some of you youngsters might not recall that Kyocera the ceramics company expand into the high density laminates business when they purchased IBM Yasu production in 2005. In the late 1980s and early 1990s, IBM had been working on increasing the density of laminate packages by adding thin film layers with photo vias. They called these SLC (surface laminar circuits) Such high density BGAs were necessary for flip chip packaging to move to HVM. This all took off ~ 1992 when IBMs Yutaka Tsukada announced the technology for flip chip underfill and SLC circuits. Ground rules for the first gen SLC are shown below:

kyocera 1


Kyocera, seeing that higher densities and lower costs would not be coming from the ceramics business, made a bold move a decade ago when they bought the business from IBM. It is interesting to look at how the technology has advanced in a decade. Their latest ground rules are shown below.

kyocera 2

ESI – High Accuracy Lasers for Adv Packaging

Electro Scientific Industries (ESI) shared the latest results with their CornerStone ICP Series UV laser drilling system designed for use in Integrated Circuit Packaging applications.

They report positional accuracy of +/- 4 µm and 10 µm via capability with AR of 1:1.

esi 1


System capabilities are summarized below:

esi 2

In addition, the new system has a 25% smaller footprint than typical laser drills in HVM production today.

Suss Microtec – Eximer Laser Ablation for Adv Packaging

Suss shared their information about damascene processing of RDL using their eximer laser tool. The eximer laser is used with mask based projection with a field area of 35 x 35mm sq.

suss 1


Suss has developed a process flow for the stacking of high density RDL layers using non photo dielectrics.

Suss 2

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFLE 262 SEMICON Europa part 1; Update on G450, Panasonic Plasma Dicing; Thin Flexible Die Packages; Osram reviews LED packaging options

By Dr. Phil Garrou, Contributing Editor

G450 – 450mm wafer status report

For most of us, whether we work in the FEOL or in packaging, what we want to know about the attempted move to 450mm wafers is (1) if it will really happen and if so (2) when will it happen. Unfortunately, those answers are not yet clear. The recent G450C update at SEMICON Europa shared some new information, but we really cannot expect such a highly politicked program to ever come out and say “This just isn’t going to work.”

G450C is a collaborative consortium being run at the Albany nano tech center. Members are Intel, TSMC, GlobalFoundries Samsung and IBM. IBM, recall has sold off all production capability to GF, so this program, to them, is really a window on what can be done, not something they will commercialize.

The consortium goal is to have a “full flow 14/10nm process capability on line by 2016.” Of interest was their tool installation status report as shown below.


In terms f process readiness, they reported the following:

  • Process Capability demonstrated on 98% 14nm process steps
  • Productivity: 80% of process tools can achieve 300mm equivalent or better (WPH)
  • Performance: Process tools at or near 300mm process targets
  • Suppliers can deliver HVM tools in 18-24 months after signals
  • Potential die cost savings of >30% achievable

Panasonic – Plasma Dicing

Panasonic reports that plasma based dicing is both damage free and results in more die per wafer due to the narrower dicing streets. Panasonic reports etch rates of 20m/min with their APX300 HVM tool.

panasonic 1


In addition, the fracture strength of the silicon is greatly increased.

panasonic 2

Front side and backside process flows are shown below.

panasonic 3

Fraunhoffer EMFT – Ultra-thin devices in flexible packages

Christof Landesberger of Fraunhoffer EMFT discussed their program to develop a processing scheme for embedding and interconnection of ultra-thin IC devices in flexible chip foil packages.

Target applications include:

  • Smart phones – Reduce package thickness
  • Healthcare and Wearables
  • Large area electronics; e. g. bendable displays and photovoltaic modules
  • Sensors on curved surfaces; to be adapted or integrated to machines, buildings, robots, housings
  • IoT applications

The key question to be answered is: “Will there be increased mechanical robustness of ultra-thin silicon die after embedding them in films?”

They report a strong increase in breaking force for ultra thin silicon after embedding as shown in the following weibull plot.



Their process flow is sown below.


In their micro controller demonstrator, 25um thick die are inserted in the cavities on the flexible substrate. The chips are covered by 10um of thin film dielectric and patterned and connected. The final packages showed no cracking or delamination after bending.

Their initial conclusions are hat rigid packages will be used for 50-150um thick die and such flexible packages will be used for ultra thin, 10-30um die.

Osram – review of chip interconnection in LED packages

Standard LED packages remain lead frame based. They are:

– easy to assemble by standard SMT reflow

– show the lowest manufacturing cost

– integral solder pad with excellent heat sinking

– single WB interconnect with proven reliability

osram 1

A multitude of packaging configurations are available and are being used.

osram 2

Die attach methods include conductive epoxies, non conductive silicones, sinterable materials and eutectic metal solders which all provide different thermal performance and cost and ae better compatible to different packages.

osram 3


Amongst other things, they conclude:

– When comparing acrylate based silver filled die attach to their epoxy counterparts Osram finds that the acrylates show less stable interconnection after solder heat treatment.

– Corrosive gasses like moisture, NO2 and SO2 diffuse through clear silicone encapsulant. Attack on copper is even worse. Hybrid silicones should be used as well as Ni diffusion barriers for copper gold plated surfaces.

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…

IFTLE 261 Consolidation Continues; the Info on InFO?; RTI 3D ASIP

By Dr. Phil Garrou, Contributing Editor

Consolidation in our maturing industry is the ONE most important this that is happening to microelectronics in the 21st century because this is/will set the playing field for everything that follows. Many of you will be working for massive new companies soon whether you know it or not. This is something you really should be paying close attention to.

LAM Acquires KLA_Tencor

Consolidation continues with the recent announcement that Lam will acquire KLA-Tencor in a cash and stock transaction. The combined company will combine Lam’s capabilities in deposition, etch, and clean with KLA-Tencor’s capabilities in inspection and metrology. The combined company will have ~ $8.7B annual revenue making it roughly the same size as AMAT.

There will likely be opposition from some in the semi industry but probably less so than for the AMAT/TEL proposed merger since there is really little overlap in their focus markets.

Western Digital (WD) to Acquire SanDisk

The hard disk drive segment of our industry reached maturity ~ 2011. The hard disk drive business started in the 1960’s. Since then the > 200 companies who have been in the business competed on data density and latency and smaller form factors. Most of that industry has long since vanished through bankruptcy, mergers and acquisitions. As expected for a mature industry segment there are now 3 surviving manufacturers – Seagate, Toshiba and WD. Seagate acquired Samsung’s HDD business in 2011; Western Digital (WD) merged with Hitachi’s HDD business in 2011 and Toshiba acquired Fujitsu’s HDD business in 2009. This divided up the HDD market into WD 48%, Seagate 40% and Toshiba 12%.

Growth in mature industry segments requires acquisitions in aligned fields. Thus it could have been expected that WD would make a move into other types of data storage. WD’s acquisition of SanDisk gives the company an instant foothold in the global, non-volatile NAND flash memory market.

With the PC HDD business in decline due to both a weakening PC market and solid state drives (SSDs) making major inroads into that market, WD needed access to NAND storage technology both for laptops/desktops and to maintain competitiveness with NAND players in the enterprise space. This acquisition will allow WD to expand its participation in higher-growth memory storage segments.

It is reported that WD will have to raise $18.4 billion to finance the $19B SanDisk acquisition. In September WD announced that Chinese state-backed Unisplendour Corporation ( a subsidiary of Tsinghua Holdings ) would be investing $3.8B for 15% of WD “to help facilitate growth and future strategic initiatives.”

Sony Acquires Toshiba’s CMOS Image Sensor Business

Toshiba has announced that it will sell its image sensor business to Sony for ~ $166MM and pull out of the sensor business. For Sony, the acquisition of Toshiba’s image sensor business would further solidify its already dominant position in the industry where it already controls 40% of the market.

For those of us that have been following 3D with TSV since its inception, we recall that Toshiba was responsible for one of the early milestones, namely it was Oct 2007 that Toshiba announced the commercialization of their “chip scale camera module” which used “through chip vias.” Although it was only a one layer device, it marked the first mainstream commercial use of TSV in the silicon chip industry. By the way that was reported in one of my very first blogs in PFTLE, the predecessor to IFTLE which ran for several years in the now defunct Semiconductor International magazine. At that time PFTLE predicted that the CMOS imaging chips would eventually be broken up into functions and stacked. Sony brought that concept to commercialization a few years ago. [ see IFTLE 172, “IFTLE 172 Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013” ]


What’s the inside info on InFO. Try as you might, despite the significant press it has received, you cannot point to a publication that clearly outlines the process flow for TSMC’s InFO package. I have been asked whether it is chips first or chips last and all I could answer was: “Good question.”

Well, sources in Asia have leaked the following process flow to me. Although I cannot guarantee this is the actual TSMC InFO process flow (until Doug Yu confirms it) I’ll none the less show it to you since it is a quite interesting flow. The answer to the question for this process flow is chips first or interconnect last. Die are placed face up, pillars are plated on die and then molded. Routng to the package BGA balls is through mold vias (TMV). The wafer is then polished down to reveal tops of Cu pillars and standard” RDL is processed up from there. Ability for finer features appears to come from more planar starting surfaces and better controls of photo processes. IFTLE would guess that warpage is the major problem for this process flow.


3D ASIP Conference 12 Years and Going Strong

As it has for the last decade, 3D ASIP will once again close out the packaging conference season with its mid December 3DIC focused meeting outside of SF.

The 12th annual 3D Architectures for Semiconductor Integration and Packaging, or 3D ASIP as it has become known, will be held December 15-17, 2015, at the Sofitel San Francisco Bay Hotel in Redwood City, Ca. It is the longest running conference on 3DIC focused on commercialization and infrastructure.

The conference general chair and program coordinator is Dr. Philip Garrou, Microelectronics Consultants of NC. The technical co-chairs this year will be Professor Mitsumasa Koyanagi, Tohoku University, and Dr. Rama Alapati, director of packaging product management, GLOBALFOUNDRIES.

Matt Lueck of RTI International and Herb Reiter of EDA2ASIC Consultants have developed two half-day tutorials focused on temporary bonding/debonding and interposer design respectively. Presenters from CEA-Leti, HD Micro, Dow, TOK, Brewer Science, SUSS MicroTec and TOK will discuss the current state of the art in bonding and debonding technologies. The interposer design program includes presentations from Mentor Graphics, Cadence Design Systems, Ansys, E-System Design, Zuke, and eSilicon.

“This year, 3D ASIP will honor two trailblazers in 3DIC, Peter Ramm, Fraunhofer EMFT and Professor Mitsumasa Koyanagi, Tohoku University. They will be honored for their early pioneering work in the 1990s that set the stage for what we today know as 3DIC. Following the award ceremony, each recipient will deliver a short presentation on his group’s early work in 3DIC.

Screen Shot 2015-11-16 at 6.02.36 AM


Plenary presentations will be delivered by Brandon Prior, Prismark, discussing the status of 2.5/3D and other high density technologies; Rozalia Beica, Yole Développement, comparing and contrasting the new 3D memory architectures; and DC Hu, Unimicron, reviewing the transformation of substrate technology.

Screen Shot 2015-11-16 at 6.02.45 AM


The nine invited sessions cover topics including: Memory Stacks become Reality, Products and Production in the 2.5/3D Infrastructure, Equipment and Metrology, High Density Packaging without TSV, and Heterogeneous Integration.

Key presentations will include Hynix, Micron, Tezzaron and Toshiba discussing their new 3D stacked memory products; Xilinx/SPIL, Amkor and TSMC discussing their non TSV high density solutions; AMD discussing the commercialization of Fiji graphics modules with HBM memory stacks. Dan Green of DARPA discussing their DAHI heterogeneous integration 3D platform and Sony discussing their new stacked image sensor technology.

For more information on the conference agenda, visit the conference website at

For all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…


IFTLE 260: IMPACT Taiwan 2015 – Altera, iNEMI, SPIL


The IMPACT conference claims to be the largest gathering of packaging and PCB professionals in Taiwan. It is organized by IEEE CPMT, ITRI, IMAPS Taiwan and the Taiwan Printed Circuit Association. The Technical Chair for IMPACT 2015 is CT Liu, of ITRI.


Charlie Lu of Altera discussed his reasoning for the new term “ViB” to describe Via-interconnect Ball-Grid-Array.

Traditionally we all learned that there are three types of interconnect: WB, FC and TAB. Lu defines ViB as a ball-grid-array package whose chip-to-package electrical interconnect is achieved by direct interconnection through the vias. Some wafer level packages and fan-out packages, he contends, belong to this category.

Traditionally, chip-to-package interconnect is done by wire bonding (WB), flip-chip bonding (FC), and to some extent, tape-automatic bonding (TAB). There are two steps for via-interconnect process: (1) via formation and (2) via filling or via bottom and sidewall metallization. Via formation could be done by laser ablation or photolithography process, or by other techniques. Via filling and metallization is usually done by mixed techniques of Ti/Cu sputtering and Cu or Ni/Cu plating. Thus, the process of via-interconnect technology is unique from that of WB, FCB, and TAB.

Lu compares the interconnect technologies in the table below.


The industry has begun using the term WLP for so called fan in packages fabricated on wafer, “FO-WLP” for fan out packages formed from reconstituted wafers, and “FO-PLP for fan out packages formed by panel level processing. Lu correctly points out that all packages except fan in WLP are FO packages. He prefers the term ViB as a category to cover both FO-WLP and FO-PLP. If it is necessary to spell out the process applied for a given ViB, an additional suffix could be added, like ViB-D, D stands for “dry”, meaning that the ViB is made by wafer Fab-like process. Likewise ViB-W means the ViB is processed by “wet” process, i.e. PCB-like process. It is no longer necessary to emphasize a package is fan-out or fan-in, because WLP already implies itself a fan-in package, apart from WLP, all others are fan-out packages.

Those of you who follow IFTLE closely know I’m a stickler for nomenclature and not a fan of terms like 2.1D which have no real meaning or “interposer” since all packages are interposers. In this case Lu is attempting to clarify the categories and I can see some logic in his presentation. Whether we all pick up on ViB or not in the end will depend on all of you.


iNEMI updated their program on “recent trends in package warpage”. Below we see a comparison of the warpage for various packages with various pretreatments.


  • Dynamic warpage of POP package varies according the construction.
  • There is insignificant dynamic warpage difference between “As I” vs Bake and MET.
  • Majority of the POP package received kept the high temperature warpage below 100um.

POP Memory:

  • There is insignificant dynamic warpage difference between “As Is” vs “Bake” and “MET”.
  • Majority of the POP package received kept the dynamic warpage below 100um.


  • There is no observable dynamic warpage difference between As Is vs Bake.
  • Different Lid attachments can yield different dynamic warpage characteristic.
  • Ceramic substrate with Lid demonstrate similar dynamic warpage behavior as like organic substrate but with lower magnitude for the package size considered.


  • The effect of “Bake” and “MET” on dynamic warpage is more apparent in PBGA package.
  • The “Bake” generally shows lower high temperature while “As Is” and “MET” shows the tendency to elevate the warpage by 20-50um. Take note that this depends on the mold material used.


Max Lu, deputy Director of SIliconware, discussed WLP innovations such as molded WLCSP, Fan-Out WLP and NTI (No TSV interconnection).

Molded WLCSP

Potential for greater board level reliability.

Passes: component level – 1000hr TCT ; 96hr HAST and 1000hr HTS PASS

Board level – 1000x TCT cycle and 30X Drop test.

IFTLE260_fig3Fan Out PoP

Thinner FOWLP results in thinner PoP packages. Passes: component level – 1000hr TCT ; 96hr HAST and 1000hr HTS PASS and Board level – 500x TCT cycle and 30X Drop test.

IFTLE260_fig4No TSV Interconnect (NTI) Platform

SIliconware was one of the first to describe a chips last interconnect technology which they call SLIT (see IFTLE 215, “STATS Acquisition; Will SLIT replace TSV?”).

SPIL proposes the merits of NTI Platform are:

  • Shortening interconnection distance than traditional TSV interposer.
  • Reducing interposer process cost without TSV related process cost.
  • Processing by all existing MEoL/BEoL equipment.

The following shows the unit operations done by SPIL and those done in foundry.


For all the latest in 3DIC and other advanced packaging stay linked to IFTLE…

IFTLE 259: IEEE 3DIC 2015 part 2 – DARPA , Xilinx, Tohoku Univ, IMEC/Samsung, Nikon, Chuo Univ., Torray


In his presentation “Path to 3D Heterogeneous Integration” Dan Green, DARPA program manager described their motivation for heterogeneous integration.

Modern RF systems are under pressure to make use of the spectrum in sophisticated ways, while working within limited power budgets on platforms with reduced size and weight. The compound semiconductor (CS) electronics industry is well-positioned to address these challenges, due to the superior properties and diversity of CS materials. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with fmax above 1THz . Wide energy bandgap GaN has enabled large voltage swings as well as high breakdown voltage RF power devices. The excellent thermal conductivity of SiC makes tens of kW power switches possible. On-chip high-Q micro-electromechanical resonators and switches in materials such as AlN, have been demonstrated that potentially can be used for clock references and frequency selective filters.

The DARPA view is that the future of CS electronics depends not on displacing Si, but rather on heterogeneous integration of compound semiconductors with silicon technology in a way that will allow the advantages of the two technology types to be optimally combined.

The DAHI Foundry Technology thrust was initiated in 2013 to advance the diversity of heterogeneous device and materials available in a silicon-based platform and make this technology available to the greater DoD and commercial microsystems design community through the establishment of an accessible, manufacturable foundry offering for device-level heterogeneous integration. Recently, a DAHI multi-project wafer run was demonstrated utilizing 0.25um InP HBTs, 0.2um GaN HEMTs heterogeneously integrated with 65nm Si CMOS. A chiplet assembly approach was chosen as the primary path at the DAHI Principal Foundry because of reported advantages in flexibility and processing of dissimilar materials.


Xilinx updated the audience on their 2.5D FPGA program. Xilinx has participated since 2006 in 3D-IC technology development. Today there are more than (7) 3D-IC products from 2 generations of FPGA family nodes in shipping to customers. The figure below compares the different technologies available for high density interconnect.

IFTLE259_Fig1 Tohoku Univ

Rittinon and co-workers reported on the stability of electroplated copper thin film interconnect.

The mechanical properties of electroplated copper thin films, such as Young’s modulus and tensile strength vary drastically compared to those of conventional bulk copper. The reason for the variation and fluctuation of these mechanical properties is that the electroplated copper thin films mainly consist of fine columnar grains with porous grain boundaries as shown in the figure below. This micro texture changes the mechanical properties of the electroplated copper thin films significantly from those of bulk copper.

IFTLE259_Fig2The existence of porous grain boundaries is the main reason for the high resistivity and local high Joule heating in the electroplated copper interconnections. Therefore, the crystallinity of the electroplated copper thin-film interconnection has significant effect on the long-term reliability of the interconnections. They find that high Joule heating appears at grain boundaries with low crystallinity.

It is well-known that the crystallinity of electroplated copper interconnections is improved by high temp annealing. Since recrystallization and/or grain coarsening occurs during annealing, however, high tensile stress remains in the annealed interconnection because the shrinkage of the film is strictly prohibited by the surrounding silicon in a TSV structure. Such high tensile stress is the main reason for stress-induced migration in the interconnection resulting in the formation of a lot of voids in it.

Since the lattice mismatch between tantalum (the Cu migration barrier layer) and copper is about 18%, these researchers feel it is necessary to introduce an intermediate layer as the seed layer material between them. They report that a thin layer of ruthenium is an effective material for minimizing the lattice mismatch. It decrease the lattice mismatch from 18% to 6% thus lowering the overall stress formation.


It has been known for several decades that low temp oxide wafer bonding can be enhanced by plasma treatment of the oxide surfaces by process flows such as the one shown below.

IFTLE259_Fig3Researchers at IMEC and Samsung have now studied the potential for low temp bonding by dielectric films other than SiO2. The figure below shows the results of the surface roughness and bond strength measurements for SiOx, SiOxNy and SiCxNy surfaces that were treated with O2, Ar or N2 plasmas. Among those three dielectric films, the SiCxNy film had the best bonding strength in the same low temperature annealing condition for 2h at 250°C.



Sugaya and co-workers reported on a new “precision” wafer bonding technology for 3DIC. The technology includes a new precision alignment methodology and a unique thermo-compression bonding procedure. Experimental results show that the alignment capability is 100nm or better, and permanent bonding accuracy of 260 nm (|mean| + 3σ) in 300 mm Cu wafer bonding.

Chuo Univ.

3D memory with TSV has been proposed as a candidate for the next generation integrated solid-state drive (SSD) with storage class memory (SCM). Such a 3D-TSV SSD is expected to have advantages of fast speed, low power consumption, and high endurance. The table below summarizes the comparison of simulated write performance, energy and required minimum I/O data rates by using the SSDs with and without 3D-TSV. The write energy reduces 68% by applying 3D-TSV in the SCM/MLC NAND hybrid SSD.


Toray has examined increasing the productivity of IC stacking by thermos compression by a “collective” process as shown below.

IFTLE259_Fig6When NCF is used with TCB, enhancement of productivity is an important issue, because it takes about 10 sec to cure the NCF and at the same time melt a solder and connect to an electrode on the substrate. They propose one technique to solve the problem, is by using “collective bonding”. In a pre bonding process, chips are placed quickly at low temperature. Pre bonding of the four layer on a Si substrate was performed in the condition that the stage temperature is 80°C and the head temperature is 150°C for 0.8 s. Post bonding was performed by the equipment which has an improved stage for 3D stacking. As the post bonding condition, the peak temperature of second step of bonding head was set to 280oC so that the temperature in the NCF of the lowest layer was 240°C which was enough to melt a solder. The stage temperature was set to 80°C.

Another technique to speed up the overall process is gang bonding where several chips are placed onto the substrate and bonded at one time.


For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…


IFTLE 258: IEEE 3DIC Sendai Japan; GINTI

By Dr. Phil Garrou, Contributing Editor

The official IEEE 3DIC meeting started in 2009. It rotates from the USA to Europe to Asia on an annual basis. I say official because we all know that “3DIC” has been a buzzword, so every electronics conference in the world has sought 3DIC content, including competing IEEE conferences.

This year’s conference was in Sendai Japan and headed up by Mitsu Koyanagi from Tohoku University. Many of you may not know that Koyanagi-san is viewed as one of the fathers of 3DIC based on his early work in the late 1980s, such as his famous paper “Roadblocks to Achieving Three Dimensional LSI”. He has been working on the three key technologies for 3DIC (thinning, TSV, and bonding) since that time. He will be receiving a “Pioneering Award” for his 3DIC activities this fall at the 3D ASIP Conference which I will be chairing. [Link]


IFTLE has discussed GINTI previously (see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati”).

One of the plenary presentations at this year’s IEEE 3DIC conference was “Advanced 2.5D/3D Hetero-Integration Technologies at GINTI, Tohoku University” by KW Lee, Koyanagi-san, and co-workers, detailing the activities at the University and the prototyping spin-out.

The Global Integration Initiative (GINTI) is 8/12-inch R&D foundry fab for the R&D of 2.5D/3D integration technologies and applications. GINTI provides a process development infrastructure in a manufacturing-like fab environment and “low cost”, prototyping of proof of concepts using commercial/customized 2D chip/wafer, and a base-line process. The figure below shows their 8/12-inch 2.5D/3D integration process equipment

State-of-the technologies include design, layout and mask making to wafer thinning, forming of TSV on chip/wafer (front side/backside TSV), redistribution routing, both side micro-bump formation, chip/wafer stacking, failure analysis, and reliability testing.

GINTI can provide 3D prototype LSI stacking using commercial 2D chips by die-level 3D hetero-integration, backside TSV formation and various stacking (C2C C2W, W2W, and self-assembly) technologies.

IFTLE258_Fig1GINTI mainly focuses on via-last backside TSV approach, because they feel it is a better solution for heterogeneously integrating different function, size, and material devices, with better flexibility for commercial chip/wafers.

Their process flow for via-last backside TSV fabrication is shown below. The incoming LSI device wafer with metal bumps is temporarily bonded onto a support wafer. Then the Si substrate is thinned to target thickness from the backside by grinding and CMP. After via patterning on the ground surface, the deep Si trench is formed from the backside by RIE processing until the first level metallization layer (M1) is exposed. Oxide liner is deposited via holes and the bottom oxide liner in via hole is selectively etched by dry etching to re-expose the M1 layer. Next, the deep trench is filled with Cu by electroplating after dep of barrier and seed metal layers. Re-distribution layer (RDL) is then formed on the backside and metal bumps are formed on the RDL by electroplating. Finally, the support wafer is de-bonded from the thinned LSI wafer.

IFTLE258_Fig2To create new 3D hetero-integrated systems, they have developed die-level 3D integration technology as shown below. Commercially available 2D chips with different functions and sizes, such as those of sensor, logic, and memories which were fabricated by different technologies, are processed to form TSVs and metal micro-bumps and integrated to form a 3D stacked chip in die level.

IFTLE258_Fig3The image below shows a 3D stacked image sensor chip comprising three layers of CIS, CDS, and ADC chips for high-speed image sensor systems.

IFTLE258_Fig4For all he latest on 3DIC and other advanced IC packaging solutions stay linked to IFTLE…


IFTLE 257: IC Insights’ McClean Report Forecast Revisions

By Dr. Phil Garrou, Contributing Editor

IC Insights’ fall revisions to the 2015 Forecast

For nearly two decades, the industry has eagerly awaited the yearly release (early in the first quarter of each year) of the so called “McClean report” issued by IC Insights, which documents and projects the status of our industry.

A fall forecast seminar was just held in Sunnyvale detailing how global economic conditions and emerging developments have reshaped sales forecasts unit shipments and pricing trends for the balance of the year through 2019.

The major message was that semiconductor industry growth, initially pegged at 7% at the beginning of the year, will be closer to 2% and will rise only 4.9% on a compound basis by 2019 to $450B.

Although IC unit sales are expected to increase ~6%,  ASP are falling ~5%, leaving the market flat.

Although IC unit sales are expected to increase ~6%, ASP are falling ~5%, leaving the market flat.

We are basically mimicking the GDP, which is what market segments do when they are mature. And recall IFTLE has been telling you that most market segments are now late in category 3 or already in category 4 (mature).

McClean was quoted by EE Times as saying: “We won’t have a big cycle in semiconductors till there is a big cycle in GDP growth, and it doesn’t seem like its coming” adding that “In general IoT doesn’t look like the savior for returning this industry to 10% growth rates…something could hit with tremendous impact very quickly … [but] the world’s still looking for the next big thing in technology,” and when discussing 450mm wafers, “Five years ago I was 95% sure it would happen in about five years, now its 50/50 whether it happens at all.

Their new assessment of top growing IC Markets is shown below:

IFTLE257_TableWhen looking at the next gen logic/foundry process roadmaps, McClean points out that Intel has just pushed out the 10nm node to 2017.

IFTLE257_Fig2IFTLE has noted several times that the money is made on the leading edge and that’s the main reason to make sure you are keeping up. Well McClean’s latest plot of TSMC’s revenue ramp shows this is spades. At the 45 node it took eight quarters to achieve 20% of total sales, five quarters at the 28 node, and just three quarters at the 20 node.

IFTLE257_Fig3For all the latest in 3DIC and other advanced packaging stay linked to IFTLE…