Insights From Leading Edge

IFTLE 353 Updating CMOS Image Sensor Technology

By Dr. Phil Garrou, Contributing Editor

A few weeks ago, we covered the Sony announcement of the Xperia XZ1, which features a 19MP Exmor RS camera with 960fps video capture and reportedly is fabricated as a stacked 3 layer CIS with DRAM. [see IFTLE 346 “Sony Introduces Stacked Image Sensor with DRAM in Xperia XZ phones]

This technology was first disclosed at IEEE IEM in 2016 as their “Cu2Cu Hybrid Bonding” [link] and discussed in IFTLE coverage of last falls 3D ASIP Conference [see IFTLE 319 “ …3D ASIP Part 2: Image Sensing – Sony, Tessera, SMIC”]

Those of us that have been following 3DIC for the past decade recognize this as the Ziptronix “DBI process” which they licensed to Sony a few years ago. It is now quite clear that the literature is generically calling this technology “hybrid bonding” since the bonding occurs to a surface containing both copper and oxide. Hybrid bonding does not have TSVs since it simultaneously connects the two substrates physically and electrically.

They depict there process flow as follows

Sony 1

The trench and via are made at the BEOL top layer of each wafer. Then, barrier metal and Cu seed are formed by PVD. Cu is plated up and annealed at the appropriate temperature. Excess Cu is removed by CMP to reveal the Cu connection pads and oxide dielectric. After face-to-face bonding, the wafer stack is annealed. As illustrated in their figure 4, the upper Cu pad and lower Cu pad are connected by Cu diffusion and grain growth, and the upper dielectric and lower dielectric are connected by dehydration-condensation reaction. They report that it is important to remove any voids from the Cu pad bonding interface during the post-ECD annealing.

Samsung CIS now include Stacked DRAM too

According to new reports [link], Samsung has developed and will begin mass production in November 2017 of a similar mobile camera sensor capable of 1,000 frames per second (FPS). Reports are that the camera contains a stacked 3 layer image sensor, with the layers made up of the sensor itself, logic chip, plus a DRAM chip that can temporarily store data.

While we are at it, let’s take a look at the advances covered at the recent Int Image Sensor Wkshp held in Hiroshima this past May.


Venezia of Omnivision described their “1.0um pixel improvements with hybrid bond stacking technology” discussing their Gen2, 1.0um CMOS image-sensor technology featuring hybrid bonding stacking.

Their first generation, stacked chip technology used oxide-oxide bonding and TSV to bond and electrically connect the sensor and logic wafers, respectively. “With stacking technology, the logic circuitry is placed under the array, resulting in an overall smaller chip size than is possible with standard BSI-CIS; where the circuit is located on the same wafer. Stacking also allows for sensor-only processes that improve CIS performance which could have negative impacts on circuit performance in a BSI-only process.”

The gen 2 technology uses hybrid bonding “where wafers-to-wafer bonding occurs at both the oxide and metal interfaces, and water-to-wafer interconnection is made at the top metal bonding pad. This architecture offers a better interconnect pitch and more flexible interconnect placement than the previous Gen1 approach. For instance, bonding can occur closer to the array edge, or even within the array.” The resulting chip size is 10% smaller using HB technology for the Gen2 1.0um, 16MP product.

fig 2



Hseih of TSMC gave a joint paper with Qualcomm on “A 3D Stacked Programmable Image Processing Engine in a 40nm Logic Process with a Detector Array in a 45nm CMOS Image Sensor Technologies”

They designed & fabricated a RICA (Reconfigurable Instruction Cell Array) ASIC wafer stacked with a pixel arrays wafer of 8MP, 1.1 um pitch BSI image sensor test vehicle. This device used “the 3D stacking technologies of a 45nm CIS process and a 40nm logic process at TSMC”.


Kagawa of Sony discussed “Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding” further detailing their Cu2Cu hybrid bonding technology.

They describe the positive attribute of not having to create TSVs in their devices as follows “Making TSVs needs special fabrication equipment, such as deep Si etcher and high coverage metal/dielectric deposition tool. In addition to the fabrication problems, there are device problems. In particular,

the keep-out-zone (KOZ) strongly affects device specifications and circuit design. On the other hand, hybrid bonding does not have such problems. It can basically be fabricated by the conventional back-end-of-line (BEOL) process, and special equipment is never needed….Moreover, the Cu connection pad is located on top of the BEOL layer, and it never interferes with the MOS-FET during the fabrication process. It enables enormous circuit design flexibility and further chip size reduction can easily be achieved.”

Reliability tests were carried out under voltage and temperature stressed conditions. Predicted lifetime was estimated from Black’s equation as over 10 years. Extremely low leakage current and good TDDB reportedly indicate that the Cu connections are well isolated by the dielectric. They fabricated a stacked back-illuminated CMOS image sensor with “22.5 megapixel 1/2.6 size CIS featuring a 1.0μm unit pixel size and an ISP…” using their Cu2Cu hybrid bonding process.


Ray Fontaine of TechInsights in his “Survey of Enabling Technologies in Successful Consumer Digital Imaging Products” detailed the technologies responsible for the remarkable advances in mobile phone camera performance over the last decade.

He notes that “Two-die stacks, comprising a back-illuminated CIS and mixed-signal image signal processor (ISP), have emerged as the dominant configuration for leading smartphone camera chips” and adds that “The recent manufacturing trend for back-illuminated CIS chips in a stacked configuration seems to have stabilized at the 90/65 nm process generation “ as shown in the fig below.

Techinsights 1

He notes that Sony’s current leadership position in the industry is due to the fact that they were the first to bring stacked CIS chips to market, by implementing homogenous wafer-to-wafer bonding (oxide bonding) with TSVs in 2013 and Cu-to-Cu hybrid bonding, (also known as Cu2Cu bonding or DBI), in 2016. OmniVision’s first observed stacked chips, fabricated with foundry partner XMC in 2015, used a ‘butted’ TSV structure in which a single, wide TSV contacted both a CIS and ISP pad structure. OmniVision later adopted a unified TSV structure for its 1.0 μm pixel generation PureCelPlus-S chips, fabricated by foundry partner TSMC. The observed Samsung stacked chips in production also feature a butted TSV structure, but instead use a W-based TSV window liner for vertical interconnect. These are shown below.

techinsights 2

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 351 ASE Tech Forum Part 3: Plasma Dicing, 2.5/3D Options

By Dr. Phil Garrou, Contributing Editor

Several of you have asked how Hannah, Madeline and family have survived the floods down in Houston. Thanks for your concern. Luckily, the old time Texans built Rice University on high ground and my son bought in a neighborhood near there. However, that doesn’t mean they didn’t see water. The pic below shows Maddie standing on the sidewalk outside their house knee deep in water, but, as you can see to the right, it was nothing compared to other parts of the city!




Finishing off our look at the ASE Tech Forum, Plasma-therm (working with ON Semi and DISCO) examined Plasma die singulation. One would look to plasma dicing to avoid the damage caused by mechanical blade dicing or the HAZ caused by Laser dicing which requires as larger than normal street to act as a keep out zone. Stress is also reduced by plasma dicing as is shown in the figure below. It is also clear that plasma dicing can result in more die per wafer due to the smaller required street/kerf.

plasmatherm 1


However, plasma dicing cannot etch through metal so any features in the streets (such as test structures) must be dealt with.

One solution is to isolate the test structures and process control monitors and etch around the die as shown in the fig below.

plasma-therm 2

In terms of market adoption of plasma dicing, they offered the following slide showing us what was qualified in production and what was in development.

plasmatherm 2

2.5 / 3D Technology Choices

ASE’s Chris Zinck in his examination of 3D packaging presented an interesting slide on 2.5/3D options plotting technology solutions vs substrate L/S capability. It is shown below. In their view what is evolving is a technology choice based on required density with std FC and PoP at > 10um; fan out using advanced laminate silicon-less RDL solutions between 10um and 1um and silicon interposers at less that 1 um. IFTLE is not so sure about the advanced substrate solutions in the 3-1um range , but in general this is a good way of looking at how the market is breaking out.


IMAPS 50th in Raleigh

Hope to see many of you at this years fall IMAPS meeting which just so happens to be the 50th anniversary of IMAPS and just so happens to be down the road from me in Raleigh NC. As I explained a few blogs ago [see IFTLE 336 “ISHM to IMAPS…” ] IMAPS has been there since the beginning of our industry and it will be fun to see all of those who have contributed to packaging through the years.



For all the latest in advanced packaging, see you at IMAPS 2017 and, of course, keep reading IFTLE…

IFTLE 350 DARPA Electronics Resurgence Initiative: Going Beyond Moore’s Law

By Dr. Phil Garrou, Contributing Editor

IFTLE has discussed in detail the coming end of Moore’s Law and the implications that holds for our electronics industry. For instance see IFTLE 300 “ITRS 2.0 – It’s the End of the World As We Know It”,

Well DoDs DARPA has stepped up and is attempting to lead the industry out of the quagmire that is the myriad of options that have presented themselves.

On June 1, DARPA’s Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) “to open pathways for far-reaching improvements in electronics performance well beyond the limits of traditional scaling”. Key to the ERI will hopefully be new collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD. The DoD proposed FY 2018 budget reportedly includes a $75 million allocation for DARPA in support of this, initiative. It is reported that in total we are looking at a $200,000MM program.

For details on the ERI see DARPA-SN-17-60 [link]

chappellThe program will focus on the development of new materials for devices, new architectures for integrating those devices into circuits, and software and hardware designs for using these circuits. The program seeks to achieve continued improvements in electronics performance without the benefit of traditional scaling. Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO), which will lead the program, announced “For nearly seventy years, the United States has enjoyed the economic and security advantages that have come from national leadership in electronics innovation…..If we want to remain out front, we need to foment an electronics revolution that does not depend on traditional methods of achieving progress. That’s the point of this new initiative – to embrace progress through circuit specialization and to wrangle the complexity of the next phase of advances, which will have broad implications on both commercial and national defense interests. ”He continued “We need to break away from tradition and embrace the kinds of innovations that the new initiative is all about…”

The chip research effort will complement the recently created Joint University Microelectronics Program (JUMP), an electronics research effort co-funded by DARPA and SRC (Semiconductor Research Corporation). Among the chip makers contributing to JUMP are IBM, Intel Corp., Micron Technology and Taiwan Semiconductor Manufacturing Co. SRC members and DARPA are expected to kick in more than $150 million for the five-year project. Focus areas include high-frequency sensor networks, distributed and cognitive computing along with intelligent memory and storage.

The materials portion of the ERI initiative will explore the use of unconventional materials to increase circuit performance without requiring smaller transistors. Although silicon is used for most of the circuits manufactured today, other materials like GaAs, GaN and SiC have made significant inroads into high performance circuits. It is hoped that the initiative will uncover other elements from the Periodic Table that can provide candidate materials for next-generation logic and memory components. One research focus will be to integrate different semiconductor materials on individual chips, and vertical (3D) rather than planar integration of microsystem components.

The architecture portion of the initiative will examine circuit structures such as Graphics processing units (GPUs), which underlie much of the ongoing progress in machine learning, have already demonstrated the performance improvement derived from specialized hardware architectures. The initiative will explore other opportunities, such as “reconfigurable physical structures that adjust to the needs of the software they support”.

The design portion of the initiative will focus on developing tools for rapidly designing specialized circuits. Although DARPA has consistently invested in these application-specific integrated circuits (ASICs) for military use, ASICs can be costly and time-consuming to develop. New design tools and an open-source design paradigm could be transformative, enabling innovators to rapidly and cheaply create specialized circuits for a range of commercial applications.


As part of this overall Electronics Resurgence Initiative, DARPA, last week, had their kick of meeting for the CHIPS program (Common Heterogeneous Integration and Intellectual Property (IP) Reuse). We have previously discussed CHIPS here [see IFTLE 323 “The New DARPA Program “CHIPS”…”

The CHIPS vision is an ecosystem of discrete modular, IP blocks, which can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of such IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. The CHIPS program hopes to develop the design tools and integration standards required for modular integrated circuit (IC) designs.

Program contractors include Intel, Micron, Cadence, Lockheed Martin, Northrop Grumman, Boeing, Synopsys, Intrinsix Corp., and Jariet Technologies, U. Michigan, Georgia Tech, and North Carolina State University.

The CHIPS program will tackle digital interfaces and systems and their supporting technologies with the goal of:

– developing common interface standards                                                                                                                                                    – enabling the assembly of systems from modular IP blocks                                                                                                               – demonstrating the reusability of the modular IP blocks via rapid design iteration


For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 349 ASE Tech Forum part II: FC, WLP & FOWLP

By Dr. Phil Garrou, Contributing Editor

Before we continue our look at the recent ASE Tech forum, a word about the solar eclipse. Much of the media portrayed this as a “once in a lifetime” event. I clearly recall one in the spring of 1970. I was in my last semester at NC State, living off campus and it was mid afternoon. It stared to get dark, the winds stirred up and the animals (birds and dogs) became silent. The temperature dropped what felt like 25 degrees and then it began to reverse.

The event was memorable enough for Carly Simon to insert lyrics about the “elite cool people traveling to be seen at a solar eclipse” into her generational song “You’re so Vain” (1972). Actually, she was watching it a few miles from me with boyfriend/future husband James Taylor who lived in Chapel Hill NC where his father was a University Dean. Anyway, it was certainly an unusual natural occurrence and the 8/21/2017 total eclipsed was my second and probably last chance to see one.

For those of you that were in its path…hope you enjoyed it this time around!


ASE Tech Forum continued

Back at the ASE tech forum in Nijmegen, Bradford Factor gave an update presentation on FC, WLP and FOWLP. On one of his early slides, Factor states that ASE began their bumping / FC work in 2000. I will add to that, noting that this all began for them after they licensed the FCT (Flip Chip Technologies) technology package ~ 2000. This was the dawn of wafer level technology, I was running the BCB business for Dow Chemical at the time and we were working with FCT to “bring up” licensees ASE, Amkor and SPIL during this time period. Taiwan had become the center of bumping and WLP. This new “wafer level” technology was destined to become the backbone of the advanced packaging for the next few decades.


Product families for fan in WLP (known as WLCSP at the time) are shown below.


The technology evolved from the FCT printed bump to the Unitive plated bump to today’s copper pillar bumps.


The latest ASE bump and WLP roadmaps are show below:


The following “industry node status” is an interesting slide in that it shows us ASE’s assessment of where the foundries are on the scaling roadmap.


ASE motivations for Fan out WLP:

  • Package Size

– Fine line redistribution (RDL) layers                                                                                                                            – Low profile by encapsulated chip and component                                                                                                       -Flexible integration by multi-chip and stacking chip

  • Cost Effective

– No substrate                                                                                                                                                                       – Panel (next generation)                                                                                                                                                 – High production yields (including with RDL substrate / chip last)

  • Performance

– Signal integrity & electrical performance, lower power consumption and better thermal ASE FO-WLP technology Roadmap and Package types follow.


For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 348: ASE Tech Forum at Nijmegen part 1 – “Advanced Packaging 2017”

At the recent ASE Tech Forum in Nijmegen chaired by John Marc Yannou, Ivanovik of Yole gave a nice overview of the industry presentation entitled “Advanced Packaging Industry 2017”

In general they report:

  • Growth decline in the main semiconductor driver (smartphones)
  • Stagnating mature markets (PC, tablets)
  • Cost benefits of CMOS scaling have ceased (see figure below). Long time readers of IFTLE have been aware of this trend sine 2011 when we reported Handle Jones of IBS observed the trend at the annual Semi ISS conference [see IFTLE 40 “Samsung 3D IC Wide I/O DRAM and Semiconductor Predictions for 2011”]

yole 1

In the future they predict no single leading driver, but rather a fragmented growing market including autonomous vehicles, vehicle “electrification”, robotics, AI and that general term that IFTLE hates, IoT.

yole 2

In general packaging has gone from:

  • Bridging the gap between semiconductor and PCB level, serving as IC protection and providing a form factor for testability


  • Shifting system integration from the die to the package level!


  • Packaging serving as the “IC shell” to becoming the performance and functionality enhancer!

They offered the following as their assessment of 2016 advanced packaging wafer split by manufacturer.

yole 3

Total 2016 OSAT revenue is $27.9B vs IDM revenue of $26.8B

They offer the following as 2016 top 25 OSAT revenue. Taiwan now has 55% of production and China is in second place with 18% followed by the US with 17%.

yole 4

Advantage will go to packaging houses which are able to either:

  • Maintain a large portfolio of package architectures and technologies for customers
  • Lead in specialty processes and packaging (i.e. MEMS, LED, image sensor packaging)

Revenue will continue to be driven by FC over the next 5 years while units will be drive by QFN and fan in WLP.

yole 5

For all the latest in advanced packaging stay linked to IFTLE…


IFTLE 347: ASE Embedded Packaging Solutions

At the recent IMAPS Carolina Chapter meeting Rich Rice of ASE gave an update presentation on “Embedded Packaging Solutions”. Specifically:

  • SESUB- Semiconductor Embedded In Substrate
  • aEASI –Advanced Embedded Active System Integration
  • FOWLP- Fan Out Wafer Level Package


– ASE offers SESUB through the JV with TDK

– embedding IC releases surface space for other components or allows reduction in overall substrate size

– short copper connections improves parasitics

– ~ 2 dozen SESUB programs underway



– combining leadframe and laminate technologies

– embedding for power devices                        

– good current capability, i.e. ~ 60A; 1.9W/mm2

– 300um Cu heat spreader on back of die      

 – 32um thick Cu lines for low resistance

– low resistivity Ag nano die attach materials keep processing temp and electrical resistance down

IFTLE 347ase 2



– die are embedded in a reconstituted plastic wafer that is then processed like a silicon wafer

– FOWLP can provide size/electrical benefits for a wide variety of products including PMIC, AP, RF devices in mobile applications demanding miniaturization and performance.


For all the latest in Advanced Packaging stay linked to IFTLE…

IFTLE 346 Sony Introduces Stacked Image Sensor with DRAM in Xperia XZ phones

By Dr. Phil Garrou, Contributing Editor

It has been nearly a decade since Toshiba announced the use of backside TSV’s to miniaturize CMOS image sensors [ see PFTLE “Imaging Chips with TSV Announced for Commercialization” Semiconductor Int., Oct 27th 2007 ; recall Perspectives from the Leading Edge, PFTLE, was the predecessor to IFTLE and ran from 2007 to 2010 in Semiconductor Int magazine before its demise]

More recently, In Feb 2017 at the IEEE International Solid-State Circuits Conference (ISSCC) Sony announced the Industry’s First 3-Layer Stacked CMOS Image Sensor (90 nm generation back-illuminated CIS top chip, 30 nm generation DRAM middle chip, and a 40 nm generation image signal processor (ISP) bottom chip for Smartphones [link]. Sony further revealed that that the CIS is made in a 90 nm, 1 Al, 5 Cu technology, the DRAM is a 1 Gb, 30 nm (3 Al, 1 W) part, and the ISP is a 40 nm, 1 Al, 6 Cu device.

Readers of IFTLE were given this info even earlier [ see IFTLE 272 “2016 3D ASIP Part 1: Pioneer Awards; Sony 3D stacked CIS…” ]

This newly developed sensor with stacked DRAM delivers fast data readout speeds, making it possible to capture still images of fast-moving subjects with minimal focal plane distortion as well as super slow motion movies at up to 1,000 frames per second (approximately 8x faster than conventional products) in full HD (1920×1080 pixels).[link]

At the recent Mobile World Congress, Sony announced adoption of this technology their Xperia XZ Premium and XZs phones, with the Motion Eye camera system capable of 960 fps.

Dick James, writing in EE Times, reports on cross-sections of the rear-facing camera chip which contains the 3 layered stack. The CMOS image sensor (CIS) is mounted face-to-back on the DRAM, which is face-to-face with the image signal processor (ISP). [Link] The cross section below is direct for Sony. Since the DRAM is sandwiched between the CIS and the ISP, the high-speed data has to go through the memory chip to the ISP, and then back-and-forth until it is output through the I/F (interface) block of the ISP, at a conventional speed suitable for the applications processor” reports James who then adds that since the DRAM die also has the CIS row drivers on it, it must be “designed as a custom part, and is not one of the TSV-enabled (TSV = through-silicon via) commodity DRAMs”.

sony 1

James has also shown the TSV layer connections between the two chips (see below). The cross section below shows two layers of TSVs connecting a 6-metal stack in the CIS to the M1 of the DRAM die. They did not have a cross-section of extended TSVs joining the CIS directly to the ISP, though there are TSVs through the DRAM to the top metal of the ISP.

sony 2

In an interesting article by Ray Fontaine of TechInsights [link] he notes that “the development of low-temperature wafer bonding and various wafer-to-wafer interconnect techniques have been key enablers for stacked image sensors. Two-die stacks, comprising a back-illuminated CIS and mixed-signal image signal processor (ISP), have emerged as the dominant configuration for leading smartphone camera chips. The CIS portion can be considered a ‘dumb’ chip carrying only an active pixel array. Most of the signal chain and digital processing is partitioned onto the ISP and systems application processor.”

He then offers the following table comparing technologies that have been implemented since 2013.



With Sony’s inclusion of DRAM into the CIS stack, IFTLE can safely predict that Omnivision and Samsung will not be far behind.

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 345 Toshiba 1Tb Flash with TSV; TSMC CoWoS expansion & 2nd Gen InFO; Samsung Foundry takes aim at TSMC

By Dr. Phil Garrou, Contributing Editor

Time to catch up on some very important industry activities…

Toshiba – 3D flash memory with TSV

Toshiba has announced development of its BiCS flash three-dimensional (3D) flash memory utilizing through-silicon via (TSV) technology [link]. Shipments of prototypes will begin in June 2017, and product samples will be shipped in the second half of 2017. Prototypes were shown at the 2015 Flash Memory Summit.[link 2]

Toshiba reports that by combining a 48-layer 3D flash process and TSV technology has allowed Toshiba to successfully increase product programming bandwidth while achieving low power consumption. The power efficiency of a single package is approximately twice that of the same-generation BiCS flash memory fabricated with wire-bonding technology. TSV BiCS flash also enables a 1-terabyte (TB) device with a 16-die stacked architecture in a single package. The 1 Tb 16 chip stack measures 14 x 18 x 1.85mm.

Toshiba expects to commercialize BiCS flash with TSV technology to provide an ideal solution in respect for storage applications requiring low latency, high bandwidth and high IOPS/Watt, including high-end enterprise SSDs.


TSMC – Expanding CoWoS Capacity?

Digitimes reports rumors in Taiwan that TSMC will expand its CoWoS (Chip on Wafer on Substrate) packaging and testing capacity to fill increasing orders from Nvidia and Google. The capacity expansion will reportedly be at the IC packaging and testing plant in Longtan Science Park (purchased from Qualcomm in 2014) where InFO packaging is currently manufactured. TSMC has not confirmed this expansion.

Reportedly, increasing orders from Nvidia and Google for high-end packaging and testing of their AI Chips has fully occupied TSMC’s existing CoWoS process capacity, driving the company to expand.

Nvidia has moved from 16nm to 12nm for fabricating its Volta-architecture GPU chips. Google has contracted TSMC to carry out wafer foundry services for it’s second-generation Tensor Processing Units (TPU2) using 16nm process technology, as well as backend packaging and testing.

TSMC – 2nd Generation InFO packaging for 7nm node

Digitimes also reports that TSMC’s integrated fan-out (InFO) wafer-level packaging technology will enter its 2nd generation, and be used for their 7nm FinFET process technology. Digitimes notes that this makes it unlikely that Samsung will be able to regain AP orders for Apple’s iPhone, since InFO makes TSMC’s 7nm FinFET technology more competitive than Samsung’s. [link]

Samsung – plans to triple foundry market share

Reuters reports that Samsung plans to triple the market share of its contract chip manufacturing business within the next five years. [link] E.S. Jung, executive VP of the foundry division, told Reuters that they want a 25 percent market share (would be #2 in market share) within five years and will seek to attract smaller customers in addition to big-name clients to fuel the growth.

Samsung first announced that they were considering separating their contract chip manufacturing organization (foundry business) last fall [link]

They finally announced the spin off its foundry operation from the System LSI division to create an independent business unit this past May. This will change Samsung’s current organization consisting of memory and system LSI into three entities including the foundry business.[link] The current foundry business is estimated to be ~ a $4.75B operation.

Research firm HIS reports that in 2016 TSMC held a 50.6% market share, GlobalFoundries 9.6%, UMC 8..1% and Samsung Foundry 7.9%

Samsung says it will start manufacturing 7nm chips using EUV litho tech in the second half of 2018.


IFTLE has discussed for years that Samsung, if they ever chose to, could become the number 2 foundry supplier in the world…well, now they choose to. This is probably bad news for GlobalFoundries and UMC. The question now becomes will Intel do the same. Intel, in the past few years, has put their “toe in the water” but has never really committed to a foundry business. Will this move by Samsung force their hand?

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 344 ECTC 4: Reliability Studies of 2.5/3DIC – Cisco, Infineon, Siliconware

By Dr. Phil Garrou, Contributing Editor

Continuing our look at presentations from ECTC 2017.

Cisco – Challenges of 2.5/3D

Li Li of Cisco gave a nice presentation concerning “Reliability Challenges in 2.5D and 3D Integration”

Compared with traditional 2D IC packaging, the emerging 2.5D and 3D IC integration involves several new elements in design, manufacturing and supply chain processes. These new elements include:

cisco 1


Let’s focus on one area that Li discusses that has for the most part gone under the radar since it is usually not addressed by back end practitioners – gettering. For further info on this topic IFTLE refers you to the work of Koyanagi and c0- workers at Tohoku Univ who have studied the impact of copper contamination on memory retention.

The devices formed from the thinned silicon wafer are more easily affected by metal impurity contamination and crystal defects. Because the Intrinsic Gettering (IG) region and the Extrinsic Gettering (EG) layer in the silicon substrate for gettering metallic contaminants are removed during the wafer-thinning process for the 3D IC fabrication. Potential Cu contamination from Cu TSVs is another concern that can further degrade the device reliability if the barrier for the Cu TSV is not designed and fabricated correctly.

Fig. 2 shows schematically the effect of IG layer and the potential risk of metal (Cu, Au, etc.) contaminants diffusing into the active region and cause device degradation.

cisco 2

Intel has reported Cu contamination from die backside causing high pin leakage after Unbiased Highly Accelerated Stress Testing and High Temperature Storage testing. To prevent Cu contamination from backside, an Ar ion implantation for Cu gettering and a SiN barrier was proposed.

Infineon & Nanyang Univ – Reliability of Copper TSV

Infineon and Nanyang reported on the “Reliability Evaluation of Cu TSV Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis”

The integrity of Ti barrier and SiO2 dielectric liner were evaluated via electrical characterization after being subjected to different stress tests such as high temperature storage, temperature cycling and electrical biasing to detect barrier and dielectric liner degradation in a the structure.

TC -65/150 °C up to 2000 cycles was performed on the structures to study the extent of barrier degradation by thermomechanical stress induced by TC. After electrical biasing, an increase in the inversion capacitance was observed in the C-V curve indicating Cu ions presence in the dielectric liner. It is suggested that the cracks formed after TC stress may have propagated within the Ti barrier. This can eventually lead to the drift of Cu ions into the dielectric liner under a sufficiently high E-field which acts as an external driving force for Cu ions to drift through the degraded barrier and cracks.

Siliconware – Warpage in 2.5D Modules

Siliconware described their “Warpage Study of Large 2.5D IC Chip Module”

SPIL lists four processes for 2.5D IC modules: Chip on Chip, Chip on Substrate, Chip on Wafer first (CoW-first), and Chip on Wafer Last (CoW-last). In this study, CoW-last was studied. CoW_last means the die are stacked on interposer wafer after the interposer is fully processed including frond side u-bump and backside via revealing (BVR), backside re-distribution layer (RDL) and C4 or Cu pillar bumping.

They found that for some specific designs, the area of multiple top dies are smaller than interposer, which produces empty area on interposer. This makes for unbalanced chip module stress and worsens chip module warpage.

Therefore, they propose a dummy die (DAF) structure(s) to fill up empty area on interposer. In this study, two dies are attached on interposer, as shown in the fig below. The thickness is the same as top die thickness.

spil 1

Underfill and molding compound

They found that a method for warpage improvement is to decrease the underfill volume by the design of lower bump/cu pillar height. Generally, high bump height provides the tolerance for warpage compensation because of more solder volume, and also enhance bump stiffness by low modulus underfill.

Assuming there is no reliability effects to low bump height, the underfill during cooling process acts a buffer material for stress releasing, but induces higher chip module warpage. From experimental results, when UF volume reduces 31%, the warpage between chip module and substrate can be reduce 10% at room and high temperature. “To decrease the volume of high CTE underfill really can improve the chip module warpage”. IFTLE reads this as meaning don’t make the bump/copper pillar higher than necessary to achieve the required reliability or it will negatively affect the warpage.

In terms of molding compound, the module with molding compound successfully negates the effects of CTE mismatch and leads to warpage reduction of 87% at high temperature.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 343 ECTC 3: Materials and Processes: Tohoku, Hotachi Chem, Samsung

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2017 ECTC.

Tohoku Univ – Low CTE Underfill

Kino and coworkers at Tohoku Univ presented their data on the “Remarkable suppression of local stress in 3DIC by MnN based filler with large negative CTE”.

Generally, CTE of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips, as shown in Fig. 2 below. Such local bending stress would affect transistor performance in thinned IC chips. Kino found that they could suppress the local bending stress by decreasing the CTE difference between the underfill material and the microbumps.

tohoku 1

In general, silica, is usually used in underfill material to reduce the CTE of underfill material. A high concentration of filler is required to reduce CTE as low as metal microbumps. However, it is difficult to use the conventional filler for 3D IC with fine pitch microbumps since a high concentration of filler in underfill material increases the viscosity. They propose to use negative-CTE material as the underfill filler to suppress the local bending stress. They used manganese nitride-based material which has large negative-CTE of -45 ppm/K at the temperature from 65 to 100°C. Results indicate that negative-CTE filler can suppress the thinned Si chip bending more than 50% compared with SiO2 filler. 

Hitachi Chemical – Expanding Film for WLP Sidewall Protection

Honda and co-workers from Hitachi Chemical discussed “Expanding film and process for high efficiency 5 sides protection and FO-WLP fabrication.”

WLP is well suited to mobile devices which require small, thin and light bodies. Fan in WLP (FIWLP) is fabricated by building up redistribution dielectric and metal layer on device wafer and attaching ball, and then it is diced to singulated packages. Device semiconductor die sides are exposed in such a FIWLP. The FIWLP fabrication process needs a wide die gap between die for molding compound and to dice, while leaving the molding compound on the die side wall for the protection.

To get the greater productivity and enhance the usage of the device area in the wafer, an expandable film and a novel process have been developedas shown below in fig 2. The film / process can also be applied to a die first type FO-WLP fabrication. Elimination of the die re-placement step can make the FO-WLP fabrication process simpler and less costly.

hitachi 1

The 5 sides protection fabrication process is composed of 7 steps as illustrated in Fig. 2. The

expanding film with diced-wafer was put on the expander and the film expanded. After that the film is fixed to the grip ring , the film is cut out along the outer rim of the ring. After the singulated dice were transferred to the carrier with keeping the expanded die gap, the grip ring was removed. Then the expanding film was removed from the carrier. After over-molding, the molded wafer was singulated by dicing and 5 side protected packages were obtained.

The stress-strain curve of the film was optimized so that the die gap becomes large. Moreover, the die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap after expansion, the standard deviation was about 0.05 mm. Furthermore, the film was applicable to die sizes 1 mm × 1 mm, 5 mm × 5 mm and 10 mm × 10 mm.

Samsung – Compression Molding Encapsulants for FOWLP

Kwon and co-workers discussed “Compression molding encapsulants for wafer-level embedded active devices”. Challenges that FOWLP packaging technology is confronted with include wafer warpage, die shift/protrusion, and board level reliability. A solution to wafer warpage is considered crucial for successful subsequent wafer processing.

They propose to use a bilayer test structure with silicon wafer and epoxy molding compound as a standardized evaluation vehicle. Each layer is 300 μm thick. To further standardize testing, the molding conditions are fixed at 135 °C x 600 sec with a post mold cure of 150°C x 2 hrs. By standardizing the test vehicle and processing conditions, warpage behavior between mold compounds can be directly compared, and any observed differences are solely caused by the EMC.

Various parameters influencing wafer warpage were screened by the simulated calculation. Among all these parameters, Young’s modulus, CTE, and Tg have a significant effect on the controlling warpage. Generally, wafer warpage is reduced by lowering the Young’s modulus and CTE, and increasing the Tg. Although concurrent optimization of Young’s modulus, CTE, and Tg of a mold compound’s properties is very difficult because of tradeoffs for modifying each component, they developed new compression molding compounds with both low Young’s modulus and CTE, with relatively high Tg.

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