Insights From Leading Edge

IFTLE 225 IEEE 3DIC – Cork: The Thermal Impact of TSVs – reexamined; Parylene: an IFTLE alternative opinion

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the key presentations at the 2014 IEEE 3DIC Conference recently in Cork, Ireland.

Global Integration Institute (GINTI) –    µ-XRD for Thermo-mechanical Stress Measurement

Copper-Through-Silicon-Via (Cu-TSV) is increasingly used for two reasons: (i) the very low resistivity of Cu as compared to that of the other TSV-fill materials that significantly reduces the (RC) delay, and (ii) the ease of Cu-electroplating to fill the TSV without any voids which enhances the production throughput.

Cu-TSV also suffers from some of the critical reliability issues such as diffusion of Cu in to active Si from back-metal contamination and the thermo-mechanical stress caused by Cu-TSV pumping.

Parasitic capacitance is approximately proportional to the size and length of the TSV. Therefore, in order to reduce the parasitic capacitance due to Cu-TSVs, one has to reduce the TSV size and length. To improve the yield of Cu-TSVs the aspect-ratio of the TSV has to be kept as small as possible. This forces one to reduce the thickness of Si thickness that leads to decrease in the mechanical strength of the 3D-LSI. The thermo-mechanical stress in 3D-LSI is widely measured using Raman spectroscopy.

In the future 3D-LSI will have TSV dia from few um down to sub um, one will no longer be able to use Raman to be used as a stress metrology tool. Micro X-ray diffraction (u-XRD) uses one order smaller diameter probe, as small as 200nm.

Ginti has studied stress values deduced from u-XRD data from LSI samples containing Cu-TSVs, whose diameter varies from 2 to 20um. It was observed that the TSV diameter has huge impact on the magnitude of resultant thermo-mechanical stress. The 20um-width Cu-TSV has induced more than -1500 MPa of stress in the vicinal Si, while the 2um-width Cu-TSV induced less than -10 MPa of compressive stress in the surrounding Si. Therefore by decreasing the TSV diameter, one can virtually eliminate the thermo-mechanical stress induced by TSV.

CEA Leti / ST Micro  – Thermal Performance of 3DICs 

Leti and ST Micro presented two papers on the thermal performance of 3DICs.

3DICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology.

There are four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs.

Heat dissipation in small hotspots is primarily diffused through the high thermal conductive silicon substrate and spreads in a semi-spherical direction, rapidly decreasing the heat density and lowering the peak temperature. In case of thinned silicon dies in a 3D stack, the inter-die interface layer acts as a thermal barrier due to its poor thermal properties, forcing the heat to spread laterally in the silicon substrate and thus resulting in a temperature distribution which approximates a cylindrical shape.

Thinned silicon dies present reduced lateral heat spreading capacity while poorly conductive adhesive materials used to bond dies together contribute to increase the vertical thermal resistance.

An increase in power density may come from higher power dissipation and/or from a reduction of the chip footprint. It means either more power needs to be removed from the same package or that the same power dissipation has to go through a reduced chip footprint. While chip footprint reduction is one of the advantages of 3D integration, it usually leads to higher temperatures for the same amount of energy dissipation when compared to single-die implementations.

Leti shows that inserting TSVs as thermal vias is of limited value. They contend that it is more important to reduce the thermal resistance between the stacked silicon dies which is due to  poor thermally conductive layers such as  BEOL metallization and underfill.

Thinned dies can present a severe thermal impediment especially to chips with hot spots. Thinned dies present high lateral thermal resistances thus forcing the heat to go through the underfill layer to the next die, which acts as a heat spreader reducing the hotspot temperature. Consequently, the thinner the die the more important is the thermal coupling between dies in case of hotspot heat dissipation.

The use of “thermal TSVs” for thermal mitigation has been routinely reported in the literature. Several thermal-aware physical optimization techniques can be found in the literature which rely on simplistic thermal models where the TSV is treated as a vertical lumped thermal resistor with thermal conductivity calculated according to its diameter and length. Such thermal models ignore the lateral heat transfer and the impact of the thin Si02 layer, which surrounds each TSV and thermally isolates TSVs from silicon substrate. The poor thermal conductivity properties of the SiO2, dominate the thermal impact of the TSVs in case of hotspot dissipation. Thus while having TSVs in the silicon substrate increases the equivalent vertical thermal conductivity at the same time it causes a lateral thermal blockage effect, especially for fine TSV pitches.

The thermal test chip is composed of two stacked dies connected through TSVs in the bottom die and μ-pillars (μ- bumps) in a face-to-back stacking configuration. Large FC Cu-pillars (bumps) are used to connect the bottom die to a BGA substrate. Gaps between layers are filled with underfill material for mechanical strength purposes.

leti 1


The SiO2 layer around each TSV leads to an increase of the hotspot temperature compared to the case without TSVs (+1.9 °C). Contrary to the common expectations, TSVs have a negative thermal impact on the hotspot temperature.


Increasing the TSV density increases the vertical thermal conductivity as well as the lateral thermal blockage effect. Splitting large TSVs into smaller ones, as suggested in [4] for instance, increases the ratio of the SiO2 layer thickness to the TSV diameter and hence increases also the lateral thermal blockage effect. Considering TSV technologies with very fine pitch, where this ratio is typically 1:10, also lead to TSV arrays with higher lateral thermal blockage effect.


An explorative study including multiple TSV array configurations and power dissipation profiles shows that, contrary to the common belief, TSVs are not effective for thermal mitigation in current TSV technologies and may even provoke exacerbated hotspots. Although TSVs help to convey heat vertically, the lateral thermal blockage effect prevails over any thermal benefit arising from TSVs in the case of hotspots. In the reported investigation, TSVs placed around a small hotspot may result in peak temperatures worsened by up to 15%.


Parylene HT for 3DIC – An Alternative Opinion


Researchers at AIST reported at Cork on Parylene HT’s use as an insulator layer for copper TSV. While it certainly is true that “the capacitance of parylene liner is much lower than that of SiO2 liner. This provides benefit in minimizing the signal delay, lowering power consumption, and reducing cross-talk between neighboring paths.” No consideration was given to the mechanical properties of Parylene HT.

HTParylene HT aka Parylene AF4, aka Parylene F has been reported in the literature for more than 35 years.  It was available commercially in the late 1990’s as Novellus AF4 when it  was thoroughly screened as a potential ILD Low=K replacement material. It was never implemented as a Low-K ILD for many reasons amongst which was the reactivity of the F with the Ta barrier layers in dual damascene structures.

Parylene (though not the HT product) has been examined as an insulator for 3D TSV  by the RTI group working on the DARPA VISA program since 2006 and by IMEC since 2008. The use of Parylene as a TSV insulation dielectric has been detailed in Chapter 7 of Volume 1 of the “Handbook of 3D Integration.”

[Garrou, Bower And Ramm Eds, Wiley VCH 2008]

While the Parylene family of products has found a nice niche as a protective coating for PC boards and medical components, it is NOT known for its superior mechanical properties.  While Parylene HT reportedly has superior thermal properties (vs other Parylenes) it’s mechanical properties remain poor as shown below.

HT properties

So the tensile strength of Parylene HT, is ~ 50 MPa and the elongation is 2%. The yield strength, i.e. the stress at which it begins to deform plastically is 35 MPa. These are not properties that I would want encapsulating a copper TSV which is known to undergo “copper pumping” and is known to exert so much stress that it cracks SiO2 liners as it expands.

Suffice it to say that I would examine mechanical reliability tests very carefully before implementing such materials into a 3DIC process flow.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 224 Ga Tech Interposer Conf 2: Laser TGV; NTK and Unimicron – Glass PCB reinforcement for high density laminates; Nvidia Pascal

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the GaTech Global Interposer Technology Workshop.


Krause of LPKF detailed their laser formation of through glass vias (TGV). They claim to be capable of forming 5000 TGV/sec. Their two step process is shown below.




They  are reporting that their prototype tool will be available in 2Q 2015 and available on the market in 4Q2015.


Seki of NTK described their work on glass core substrates which can be used as both interposer substrates and cores for high density laminate substrates.



The fabrication process is shown below:



Because of the high modulus, glass core has less warpage than laminate with or without dies.



With CO2 laser drilling cracks were observed in the polymer laminated glass, reportedly due to the CTE mismatch between the polymer and glass and the stresses induced by the laser drilling. The thicker the polymer coating the higher the induced stress.



2um L/S and 10um TGV appear possible for this system.


DC Hu of Unimicron reviewed their perspective on the “Glass as a Substrate Material for High Density  Interconnects”.

Their process flow for using glass sheet to replace woven glass core for PCB laminate is shown below. It has been run on a 508mm x 508mm panel size.

Unimicron 1


Techniques for L/S reduction are shown below:

unimicron 2


The embedded interposer carrier is an option to eliminate the solder joints between the interposer and organic substrate.

unimicron 3



Abe Yee of Nvidia described their program with TSMC and Hynix for their future gen graphics modules.

Nvidias GPU roadmap shows the 2016 entry of Pascal with 3D memory:

Nvidia 1


Yee comments that “Memory to GPU requires 2.5D with TSV”.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFLE 222 2014F IC Sales; SMIC joins group Acquiring StatsChipPAC; China to become a Consolidation “Predator”?

By Dr. Phil Garrou, Contributing Editor

IC Insights – 2014 Final Sales Leaders

According to IC Insights, this year’s top-20 ranking includes two pure-play foundries (TSMC and UMC) and six fabless companies.  The top four semiconductor suppliers all have different business models.  Intel is essentially a pure-play IDM, Samsung a vertically integrated IC supplier, TSMC a pure-play foundry, and Qualcomm a fabless company.

fig 1


IC Insights – S. Korean and Taiwanese Companies Control 56% of Global 300mm Fab Capacity

IC companies headquartered in South Korea and Taiwan lead the way in DRAM and flash memory and foundry services.

Samsung and SK Hynix currently account for 35% of global 300mm wafer capacity.  Samsung alone controls about 24% of all the world’s 300mm capacity.   Samsung and SK Hynix also both own big 300mm fabs outside of South Korea.  SK Hynix’s largest fab is in China.  Samsung also has a 300mm fab in China as well as two in the U.S.

Taiwanese companies currently manage 21% of the world’s 300mm capacity, with about 85% of that capacity being committed to foundry services.  The remaining 15% of Taiwan-controlled 300mm capacity is mostly used to produce memory devices.   There is only one Taiwanese-controlled 300mm fab located outside of Taiwan, UMC’s fab in Singapore.

fig 2


SMIC joins group buying STATSChipPAC

Our friends at Digitimes have reported that SMIC has joined the China group of China-based investors looking to buy STATS ChipPAC which includes Jiangsu Changjiang Electronics Technology (JCET).  JCET is China’s largest semiconductor chip tester with five production plants located in the provinces of Jiangsu and Anhui.

In Nov 2014, JCET made a $780 MM offer to acquire STATS ChipPAC. Negotiations are currently scheduled to complete at the end of the year.

Under the proposal, SilTech Shanghai (parent of SMIC) will put $100 MM into the deal. The IC Fund set up by the Chinese government is another co-investor. Incorporated in September 2014, the IC Fund is China’s national investment fund aiming to boost development of the local IC industry.

China to become predator for IC business consolidation during 2016-2020 ?

Digitimes also reports that they expect Chinas next 5 year plan (2016-2020) to reveal “…there is no doubt that China is likely to become one of the major predators for IC businesses during the period”. Further predicting that “…Taiwan-based IC design houses and IC backend service providers are likely to become the preys to be hunted by China-based IC companies.”

IFTLE 221 RTI 3D ASIP part 1: Global Foundries; Ga Tech

By Dr. Phil Garrou, Contributing Editor

It’s that time of year again when Hanna and Madeline wish a very Merry Christmas to all…

H & M


December is also the final 3D conference of the year, RTI Internationals 3D ASIP conference in Burlingame, CA. Over the next few weeks we will be looking at the remaining content from the GaTech Interposer Conference and the RTI 3D ASIP conference.

Global Foundries

Zafer Kutlu of GlobalFoundries updated the audience on the “Status of Manufacturing and Design of 2.5D Packaging Technology” at his company. The GF open supply chain includes EDA and IP partners Cadence, Synopsys and Mentor Graphics and OSAT partners Amkor, ASE, STATSChipPAC and SPIL and memory stack supplier Hynix.

GF 1


The ATACAMA test vehicle, was used for tool/line setup, base investigation on interposer design and processing, supply chain setup. The KALAHARI technology baseline qualification test vehicle, for CPI qualification and final inputs to DM and PDK.

GF 2


Kutlu announced that they would be ready with PDK Rev 1.0 in 1Q 2015.

Ga Tech

Muhannad Bakir of GaTech was invited to share his concepts on silicon bridge interconnects and 3D micro fluidic cooling solutions that he is working on for the DARPA ICECool program. Bakir was asked to “Bring the real Data” and that he did as you can see from the picture below.

Bakir brought Data to 3D ASIP

Bakir brought Data to 3D ASIP

Concept 1 is a linking interconnect technology that use self aligned silicon interposer tiles and bridges. The tiles are aligned using pyramidal pits etched in the silicon and mated with 300um solder balls (as shown below) The interposers can be linked and interconnected using the same ball and socket alignment concept. Connection between interposer and mother board or chip and interposer is made using the GaTech “spring”  interconnects as shown. Although I am not yet sold on using the spring connection in HVM, we will keep an eye on this technology as it is developed.

GT 1


The second concept pertains to microfluidic cooling for silicon interposer modules.

GT 3


Silicon dice with electrical microbumps, fluidic microbumps and vias, and micropin-fin heat sinks were fabricated and flip-chip bonded on a silicon interposer. Micro pin fins are etched into the back side of the chip and TSV created in the pin fins to connect to the next level.

GaTech 4


Compared to chips that are air cooled, the micro fluidic module shows significantly cooler operation (i.e. 98 C max vs 64 C max).

Stay tuned because working with Altera, they are creating such cooling channels in the backside of a live FPGA.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 220 GaTech Global Interposer Conference part 1 : Repeat After Me – “Panel Size, Equipment Set Cost and Yielded Throughput”

By Dr. Phil Garrou, Contributing Editor

GaTech Global Interposer Conference

The 4th Annual Global Interposer Technology Workshop At GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon. Some of the panel discussions I have seen discussing the pros and cons of various interposer alternatives have been at this meeting due to the broad technical scope of its attendees.

Joining Rao Tummala as co-chairs were Matt Nowak of Qualcomm and Subu Iyer of IBM.


Representing Yole Developpement I presented an update on 2.5/3D focusing on thee new 3D memory architectures which have been needed for silicon interposers to really take off.

Yole 1


The audience was also forced to endure my lecture on packaging nomenclature which is getting completely out of hand.

Leadframes, BGA substrates and pieces of silicon with high density wiring and TSV are all interposers. The term 2.5D was a joke and the term 2.1D or others such as 5.5D similarly are jokes with no technical meaning. What the laminate community is beginning to call 2.1D is simply a higher density BGA substrate.

yole 2



IyerIBM’s Subu Iyer, an IBM Fellow, IEEE Fellow and front end practitioner for many decades has been a long time supporter of this Global Interposer Conference.

Always one to speak his mind Subu was blunt and to the point on two key issues during the panel session at this conference; (a) interposer definitions and (b) the presumed interposer cost structure.

He agreed that 2.1, 2.5D etc. has no real meaning and is only confusing non packaging practitioners. Here is the now infamous exchange with Rao Tummala [link]

Subu: “I find the whole concept of 2.5D fairly atrocious. I have banned its use [in IBM].”
Rao: “what are you going to call it?”
Subu: “Interposers, like God intended it to be.”

While nomenclature is important to keep concepts straight, even more important was the discussion on the relative costs of silicon vs glass vs laminate interposers. Subu’s point was:

“…high density interposers will all cost the same whether glass or laminate or silicon…the cost is not materials dependent but rather density dependent”

This is a point  that I have been trying to make myself for a few years now on IFTLE since the concept of the glass interposer became all the rage. As Subu said, interposer costs will all be approximately the same if the densities are equal and the equipment sets are the same.  In the chemical industry, from whence I came, the rule of thumb was that raw materials were responsible for approx. 10% of the total cost.

The key is NOT that glass is a low cost material, but rather whether one can manufacture fine features on large glass panels . Panel size and equipment set cost and throughput (yielded) will determine the cost of glass interposers not (I repeat) not the fact that window pane is cheaper than a silicon wafer.

Low cost equipment to create high density features on  large panel substrates (which obviously won’t be silicon)  IS a worthy goal for both glass and laminate providers,  lets just not loose track of what the key factors are. PANEL SIZE…EQUIPMENT SET COST…THROUGHPUT

In fact, a t the 2011 GaTech Global Interposer Conference Yole Developpement predicted that panel lines would be required for 2.5D interposers to attain a low enough cost to be widely adopted in the chip packaging community [link]

GaTech Glass Panel Consortium

At the IEEE Global Interposer Technology workshop in Nov Rao Tummala announced the formation of a “Panel based Global Glass industry Consortium” for “low cost, ultra miniaturization, high performance and Si like ultra high IO interconnections to address both small and ultra small system needs such as smartphones, wearables, IoTs and medical systems.”

Tummala continued “ we started looking at glass in 2010….today we have 50 global companies involved…GaTech can now access the complete ecosystem to develop and apply this technology to single chips, with lower cost than todays packages, multi chip in 2.5D architecture, similar in IO pitch to todays Si interposers but at much lower cost and ultimately to 3D system architectures”

GaTech continued that they “are producing advanced 2D, 2.5D and 3D system packages in its 300mm panel facility and looks forward to transferring the technology to 510mm panel fabs.”

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 219 Amkor responds to Samsung Plated Mold Via; TSMC INFO factory, 3D Memory Stacks finally arrive

By Dr. Phil Garrou, Contributing Editor


At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared below.

samsung em 1


Samsung EM describes the driving force for this new technology as the added adhesion that they get by replacing the solder TMV fill with copper in the PMV.

Seeking input from Glenn Rinne of Amkor, IFTLE found out that Amkor has run both processes and seen that the laser formed vias have both cavities and protrusions in the via walls due to the filler in the mold compound. The cavities serve as a “roughness” which anchors the solder fill and the filler particles protruding into the vias actually shadow the deposition of seed layer when copper is plated into the holes so they concluded that the solder, which is “conductive enough” actually shows better adhesion and is a cheaper process.

TSMC Continues move into packaging

TSMC is purchasing a plant in Longtan, Taiwan from Qualcomm for $85MM and turning it into a facility devoted to the development of the advanced integrated fan-out wafer-level packaging (InFO-WLP) technology. TSMC could initiate manufacturing as early as 2016 on 16nm chips, but HVM date will depend on “customer demand” [link]

TSMC and Samsung battle for Apple and Qualcomm Orders

It is reported that both Apple and Qualcomm will likely buy a larger proportion of 14 nanometer smartphone chips from Samsung rather than TSMC beginning in the second half of 2015 [link].

Given that Samsung has more advanced manufacturing technology to produce fin field-effect transistor, the company is reportedly more likely to win Apple’s contract for A9 processor production, said research institute Bernstein Research.

The Commercial Times reports that Qualcomm has already started working with Samsung to develop the chips. The Economic Daily News adds that Qualcomm has already placed orders with Samsung.

3D Memory Stacks Finally Arrive

For those of you struggling with all the new memory architectures that have been announced, I recommend the recent article by Yole Developpement which details announcements by Hynix, Samsung, Micron and Tezzaron [link]. With the recent Samsung announcement of mass production of 64 GB DDR4 DIMMs that use TSV technology for enterprise servers and cloud-based applications, all three of the major DRAM memory manufactures, Samsung, Hynix and Micron, have now announced the commercialization of TSV based memory architectures.



Different applications will have different requirements in terms of bandwidth, power consumption, and footprint. As we move into 2015 several industry segments have announced applications using the new memory stacks. Intel recently announced that their Xenon Phi processor “Knights Landing,” which will debut in 2015 will use 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth for high performance computing applications.  AMD and Nvidia have also announced the use of HBM in their next generation graphics modules like the Nvidia Pascal due out in 2016.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 218 IMAPS 2014 contd: K&S Thermo compression, Shinko 3D stacking, Samsung High Density Organic Interposers

Continuing our look at the 2014 IMAPS Conference held in San Diego…


Colosimo of K&S examined high productivity Thermo-compression FC bonding. In traditional FC assembly, the chips are tacked down to the substrate and then solder joints are melted and mass reflowed in an oven. Mass reflow (MR) becomes more difficult as the pitch of the solder bumps becomes finer due to control of solder flow and warpage of the package when the die and substrate are heated and cooled together. These issues are exacerbated for thin die and die stacks. Thermo compression (TC) was developed to locally heat the solder without subjecting the entire substrate to the heating and cooling cycle.  This requires the bond head heat past the MP of the solder and then cool down to a low enough temp to pick up the next die from the wafer mounted to tape. Current tools today can do this in 7 to 15 seconds (a few hundred units/hr) which is substantially slower than todays standard FC process.

The newly developed K&S TC  tool reportedly can process 1000-2000 chips/hr.


Shinko detailed their studies on 3D stacking an SoC die and a memory die in a SiP package.  The fig below shows X-sectional image of the 3D Sip. The structure has a bottom die (6mm sq) with TSVs, stacked on an organic substrate and a top die (9mm sq) stacked on the back side TSV of the bottom die. The bottom die has 10um TSV on 40um pitch.

Shinko 1


MEOL (mid end of line) processing flow is shown below. The bottom wafer with copper pillar bumps on its front side and blind TSV is attached to a carrier and thinned to expose the TSV and passivated. The carrier is debonded and the die are sawn for assembly.

shinko 2


The figure below shows the die stacking and packaging flow. The bottom die with copper pillar bumps is assembled onto the BGA substrate. Next the microbumps on the top die are bonded to the TSV pads of the bottom die. The finished assembly is encapsulated and solder balls are attached to he BGA package.

BLR (board level reliability) comprising Temp cycling ad drop testing is shown in the following table. Weibull plot of temp cycling shows first failure at 2,344 cycles and 0.1% failure at 1194 cycles.

shinko rel


Samsung EM

Samsung Electromechanics examined the fabrication of Fine featured organic interposers. The next gen packaging such as wide IO memory – logic packaging (JEDEC requires min bump pitch of 40um) requires connection on less than 50um pitch. The Samsung EM process flow using photoimageable build up layers reportedly is capable of less than 5/5 L/S with micro-vias on 50um pitch. The layers can be connected with Vias with min 10um dia.


Univ. Texas

Paul Ho’s group at U Texas has examined the impact of copper grain structure and material properties on via extrusion in 3D interconnects.

The copper vias they examined were 5.5 x 55um in 780um thick Si. In sample A the copper grain size was uniform. In sample B the copper grains were a mixture of large and small grains. The average elastic modulus for A TSV were 117 MPa and for B 93 MPa. TSV extrusion was found to be 117nm for A and 147nm for B. The smaller more uniform grains were found to exhibit higher yield strength and therefore less via extrusion. Stronger Cu/Si interfaces are also shown to achieve less via extrusion.

GaTech Mechanical Eng

Charles Ume of GaTech reported on his studies detailing the effect of bump pitch, package size, Mold compound and substrate thickness on PBGA warpage.

FEA studies reveal that solder bump pitch, package size and mold compound thickness affect he maximum PBGA thickness significantly, but substrate thickness does not.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 217 IMAPS 2014 Contd: Glass Interposers and Panel Processing

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2014 IMAPS Conference held in San Diego…


Shorey of Corning Glass gave an update on glass panel fabrication. He noted that “there are challenges in applying standard plating processes to glass,” but Autotech has recently reported significant progress in the ability to metallize glass vias using new adhesion promoters. They show complete fill with little overburden in 80um holes in 300um glass.

They also showed 370 x 470 x 0.3mm glass panels. A Rudolph Jetstep S3500 was used to create “~3um L/S…with additional work we fully expect to be able to resolve < 3um L/S”.  Smallest vias shown were 35um in 100um glass.

Corning 1


Rudolph Technologies

In an aligned presentation, Ruhmer of Rudolph discussed high resolution patterning to enable panel based advanced packaging.

When examining litho steps for panel processing Rudolph points to the following key items: minimum resolution, overlay accuracy, sidewall angle and CD control, depth of focus (DoF), exposure field size and warped panel handling capability.

– optical characteristics of suitable litho systems should offer N/A of 0.1 to 0.15 in order to meet L/S resolution requirements for high density interposers (1-2um)

– depending on the complexity of the interposer 5 or more mask layers per side can be required. In general the overlay accuracy should be ~ 1/3 the resolution limit of the system, so for a resolution of 1.5um the overlay accuracy should be 0.5um. Reconstituted substrates for FO-WLP is more complex due to die shift.

– accurate focus control across the wafer is required for tight CD control and consistent sidewall angle in photo dielectrics

– depth of focus for back end processing requires 10um or greater range, not typically available in front end steppers.

– exposure field size should at least cover one die to avoid stiching.

– in initial panel based FO-WLP testing warpage of approx 10mm was observed for a Gen 2 glass panel. Equipment with  warped handling features like switchable and compliant gaskets on chucks and handlers ae needed for litho and other processing steps.

Corning / Unimicron / Qualcomm

Corning, Unimicron and Qualcomm reported on their low cost interposer development program.

They sought to show feasibility of interposer manufacturing on their 200um thick 508 x 508mm glass panel format. Daisy chains are connected with 100um TGV (through glass vias) and 8/8 L/S.

The process flow using ABF dielectric is shown below.

corning-unimicron-qualcomm 1


Early handling led to glass breakage. The ABF lamination (Ajinomoto) gave the thin glass panel mechanical support more handlable.  Then vias were created through the ABF.

Warpage of the glass panels were compared to laminate (BT) panels of the same size with 200um core thickness. The glass panels showed 3X lass warpage.


DNP reported on a comparison of fabrication processes and electrical performance of silicon and glass interposers. I should note that these appear to be DNP processes, not necessarily standard processes. For instance they comment that silicon is fabricated on 200mm lines but glass can be fabricated on large panel lines. The facts actually are that Si is fabricated commercially on 300mm lines and large panel glass interposers are in R&D stage.

Their silicon and glass processes ae compared below.



In the silicon process, the holes are formed by ICP-RIE. The wafer is then thermally oxidized and coated with PECVD SiN. The holes are seed sputtered then plated with Cu, CMP’ed and both sides covered with Cu/PI RDL. TSV are on 200um pitch.

In the glass process, 50um TSV on 200um pitch are formed in 0.3mm glass by focused electrical discharge (Recall AGC is a proponent of this method). After Ti/Cu seed the vias a electroplated with copper and the surfaces CMP’ed. Copper / PI RDL are added to both sides.

Glass interposers showed better high freq. performance than silicon as was expected.




Mori of Shinko described their development of Glass Interposers with fine pitch ubumps and their warpage results. They examined glasses with CTE’s of 3.2 and 9.5 ppm and corresponding moduli of 73 and 90 GPa. Their design rules are shown below.

Shinko 2-1


Three laminates were examined with properties shown in the table below:

shinko 2-2


Warpage of the die on interposer on substrate showed that warpage of the assembled stack is lowered with lower CTE laminate substrate but is not affected by the CTE of the glass Interposer. Modeling verified these results.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 216 3D ASIP Program; 2014 IMAPS part 2: MR for Amkor Copper Pillar Bumps

By Dr. Phil Garrou, Contributing Editor


It’s that time of year again to be thinking about registering for the RTI sponsored 3D ASIP (Architectures for Semiconductor Integration & Pkging) which will be held at the Burlingame Hyatt on Dec 10-12 [link].

RTI ASIP has been focused on 3DIC and 2.5D for 11 years now. As we are now finally seeing  commercial commitment from the memory suppliers and the graphics module manufacturers hopefully we are observing 2.5/3DIC  finally taking off. Unlike other, more academic conferences, RTI ASIP has always been focused on the commercial and business aspects of bringing 3DIC to the market place.

This years program includes two special pre-conference symposia . A  ½ day symposia 2.5/3D IC design tools and flows led by Herb Reiter will include speakers from Cadence, Mentor, Apache design, GF, Rambus and Qualcomm. There will also be a half day tutorial on the current state of the art in 2.5/3D processing led by yours truly with “drill and fill” covered by Dean Malta of RTI; Temp bond and via reveal presented by Severine Cheramy of Leti and assembly presented by Laura Mirkarimi of Invensas.    As a special bonus, those attending the processing tutorial will receive a free copy of “The Handbook of 3D Integration Volume 3: 3D Process Technology” edited by Garrou, Koyanagi and Ramm.

The regular conference includes presentations by Micron, Xilinx, Nvidia, GF, Synopsys, Nanium, Unimicron ad many more . Of special interest should be the updates on their DARPA ICECool  3D cooling programs by Bakkir of GaTech and Gaynes of IBM Watson and the IoT (Internet of things) presentations by Beica of Yole and Schulz of the silicon integration initiative.

Hope to see you there.

Amkor – Extending Mass Reflow to Finer Pitch Copper Pillar Bumping

Another key paper from the recent 2014 IMAPS Conference in San Diego was by Fernando Roa of  Amkor concerned with extending the current processing envelope for Copper pillar bumping using mass reflow (MR).

Thermo compression (TC) is typically applied for copper pillar bumping. In general, it is a slower more expensive assembly process since each die has to be positioned and mated before moving on to the next die. A bonding head is typically used to hold the die flat and in alignment with the substrate while heat is applied to complete the connection. In general MR throughput is 2X that of MR.

In contrast, MR bonding places the die and then reflows them all at once.  Std FC attach and capillary underfill is shown below vs thermo-compression (TC) bonding.  TC typically underfills with non conductive paste (NCP) or film since capillary underfills are more difficult to use with copper pillar bumps because of their fine pitch.

amkor 1


Amkor typically uses the MR process flow for copper pillar bump (CPB) from 200 to 100um pitches with minimum changes to the standard process flow.

For fine bump pitch (b), since the bumps are much closer together there is less room to create solder mask defined pads as show below. Since the bump diameter is close to the typical width of the trace they are allowed to form connection directly on the trace.

amkor 2


While typical MR assembly relies on solder self alignment during reflow, MR of solder to trace is more difficult since self alignment to solder catch pads is not possible. In MR of fine pitch bumps the solder wraps around the trace in contrast to TC joints that typically show solder squeezing out of the joints because of the compression.

Very precise selection and control of die thickness, substrate construction and substrate finish is necessary to reduce or eliminate solder shorts and non wets. Roa indicates that Amkor efforts are underway to extend MR to finer pitch bumping activities.

IFTLE 215 STATS Acquisition; Will SLIT replace TSV?

By Dr. Phil Garrou, Contributing Editor

Rumors on the SCP Acquisition

We have discussed the Acquisition of STATSChipPAC (SCP) in recent blogs [see IFTLE 195,  “STATS in play….” and IFTLE 198, “….STATSChipPAC suitors named…”.] In late August, Bloomberg News reported that Jiangsu Changjiang Electronics (JCET) and Tianshui Huatian Technology were working on offers for SCP [link].

IFTLE continues to hear rumors from multiple credible sources that the deal with JCET is imminent and that final price is being negotiated. While denials are being floated by JCET, we all recall that similar denials were also rampant in the recent IBM / GF deal till the last minute.

IFTLE is also hearing that during these negotiations SCP, like IBM, is loosing key personnel throughout the organization. But, whereas IBM personnel movement was to ultimate acquirer GF, not so for SCP and JCET. Rumors from SCP indicate that JCET will not be retaining any key Singapore management in an effort to lower their cost position. As JCET waits to lower the ultimate acquisition price, IFTLE believes they are also lowering the overall value of SCP. A company is its people!  There are also unsubstantiated rumors of customers leaving SCP because of this chaos.

While it may be 2015 before the deal is consummated, IFTLE can see SCP falling from the #4 OSAT position and is probably already behind PTI.

Will SLIT replace TSV?

At the recent IMAPS meeting in San Diego Xilinx and SPIL presented the paper “Cost effective, high performance 28nm FPGA with new disruptive Silicon-less Interconnect Technology (SLIT).

In the traditional Xilinx silicon based FPGA module the FPGA die with microbup interconnect are connected to the 4 layers of 65nm interconenct on the silicon inerposer which then has TSV and c4 bumps to connect power/grd and other incoming sgnals.

In the new SLIT technology the same FPGA slices are mated to 65nm intrconenct on silicon but no TSV are required since ther is selective Si removal and backside contact formation along with required inline wafer warpage control. The structure is EXPECTED to give lower cost while delivering better electrical performance. The structures are compared below.

TSV “drilling and filling” are eliminated as are thin wafer handling, backside reveaand many inspect and metrology steps.

xilinx 1


(a) traditional Xilinx FPGA with silicon Interposer; (b) FPGA without interposer

Xilinx 2


(C) SLIT in X-section

The 65nm interconnect are created on std bulk silicon The bottom most dielectric layer is selected to have high selectivity during subsequent backside etch. The top of the metallization interconnect layer is capped in 45um pitch pads and microbumps.

The FPGA die are  thinned diced and stacked onto the interconnect wafer. After reflow the ubump gap is underfilled and overmolded and the mold cmpd is ground down to expose the die top surface.

Subsequent wafer thinning is done to the dielectric etch stop layer.  Contact holes re etched in the dielectric and pads and balls are created/placed.

The main processing issue is wafer warpage, especially after the full silicon removal. Stresses are balanced with a reinforcement layer and other stress controls during the processing.

This is certainly a very interesting proposed structure and IFTLE will be keeping an eye on SLIT processing.

More from IMAPS in subsequent blogs

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