GlobalFoundries 2.5 / 3D at 20nm
Dr. Phil Garrou,
A year ago, GlobalFoundries (GF) CTO Bartlett announced the installation of TSV production tools for the company's 20nm technology platform and announced that "the first full flow silicon with TSVs was expected to start running at Fab 8 (Saratoga, NY) in Q3 2012 with mass production expected in 2014 and the 2.5D line (their 65 nm Fab 7 line in Singapore) had a similar time schedule as the 3D line in the United States."
In early April, GlobalFoundries announced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in N.Y., the silicon foundry vendor manufactured TSV test wafers using their 20nm-LPM process technology, and at Fab 7 in Singapore, the company demonstrated a 65nm 32mm x 26mm interposer test vehicle for 2.5D chips. Both 2.5D and 3D are set for a 20nm introduction, full qualification by next year and non-early adopter production in 2015.
They are using a 6 x 60 ??m vias middle, copper TSV as shown in the figure below. Interposer size is limited by reticle size (i.e., 25-30 mm).
Dave McCann, VP of packaging technology at GlobalFoundries, reports that GF is taping out a 3D design for an undisclosed customer and is working with two others on 2.5D. "2.5D is already here," he added. Several 2.5D test structures were shown that were collaborations with Amkor.
While foundries TSMC and Samsung are both offering turnkey solutions, GlobalFoundries and UMC are supporting a partnering ecosystem where they will handle the traditional front-end steps and the "via creation" process and then will hand off the traditional backend steps such as temporary bonding/debonding, grinding, assembly and test to traditional packaging houses such as ASE, Amkor SCP and SPIL.
A year ago, GF announced hopes of shipping 28 and 20nm 3D chip stacks in 2014. Now, GF states only the 20nm chips will be used in stacks and they may not ship in volume till 2015.
Hybrid Memory Cube Consortium
In related news, consider the current status of the Hybrid Memory Cube (HMC). ARM, HP, and SK Hynix joined former members including Micron, Samsung, Altera, IBM, Microsoft, AMD, Fujitsu, ST Micro, Marvell and Xilinx in June 2012.
|GLOBALFOUNDRIES utilizes a "via-middle" approach to TSV integration, inserting the TSVs into the silicon after the wafers have completed the Front End of the Line (FEOL) flow and prior to starting the Back End of the Line (BEOL) process. This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material.|
The group has recently issued version 1.0 of its specification for a vertical memory stack with a defined logic-layer interface. The group is reportedly changing focus to higher-speed variations of a DRAM stacked using TSV technology. They want to increase data rate across modules from the current 10 - 15 Gb/sec up to 28 Gb/sec.
Micron said it will deliver engineering samples of 2 and 4 Gb versions of the stack by this summer with commercial production scheduled for late 2013 or early 2014.
High-speed networking vendors will probably be the first to commercialize with HPC-centric applications next in line. Initial HMC implementations will be DRAM, but multi-memory stacks that employ NAND flash and DRAM are expected to follow.
Solid State Technology | Volume 56 | Issue 3 | May 2013