Insights into low frequency noise in high-mobility transistors
EDDY SIMOEN, imec, Leuven, Belgium
The impact of high-mobility channel materials and novel device architectures on the low-frequency noise behavior of 22nm and below CMOS transistors is reviewed.
The implementation of novel high-mobility channel materials (SiGe, Ge, III-V) and the use of advanced device architectures (thin films on UTBOX, FinFETs and nanowire transistors) in upcoming CMOS nodes strongly affect their low frequency (LF) noise performance [1,2]. Both 1/f noise and gate-voltage dependent generation-recombination (GR) noise can be found in silicon bulk FinFETs. The flicker noise mechanism can be governed both by number and mobility fluctuations in the same wafer, while the GR noise, normally ascribed to trapping in the gate dielectric, causes a significant variability of the power spectral density (PSD).
Impact of high-mobility channels
It has been shown that the implementation of strained SiGe channels not only boosts the device performance [3,4] but at the same time, can result in a lower noise PSD, when the channel is off-set from the interface [5,6].
|Figure 1. Current noise PSD versus frequency, corresponding with p-type SiGe-channel BFFs fabricated on a (110) Si substrate, respectively, with L=1 mm and different Wfin.|
To study the impact on the noise, a comparison is made with planar implant-free quantum well (IFQW) pMOSFETs, exhibiting mainly 1/f noise which is governed by mobility fluctuations, based on the behavior of the normalized current PSD versus the channel current in linear operation. Contrasting LF noise spectra (FIGURE 1) and PSD (FIGURE 2) are seen for (110) and (100) SiGe p-channel bulk FinFETs. While the (100) devices exhibit similar behavior as the planar references, the (110) structures suffer from excess GR noise, especially for larger widths. This is associated with the faceting of the SiGe QW, which introduces extended defects in the material.
|Figure 2. Normalized noise spectral density versus drain current Id for a number of p-type SiGe-channel BFFs fabricated on (100) and (110) Si substrates, at f=25Hz.|
The reduction of the 1/f noise in SiGe buried channel pMOSFETs is well documented in the literature [5-8] and has recently also been demonstrated for SOI pFinFETs . In case the PSD is related to number fluctuations, this reduction can be ascribed to the larger tunneling distance and the valence band offset of the SiGe QW with respect to silicon, which reduces the number of accessible traps in the gate dielectric. At the same time, the presence of extended defects in (Si)Ge channel pMOSFETs can contribute excess GR noise , as in the case of the (110) channel devices reported here. These extended defects are related to the faceting of the epilayer. This also gives rise to a higher density of interface states, where both top and sidewalls are according to different (110) lattice planes. In spite of this, the highest hole mobility is obtained for the (110) based SiGe-channel pMOSFETs, which can be ascribed to the favorable channel orientation compared with (100) silicon substrates.
LF noise variability
A general tendency for the noise of transistors with nanometric device dimensions is the large, orders-of-magnitude variability of the noise PSD, which is usually due to the presence of random telegraph noise (RTN), associated with traps in the gate oxide. A similar variability has been found in Si bulk FinFETs  or in SiGe channel bulk FinFETs. A detailed numerical simulations' analysis has recently been reported , investigating the role of the position of the RTN trap with respect to the channel on the induced relative current switching amplitude ??Id/Id.
|Figure 3. Normalized noise current spectral density versus drain current at f=25Hz and in linear operation for a set of 1mm x 0.105mm UTBOX SOI nMOSFETs, aligned across the vertical diameter in the center of the wafer.|
|Figure 4. Correlation between the input-referred noise PSD SVG@VT at 25 Hz versus threshold voltage for 1 mm x 0.105mm FD UTBOX SOI nMOSFETs on the same wafer in linear operation (VDS=50 mV).|
However, it has also been noted that the responsible 1/f noise mechanism for bulk FinFETs changes from number to mobility fluctuations within the same wafer and from die to die . This implies other possible origins of the PSD variability. Therefore, a more systematic study of the LF noise variability has been undertaken in UTBOX SOI nMOSFETs, developed for 1-transistor (1T) Floating-Body RAM (FBRAM) memory applications, with a BOX thickness of 10 nm and a film thickness of 10 or 20 nm. The impact of the presence of extensions has also been evaluated. An example is given in FIGURE 3, whereby no clear correlation has been found with the corresponding variability in the DC parameters, like the threshold voltage (FIGURE 4). From comparing FIGURES 5 and 6, it is derived that the higher LF noise PSD is due to excess GR noise, which in many cases exhibits gate-voltage dependent parameters (corner frequency f0 and plateau amplitude SI(0)).
|Figure 5. Low-frequency noise spectra around VT for a 1 mm x 0.105mm FD UTBOX SOI nMOSFET exhibiting predominantly 1/f noise around 25 Hz.|
|Figure 6. Low-frequency noise spectra around VT for a 1 mm x 0.105mm FD UTBOX SOI nMOSFET exhibiting two GR noise components, one showing gate voltage dependence while the other one does not.|
LF noise model for FD thin-film or narrow-fin devices
While gate-voltage-dependent Lorentzians are usually ascribed to traps in the gate oxide , we have shown that in the case of FD devices, GR centers in the Si film (or fin) can give rise to the same behavior. We have also shown that the SRH time constant can vary significantly with gate bias, as this modulates the electron quasi-Fermi level with respect to the trap level position ET.
Our model has some important implications. First, it provides a tool for GR defect spectroscopy in advanced FD or narrow-fin devices: from the VGS at maximum plateau amplitude, one can readily derive the trap activation energy, as ET coincides with the calculated EFn. Combining with the calculated free carrier densities, one may derive the electron and in some cases also the hole capture cross section from Eq. (2). Finally, the trap concentration follows from SI(0). This is equivalent to changing the temperature in PD or bulk devices , resulting in the construction of an Arrhenius plot. However, here the Fermi level is modulated by the gate voltage instead of the temperature. It has been verified that both analysis methods yield the same activation energy for the trap levels, responsible for the GR noise. In case of two independent gates, like for SOI devices with UTBOX, the back-gate voltage provides an additional degree of freedom to scan the band gap of the semiconductor.
A second important consequence is that the model provides an alternative explanation for the variability of the noise PSD in thin-film or narrow-fin structures: GR noise amplitude can be varied over more than a decade, depending on the position of the Fermi level with respect to the trap energy. It is the energy level position in the band gap which is responsible for the variability of the noise PSD induced by defects in the FD silicon film or fin. Additional GR noise variability can be induced by device-to-device variations in the threshold voltage, as this will equally modify the quasi-Fermi level with respect to the trap level for the same operation voltages.
A third consequence specific to 1T FBRAM devices on UTBOX SOI substrates is that there is a correlation between the retention time and the PSD. . The retention time is in this case defined by the degradation of the ???0'-state by hole generation through defects in the silicon film or at the interface (Gate-Induced Drain Leakage) [13,14]. It indicates that LF noise is also a useful tool for the study of the hole generation centers responsible for the degradation of the 0-state in these 1-transistor memories. Finally, it is shown that the application of the model to bulk FinFET devices is straightforward.
1. E. Simoen et al., IEEE Trans. Electron Devices, 58, 3132 (2011).
2. E. Simoen et al., IEEE Trans. Electron Devices, 59, 1272 (2012).
3. Y. Sun et al., J. Appl. Phys., 101, 104503-1 (2007).
4. J. Mitard et al., IEDM Tech. Dig., 249 (2010).
5. C.-Y. Chen et al., IEEE Trans. Electron Devices, 55, 1741 (2008).
6. S.-L. Wu et al., Jpn. J. Appl. Phys., 48, 04C036-1 (2009).
7. F. Li et al., IEEE Electron Device Lett., 31, 47 (2010).
8. S. Deora et al., IEEE Electron Device Lett., 32, 255 (2011).
9. B. Rajamohanan et al., IEEE Electron Device Lett., 33, 1237 (2012).
10. M.-L. Fan et al., IEEE Trans. Electron Devices, 59, 2227 (2012).
11. I. Lartigau et al., J. Appl. Phys., 101, 104511-1 (2007).
12. E. Simoen et al., accepted for presentation at ESSDERC/ESSCIRC.
13. T. Nicoletti et al., IEEE Electron Device Lett., 33, 940 (2012).
14. M. Aoulaiche et al. IEEE Trans. Electron Devices, 59, 2167 (2012).
E. SIMOEN, T. ROMEO, L. PANTISANO, A. LUQUE RODR??GUEZ1, J.A. JIM??NEZ TEJADA1, M. AOULAICHE, A. VELOSO, M. JURCZAK, R. KROM, J. MITARD, CH. CAILLAT2, P. FAZAN2, F. CRUPI3, and C. CLAEYS4; Imec, Kapeldreef 75, B-3001 Leuven, Belgium. Tel.: +32-16-28 13 81, Fax: +32-16-28 17 06, Email: Eddy.Simoen@imec.be; 1University of Granada, Spain, 2Micron Technology Belgium, Leuven, 3University of Calabria, Italy, 4also at KU Leuven, Belgium. Originally presented at the 2013 International Electron Devices Meeting.
Solid State Technology | Volume 56 | Issue 2 | February | 2013