3D IC with TSV: Status and developments
E. Jan Vardaman,
TechSearch International, Inc.
While the drivers for 3D ICs remain performance and form factor, the time line for its adoption keeps shifting out into the future. Several technical challenges and infrastructure issues such are delaying high volume manufacturing of TSV technology for 3D ICs. Until these issues can be resolved, alternative packages will continue to be used.
On the technical side while there has been a lot of progress in via formation and filling, there are still some process steps that impact yield and have low throughput such as the debonding step during wafer thinning. The problem is combo material and equipment problem. New materials are being introduced and show promise, but engineering requires time. Stacking memory would seem to be the first step, but has proved to be challenging. 3D IC solutions without a debond step have been introduced by Tezzaron using its architecture and a novel process to stack memory was introduced by Elpida before it went in bankruptcy.
Many companies show a silicon interposer or 2.5D solution on their packaging roadmaps where a logic device is mounted next to a stack of memory and the through silicon vias are in the substrate. The problem is that this assumes stacked memory with TSV is commercially available at a cost/performance ratio that matches the requirements. With the stacked memory unavailable this pushes out the adoption of even 2.5D. Some companies also indicate that the cost of the silicon interposer is too high and they would like to consider a glass interposer or even a high-density organic substrate. At this time, glass interposers with TSVs are not commercially available and organic substrates with fine features are still in development.
|Effect of Interposers on 3D IC Forecast|
For stacks of memory and logic the industry still needs thermally aware design tools and even new thermal solutions for stacks that contain logic and memory. Where there has been progress on test methodology development, additional work is still needed. Commercialization of EDA tools will benefit the industry greatly.
Once the 3D IC technical challenges are resolved and the technology becomes cost-effective, business challenges will remain until the industry settles on a model. According to ASE, the industry will use multiple models depending on the customer and the foundry.
Many approaches to 3D packages exist, including stacked die with wire bond or wire bond/flip chip, stacked packages, package-on-package (PoP), and chip-on-chip (CoC). Companies plan to continue the use of today's 3D packages with evolutionary improvements and adopt a 2.5D or interposer solution until 3D IC challenges can be met. It is important to remember that new package technology introduction takes time and the process and infrastructure have to be well developed: Xilinx spent 6 years to develop its now famous FPGA partitioned die on silicon interposer with TSV solution.
Solid State Technology | Volume 56 | Issue 2 | February | 2013