2013 technology forecast: Unprecedented challenges ahead
We asked leading industry experts to give us their perspectives on what we can expect in 2013. The challenges ahead include 450mm, FinFETs and 3D NAND, TSVs and 3D integration, and sensor fusion.
Vice President and General Manager, Silicon Systems Group, Applied Materials
Multiple inflections will figure prominently in 2013. Among these, we see the foundry transition to 20nm process technology node as a significant milestone. 20nm is all about building advanced transistors that can deliver low leakage, low power and high performance in a smaller footprint. To achieve this combination of performance and energy efficiency, chip makers must adopt high k metal gate transistors which could deliver a 20 percent savings in power consumption while offering a 15% increase in speed. Further leakage and speed performance improvements at 20nm and below will be gained from FinFET transistors. Beyond advances to the transistor, we expect major inflections in lower resistance interconnects, advanced patterning, packaging, and 3D NAND flash technology.
We've never seen in this level of change in the industry or this pace of manufacturing process development. Innovations in new semiconductor materials, manufacturing processes and other technologies will be needed to support these inflections that each pose critical challenges. Unprecedented precision engineering will be needed to manufacture chips features measured in nanometers. At these dimensions every atom counts and controlling variability is vital to meet performance and productivity targets. Also pivotal in enabling future chips will be new classes of materials with superior properties that can be used in a broad range of process applications.
With demand for new forms of consumer electronics and new methods of computing driving the pace of innovations, we're going to see more changes in the next five years than we've seen in last 15. These innovations will require major research and development efforts and very early and close collaboration across the industry.
Arthur W. Zafiropoulo,
Chairman and CEO, Ultratech, Inc.
After all the speculation, discussions and debates, the transition to 450mm wafers will happen. As an equipment manufacturer, it is not enough to simply survive, but it is imperative to thrive in the transition to 450mm. While driven by all the major semiconductor companies, the transition to 450-mm wafers will have a compounding effect on equipment manufacturers' R&D investments. By combining the technology challenges and the wafer diameter change, companies in the equipment industry will require a strong balance sheet to be successful.
Smart companies know that success lies in the ability to be bold and aggressive in R&D and remain conservative on the balance sheet. Success is also determined by a company's efforts to prepare for the future by investing and developing the right technologies and supporting capabilities. By developing innovative technologies that address the critical issues around the transition and adoption, companies can play an enabling role for 450mm.
Richard Gottscho, Ph.D
., EVP - Global Products, Lam Research Corporation
The semiconductor industry is evolving and facing unprecedented technology and economic hurdles. Limits imposed by planar technology and a stalled lithography roadmap threaten to slow down the rate at which density, cost, and speed improvements can be made. As this industry has shown before, however, there is more than one way to skin a cat. FinFET devices offer superior speed at lower power consumption. 3D NAND enables bit scaling of flash memory without the need of lithography roadmap extension. Multiple patterning extends the lithography roadmap. Through-silicon via (TSV) technology brings increased density, lower power consumption, and faster computing to mobile applications. But, these inflection technologies have their own set of challenges.
FinFETs are challenging to etch because the 3D topography requires long over-etching to clear corners; etching selectivity becomes of paramount importance. Atomic-scale precision is required across not only the wafer, but also from wafer-to-wafer and from fab-to-fab. Etch costs increase for all these reasons. FinFET metal gates have high-aspect-ratio features that must be filled without voids with thin, conformal, low-resistivity diffusion barriers using atomic-layer deposition.
Executive Technology Director, EV Group
The Internet of Things is about more than just gathering information through ubiquitous sensors. Huge amounts of data need to be affordably stored and analyzed, in order to be useful, which requires keeping Moore's Law alive. Fortunately, new semiconductor 3D manufacturing technologies are poised to play a critical role in further commoditizing memory and processing power. In 2013 high volume production of true 3D technology will commence. The industry will also see intensified wafer level developments particularly around image sensors and memory, as new DRAM designs allow for monolithic integration at the wafer level. Wafer-to-wafer bonding processes, combined with built in self-test, error detection and correction are poised to overcome one of the few remaining hurdles to high-volume, low-cost 3D manufacturing.
VP & GM, Electronics Business Unit, FEI
Consumer demand for more power, speed and functionality in less space seems to be insatiable. Yet semiconductor manufacturers have reached the end of the era when this demand could be satisfied by simply shrinking the dimensions of fundamental planar device technologies. Now they must accommodate complex, three-dimensional (3D) device architectures and a plethora of new materials. At the package level they must develop and produce 3D designs that stack and interconnect multiple die without sacrificing yield or performance. The net result of all this innovation is a sharp increase in R&D capital intensity. In order to maintain profitability manufacturers must increase the productivity and return from their R&D investments. Moreover, time-to-market has become the new battle ground where the first to market enjoy a brief period of premium pricing and higher margins, before the battle begins again.
At the moment, the MEMS industry is experiencing tremendous growth, driven largely by numerous consumer electronics products whose MEMS components, both multiple and varied, are finding their way into people's everyday life. Whereas before a phone had a single microphone, today's high-end smart phones may have as many as three microphones for noise suppression using advanced beam forming audio techniques. This and other high-end consumer applications for devices such as accelerometers, gyroscopes, and MEMS oscillators are the likely drivers in analysts' predictions for a 15 percent compound annual growth rate (CAGR) over the next five years.
Senior Vice President and General Manager, Silicon Engineering Group, Synopsys, Inc.
Whenever we communicate with our mobile phones, catch up on the latest news in our tablet computers, or snap those memorable holiday family photos with our digital cameras, we are relying on an indispensable semiconductor technology: the NAND flash memory. Over the past two decades, NAND flash memory has become one of the linchpins of the semiconductor market with revenues of approximately $21B in 2012 according to iSuppli. As in other semiconductor technologies, NAND flash evolution has been driven by density, performance and cost improvements. And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures. Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling.
Chief Technology Officer, SAFC Hitech
We are in an age where chemistry is center stage in the race to advance Moore's Law and More Than Moore. The continued drive towards smaller feature sizes, increased performance, and lower power consumption requires highly complex architectures using new materials and advanced process technologies. This is primarily true for processes in which physical vapor deposition (PVD) is being displaced by atomic layer deposition (ALD) and chemical vapor deposition (CVD). For example, materials are being developed to form high purity functional layers for applications in logic, memory, and interconnect areas, all within given thermal budgets
Vice President, Sales and Marketing , Entrepix, Inc.
One of the biggest challenges for the industry is that 80 percent of the devices used for portable and mobile applications are currently manufactured on 200mm or smaller wafers. How this plays out going forward could change who the dominant players will be and therefore could drive consolidation. As the communications market advances, design wins play a large role in the uncertainty. The secondary equipment market provides ongoing opportunities throughout the entire market, especially during periods of economic difficulty, and is extremely well positioned to capitalize on the continued strength of the 200mm market.
Vice President of Marketing and Product Management, Rudolph Technologies, Inc.
Advanced packaging is in the early stages of a dynamic growth phase. Demand for equipment and related tools in the 3DIC and wafer-level packaging area is forecasted to grow from approximately $370 million in 2010 to over $2.5 billion by 2016. Advanced packaging requirements are driving the evolution of back end manufacturing to become more similar to the front end where the need to tie the entire process together with effective process control has long been established.
Ideally, a photolithography solution for advanced packaging begins with a reduction stepper that is uniquely capable of meeting current and future requirements of advanced packaging processes: greater depth of focus to handle the thicker resists required by exaggerated wafer topography; flexible automation and specialized handling for warped wafers, reconstituted wafers, and large panels; on-the-fly focusing at every exposure to ensure maximum image quality; and an on-board reticle library and fast-change reticle wheel for increased productivity.
Solid State Technology | Volume 56 | Issue 1 | January 2013