CoWoSprocess cuts power, boosts performance, shrinks footprint
Jerry Tzou, TSMC, Hsinchu, Taiwan
Converging the IC package and system board into one device package
A new integrated process technology, CoWoS (chip-on-wafer-on-substrate) by TSMC, uses a silicon wafer with through-silicon vias (TSVs) as a carrier to integrate multiple chips in a single device to reduce power, improve system performance, and reduce form factor. The process attaches silicon chips to the TSV'ed wafer through a CoW bonding process and then attaches the subsystem to the substrate to form the final component (Fig. 1).
Figure 1. CoWoS die and finished package.
This architecture enables higher-density interconnects and decreases global interconnect length and associated RC loading, resulting in enhanced performance, reduced power dissipation, and smaller form factor. As high performance applications need greater bandwidth between advanced processors and memory, and become I/O and bandwidth limited, CoWoS integration can effectively address the need by shortening the distance between them, providing the added benefit of reducing power consumption. In addition, convergence of the IC package and system board into a single device package minimizes the number of packages on printed circuit boards (Fig. 2).
Figure 2. Converging the IC package and system board into a single device package minimizes the number of packages on printed circuit boards.
CoWoS also allows designers to partition large die into a few smaller ones or partition subsystems by packaging multiple chips manufactured on different process technologies in one device. For example, a designer may choose an advanced technology for critical parts such as CPUs and use mainstream technology alongside it to optimize cost.
TSMC has successfully qualified CoWoS technology using its first test vehicles and has started shipping risk production CoWoS units to customers. TSMC will build an infrastructure that encompasses DRAM manufacturers, EDA vendors and IP suppliers to facilitate CoWoS access.
TSMC uses DRAM with its CoWoS technology to produce integrated chips featuring lower power consumption, smaller form factor, and higher system bandwidth. These devices will prove ideal for networking equipment, high-performance computing (HPC) applications, smartphones, tablets and Ultrabooks.
TSMC, along with its EDA and IP infrastructure partners, has created multiple CoWoS design solutions through test chip and reference flow collaboration over the past year. Cadence has provided implementation for bump assignment, redistribution layer and interposer routing. CoWoS implementations also use Cadence Wide-I/O Controller IP to enable chip-to-chip connections that increase bandwidth between DRAM and logic.
Several other EDA companies are involved in these efforts. Mentor has supplied multi-die physical verification of DRC, LVS, and extraction. Apache/Ansys can be used for IR-drop and electro migration power integrity analysis, and Sigrity can be employed for substrate extraction.
These tools, along with others in development or evaluation, will be included in TSMC's recently introduced Reference Flow for 3D design. TSMC's integrated CoWoS process provides turnkey, end-to-end manufacturing that includes the front-end process as well as backend assembly and test.
Jerry Tzou is deputy director of the backend business division of TSMC, Hsinchu, Taiwan.
Solid State Technology | Volume 55 | Issue 9 | November 2012