IMAPS 2012: A review


Dr. Phil Garrou, Contributing Editor

The 45th Symposium on Microelectronics (IMAPS 2012) was held September 9-13 in San Diego. Here's a quick review of some of the 3D and advanced packaging papers presented at the meeting.

Gu and co-workers at Qualcomm reported on a memory on logic 3DIC stack consisting of a two-chip-wide IO memory stack bonded to a 28nm logic chip. TSV are 6??m, wafers are thinned to 50??m, TSV connection is to M1 of the 7-layer copper/low-k interconnect stack. The memory stack has 1200 IO on 40??m pitch. The bottom memory die has TSV, the top die does not need them. Thinned die are shipped either on their carrier (the OSAT removes the carrier) or after removal from the carrier on a flex frame.

A negligible shift in electrical parameters is observed after optimizing TSV formation and determining the need for a 5??m keep-out zone (KOZ). No change in bump resistance is seen after 1000 hrs at 150??C and 1000 cycles of temp cycling.

Xilinx has been releasing information on its 2.5D FPGA module for the past two years. In the latest presentation, Banijamail and co-workers examine the reliability of their 2.5D Virtex-7 H580T, which consists of a transceiver chip and two FPGA slices. Interposer TSVs are 10-20??m and 50-100??m deep. FPGA chips are bumped on 30-60??m pitch using Cu pillar bump technology.

Different substrate sizes and designs, lid designs, lid materials, and underfills were examined to minimize warpage and maximize microbump and c4 bump reliability. Control of these variables resulted in packages that met JEDEC warpage spec and minimized BGA fatigue.

With the recent announcements by Xilinx, Altera and others the commercial production of 2.5D products on "high density" interposers is entering the realm of commercial reality. While it is clear that fine featured interposers will come from foundries like TSMC, there have been questions, about "coarse featured" interposers in terms of who will make them and what applications they will be used in.

Shinko and CEA Leti now describe integration and electrical characterization of such a "coarse featured" 3D silicon interposer demonstrator for a SiP application. This demonstrator consists of (4) 10x10mm chips mounted on a 26x26mm Si interposer with 25??m microbumps on 50??m pitch and underfilled. TSV diameter are 10??m and interposer thickness is 100??m for an Aspect Ratio (AR) of 10. We are told that RDL on both sides of the interposer are done with a "semi additive process" although we are not given line width or pitch.

In their paper "Stacking Aspects in the View of Scaling," imec points out that when pitch goes below 40??m, "stacking accuracy is one of the main drivers to ensure yielding devices." It is shown that stacking can be made less sensitive to in plane misalignment by the obvious options of increasing the pad size or decreasing the solder bump size

In a second presentation, "Small pitch microbumping and experimental investigation for underfilling 3D stacks," they report on 3D stacking characterization when using pre-applied underfill (UF).

For 3D stacking, capillary underfilling has clear limits in terms of the gap between die and the bump pitch. This limits high density integration and therefore shifts focus onto pre-applied underfill where the material is dispensed on the landing die before stacking. Pre-applied UF does have concerns such as transparency for alignment marks and UF/filler entrapment between bumps.

imec's studies reveal that both NUF/NCP (define) and WUF (wafer underfill) have commercial products that result in >90% electrical yield after underfilling, although issues such as delamination of WUF films was observed.

Solid State Technology | Volume 55 | Issue 9 | November 2012