Issue



New level of repeatability required for 3D NAND


11/01/2012







Jeff Marks


Jeff Marks, global product group chief technology officer, Lam Research Corp.


Historically, manufacturers have increased memory density by packing more cells together in a single plane. As traditional dimensional shrinks become increasingly difficult, the industry is transitioning from planar to 3D NAND architectures by stacking memory cells onto the same silicon substrate. This approach is made cost efficient by fabricating numerous memory levels simultaneously and using standard semiconductor processes and materials.


In 3D NAND, critical dimensions for deposition and etch processes can be roughly five times larger than those used in planar devices. While this relaxes scaling challenges due to shrinking, it would be misleading to suggest that fabrication is trivial. Making trillions of identical memory cells requires outstanding repeatability on every wafer, wafer to wafer, chamber to chamber, and fab to fab. In addition, 3D NAND stacking introduces an entirely new dimension of process repeatability control???level to level. This new requirement is especially challenging because errors are magnified by the sheer number of levels, and chipmakers are driving more memory levels to increase product value. As a result, the precision requirements for many 3D NAND processes can far exceed those of their planar counterparts.


The magnification of error effect in 3D NAND stacking is evident in several critical steps, and here we consider a vertical channel architecture. In the case of deposition, the gate stack of a 30-level memory device requires depositing 60 repeatable thin film layers at a time, compared with only one to two layers for planar devices. For the plasma-enhanced CVD process, this means that any minor imperfections (e.g., defects or surface roughness) in the first few layers can propagate into subsequent layers, compounding with each added film. Dielectric film stress is also additive and can result in wafer bowing. Film distortion is a concern because every other layer of the 3D NAND stack will become an electrically active part of the device. Furthermore, undulations in the film stack can interfere with pattern transfer, which then makes subsequent process steps more difficult. One solution approach is to optimize the properties of the alternating film layers to neutralize distortion.


Looking at an etch example, the hole etch is critical because it forms the cell channel for all of the levels by "punching" a hole through the stack of alternating film layers in a single pass. Although the aspect ratio for an individual level may only be 1:1, the net aspect ratio of the hole can reach 40:1 in a 30-level device. This is a difficult etch because a nearly perfectly straight profile is required in order to keep the channel size the same at each level. Even a 0.5-degree deviation from vertical can cause the channel dimension at the top level to be ~20% larger than at the bottom. One strategy to minimize this variability is to modify the hardmask properties to enhance etch precision.


Magnification of error concerns also exist for the "stair" etch, which forms the landing pads for each level's contact. This process requires multiple mask trims in a single pass to create features that look like steps of all the same size. Any systematic error in step size is magnified by the number of levels in each pass, shifting the contact placement with each successive step. Considering a 500nm step, only a 5% incremental error would cause the contacts to completely miss the pad after eight levels. The challenge for this process is to etch at high throughput without losing level-to-level precision.


As described, manufacturing 3D NAND devices requires a new level of repeatability driven by a unique compounding effect. Equipment suppliers will need to continue working closely with customers to deliver the precision needed???including optimizing performance from individual processes and leveraging coupled effects between process steps.


Solid State Technology | Volume 55 | Issue 9 | November 2012