Issue



A review of recent advances in electronic devices


10/01/2012







Highlights from recent and upcoming conferences point to a bright future for traditional and emerging electronics, based on silicon, flexible substrates, graphene and nanowires.


The FinFET has grabbed the limelight when it comes to next-generation electronics, and further advances continue to be made, particularly by Intel. At the upcoming International Electron Devices Meeting (IEDM)in December, the company plans to show how they have developed a complete platform for system-on-chip (SoC). But that's just one of the exciting announcements to come from IEDM and other conferences, such as the VLSI Symposium held in June.


Tremendous advancements have been made in building advanced circuits on flexible substrates, for example, which could some day lead to roll-to-roll processing of ICs. To date, flexible circuits have offered limited performance because plastic substrates aren't compatible with the high temperatures and harsh processes needed to make high-performance CMOS devices. At IEDM, for the first time, a way around this will be unveiled. IBM researchers will demonstrate high-performance state-of-the-art CMOS circuits ???including SRAM memory and ring oscillators???on a flexible plastic substrate.


IBM used extremely thin silicon on insulator (ETSOI) devices, with a body thickness of just 60 angstroms. IBM built them on silicon and then used a simple, low-cost room-temperature process called controlled spalling. Then they transferred them to flexible plastic tape.


The devices had gate lengths of <30nm and gate pitch of 100nm. The ring oscillators had a stage delay of just 16ps at 0.9V, believed to be the best reported performance for a flexible circuit.


imec, the Belgium-based consortium, also recently announced that it has integrated an ultra-thin, flexible chip with bendable and stretchable interconnects into a package that adapts dynamically to curving and bending surfaces (Figure 1). The resulting circuitry can be embedded in medical and lifestyle applications where user comfort and unobtrusiveness is key, such as wearable health monitors or smart clothing.





Figure 1. imec has integrated an ultra-thin, flexible chip with bendable and stretchable interconnects into a package that adapts dynamically to curving and bending surfaces.
Figure 1. imec has integrated an ultra-thin, flexible chip with bendable and stretchable interconnects into a package that adapts dynamically to curving and bending surfaces.

New flavors of FinFETS


Multiple-gate transistors, such as the FinFET (or "trigate" transistors as known by Intel) provide superior on/off control, enabling high drive currents to be achieved at a lower supply voltage than otherwise. At IEDM, Intel will discuss how it developed several FinFET "families" of high-speed, low-standby-power and high-voltage-tolerant devices (Figure 2), combined with state-of-the-art interconnects and RF/mixed-signal features for a wide range of SoC applications.





Figure 2. Intel will roll out two versions of its tri-gate transistor, one for logic (top) and the other for high voltage (bottom), all integrated into an SoC. Source: Intel.
Figure 2. Intel will roll out two versions of its tri-gate transistor, one for logic (top) and the other for high voltage (bottom), all integrated into an SoC. Source: Intel.

The high-speed logic transistors have subthreshold leakages ranging from 100nA/??m to 1nA/??m, while the low-power versions feature leakage of < 50pA/??m yet have drive currents 50% higher than 32nm planar (traditional technology) devices. The process also yields high-voltage transistors (1.8V or 3.3V) for analog circuits, I/O, legacy designs and other applications. They feature the highest reported I/O device drive currents for an SoC technology (NMOS/PMOS=0.92/0.8mA/??m at 1.8V). The trigate technology platform also features eight to 11 layers of low-k and ultra-low-k carbon-doped oxide (CDO) interconnect at tight pitches for different applications; many analog/mixed-signal features; and three different SRAM bit cells, spanning high-density/low-leakage (0.092??m2), low voltage (0.108??m2) and high-performance (0.130??m2).


ETSOI


Another exciting development in the transistor world is extremely thin SOI (ETSOI) technology, which is quickly emerging as a viable device architecture for continued CMOS scaling to 22nm and beyond. It offers superior short-channel control and low device variability with undoped channels. At the IEDM, a team led by IBM will report on the world's first high-performance hybrid-channel ETSOI CMOS device (Figure 3). They integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. A novel STI-last process makes the hybrid architecture possible. The researchers built a ring oscillator circuit to benchmark performance, and the hybrid planar devices enabled the fastest ring oscillator ever reported, with a delay of only 11.2ps/stage at 0.7V, even better than FinFETs.





Figure 3. An electron microscope view is shown at the top and an EDX (energy-dispersive X-ray) spectroscopic view below it of a SiGe-channel PFET with 6-nm channel thickness, 22nm gate length, 100-nm contacted gate pitch, high-k/metal gate architecture and ISBD SiGe raised source drain. Source: IBM.
Figure 3. An electron microscope view is shown at the top and an EDX (energy-dispersive X-ray) spectroscopic view below it of a SiGe-channel PFET with 6-nm channel thickness, 22nm gate length, 100-nm contacted gate pitch, high-k/metal gate architecture and ISBD SiGe raised source drain. Source: IBM.

Future memories


While conventional charge-based memory is approaching fundamental scaling limits, several so-called "emerging memories" have migrated from laboratory samples to integrated products. Among various emerging memory technologies, MRAM (magnetoresistive random access memory) has been making impressive progress, ahead of other emerging memories, and has demonstrated the capability to be a successor to DRAM or SRAM. MRAM data is stored via magnetic moments. Parallel or anti-parallel magnetic moments in MRAM stacks present the "0" or "1" state. In earlier generations of MRAM, these states were switched by current-induced magnetic field but that is an obstacle for scaling. The invention of ST (spin-torque) MRAM, which is switched by injecting spin-polarized tunneling current, removes the scaling limitation. At IEDM, in an invited paper, researchers from Everspin Technologies will describe how they built the largest functional ST-MRAM circuit ever built, a 64Mb device with good electrical characteristics. The work shows that MRAM technology is fast approaching commercialization.


Earlier this year, at the VLSI Technology Symposium (Honolulu, Hawaii), imec presented significant improvements in performance and reliability for a type of non-volatile called resistive RAM (RRAM).


RRAM is a promising concept for future non-volatile memories because of its high speed, low energy operation, superior scalability, and compatibility with CMOS technology. Its operation relies on the voltage controlled resistance change of a conductive filament in the dielectric of a Metal/Insulator/Metal (MIM) stack. RRAM systems based on HfO2 have been demonstrated to have excellent scaling capabilities (area <10x10nm) and strong reliability due to efficient voltage-controlled management of oxygen motion in the stack during switching.


Progress in more conventional memory technology also continues, particularly in 3D memories. At IEDM, the first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers. They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction and improves manufacturability. The new architecture also enables the use of a novel "staircase" bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75nm, 64 cells per string and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional sub-20nm 2D NAND, but it can provide 1 Tb of memory if further scaled to 25nm feature sizes. At that size the Macronix device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density.


Graphene, MoS and nanowires


No discussion of emerging electronics would be complete without an update on graphene, and an exciting alternative. Graphene is seen as a potential replacement for silicon in future transistors because it has an exceptional set of properties (high current density, mobility and saturation velocity). However, transistors made of graphene cannot be turned off because graphene has almost no band gap. Researchers have begun to investigate a new 2D material???molybdenum sulfide (MoS)???which has similar characteristics but offers something graphene doesn't: a wide energy bandgap, enabling transistors and circuits to be built from it directly. At IEDM, an MIT-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material's 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter). The transistors demonstrated record MoS mobility (>190cm2/Vs), an ultra-high on/off current ratio of 108, record current density (~20??A/??m) and saturation, and the first GHz RF performance from MoS.





Figure 4a. A computer simulation showing the structure of the optimized ambipolar silicon nanowire device structure, with three 45-nm-long gate regions.
Figure 4a. A computer simulation showing the structure of the optimized ambipolar silicon nanowire device structure, with three 45-nm-long gate regions.




Figure 4b. This image is a tilted SEM (scanning electron microscope) view of the nanowire stacks after deposition and etching of the polarity gate structures.
Figure 4b. This image is a tilted SEM (scanning electron microscope) view of the nanowire stacks after deposition and etching of the polarity gate structures.

Another important development to be unveiled at IEDM: The phenomenon of ambipolar conduction (the ability to switch between N- or P-type), which has been observed in some nanoscale transistors made from silicon, carbon and graphene. A team led by researchers from the Swiss Federal Institute of Technology in Lausanne (EPFL) built gate-all-around ambipolar Si nanowire FETs in a vertically stacked configuration on an SOI substrate (Figure 4). A "polarity gate" attached to the ends of the nanowires is used to switch their polarity dynamically between the N and P states, while a control gate in the middle turns them on or off. The devices showed an excellent on/off current ratio of 106 and subthreshold slope of 70mV/dec. The researchers built a logic gate to show the technique's usefulness for future logic design.


Solid State Technology | Volume 55 | Issue 8 | October | 2012