Progress in 3DIC SEMI standards


Dr. Phil Garrou

The Inspection and Metrology Task Force of the SEMI 3D standards group, recently approved its first Standard,SEMI 3D1, Terminology for Through Silicon Via Geometrical Metrology.

SEMI 3D1 will provide a starting point for standardization of geometrical metrology for selected dimensions of through silicon vias (TSVs). Although different technologies can measure various geometrical parameters of an individual TSV, or of an array of TSVs, such as pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area, and bottom diameter, it is currently difficult to compare results from the various measurement technologies as parameters are often described by similar names, but actually represent different aspects of the TSV geometry.

Other standards under development by the Inspection and Metrology Task Force include SEMI Draft Document 5270, Guide for Measuring Voids in Bonded Wafer Stacks, SEMI Draft Document 5409, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks, SEMI Draft Document 5410, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures, and SEMI Draft Document 5447, Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures.

The Thin Wafer Handling Task Force is focused defining thin wafer handling requirements including physical interfaces used in 3D-IC manufacturing. Current standards for shipping are not well-suited for the reliable storage and transportation of thin wafers and dice on tape frames used in 3D-IC manufacturing. Wafer thicknesses of 30-200??m will need significant changes to the current design criteria of current wafer transport and storage containers. SEMI Draft Document 5175 aims to address the robust handling and shipping of thin wafers, including changes in securing the wafers.

The Bonded Wafer Stacks Task Force is near completion of its SEMI Draft Document 5173, Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack and SEMI Draft Document 5174, Specification for Identification and Marking for Bonded Wafer Stacks.

Current wafer standards do not adequately address the needs of wafers used in three-dimensional bonded wafer stacks for stacked integrated circuits. In each step of a 3D-IC process, the incoming material must be specified in terms of wafer dimension and materials present. Wafer thickness, edge bevel, notch, mass, bow/warp and diameters change when wafer stacks are bonded, debonded, and when wafers incorporated into stacks are thinned. Further, these parameters will change for a single wafer stack during process. This Document will provide the required properties of both silicon ("device") wafers and glass ("carrier") wafers to be used in 3D-IC applications. Templates for describing bonded wafer stacks and processed wafers to be used in the bonding flow would be provided as well.

The Middle-End Task Force is focused on the middle-end processes on wafers with or without TSVs, including post-final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line formation and carrier de-bond. The task force's first two proposals are SEMI Draft Document 5473, Guide for Alignment Mark for 3DS-IC Process, and SEMI Draft Document 5474, Guide for CMP and Micro-bump Processes for Frontside TSV Integration. The group that developed SEMI 3D1 continues to develop standards to be used in measuring the properties of TSVs, bonded wafer stacks and dies.

Solid State Technology | Volume 55 | Issue 8 | October | 2012