BCDMOS designed for 700V driver chips
JAE SONG, Dongbu HiTek, Seoul Korea
A specialized ultra high voltage BCDMOS process at the 0.35??m node deploys thin n-epitaxial technology to support high voltage applications.
BCDMOS today ranks as a preferred process for implementing system-on-chip solutions, thanks to its capabilities to integrate Bipolar (analog), CMOS (logic) and DMOS (power) functions on a single chip. Within the past few years, the rapidly growing demand for monolithic smart power ICs has greatly accelerated the evolution of BCDMOS process technologies to support ultra high voltage applications.
Specialty semiconductor foundries have taken leadership roles in expanding the capabilities of BCDMOS to better implement ultra high voltage chip solutions. One of the most promising developments centers on optimizing DR-LDMOS (Double RESURF LDMOS) transistors by using thin n-epi technology and introducing a P-TOP layer to reduce on-resistance while maintaining high breakdown voltage.
Two types of DR-LDMOS structures have been optimized using thin n-epi technology. One is for a switching transistor to increase on-breakdown voltage, and the other is for a level shifter between low and high side regions. Let us now take a closer look at these two types to better understand how their structures take BCDMOS process technology to a new level in supporting ultra high-voltage industrial applications.
DR-LDMOS for level shifting
Fig. 1 illustrates an actual DR-LDMOS top view (with circular shape) along with a cross section of a 700V DR-LDMOS structure that forms a level shifter on the high side of the gate driver IC. Significantly, the high on-breakdown voltage transfers a low voltage logic signal to a high voltage control part. Resistance is applied to the vertical JFET between P-BODY and P-TOP in DR-LDMOS to improve on-breakdown voltage as shown in Fig. 1b.
FIGURE 1. Actual DR-LDMOS top view (a) and cross section of 700V DR-LDMOS (b) for level shifter.
Fig. 2 shows the variations of breakdown voltage and on-resistance with the variation of P-TOP distance from the P-BODY edge. As the P-TOP length (X1) decreases towards P-BODY edge, the on-resistance is increased due to the reduced conductivity caused by increases in JFET resistance. The breakdown voltage increases with the decrease of X1 due to maintaining an optimal charge balance between n-epi and P-TOP for Double RESURF.
FIGURE 2. Breakdown voltage (a) and on-resistance (b) with variation of P-TOP distance from P-BODY edge.
If the X1 is increased more than 0.4 (X1/X2), the breakdown voltage drops drastically from its plateau voltage due to the high surface electric field under the gate electrode. As a result of optimizing JFET resistance for DR-LDMOS, an on-breakdown exceeding 700V is achievable at the optimal condition (X1/X2=0.4) and the off-breakdown voltage exceeds 900V as shown in Fig. 3.
FIGURE 3. DR-LDMOS I-V characteristics for level shifter (a) and breakdown voltage (b).
DR-LDMOS for switching
Fig. 4 shows a cross section and layout schematic of DR-LDMOS transistor with multi fingers for switching applications. This device is applied to a Double RESURF structure with an additional PTOP layer inside and an extended n-type drift region (n-epi) to reduce on-resistance.
FIGURE 4. Layout schematic and vertical structure of the LDMOS for switching applications. Actual DR-LDMOS top view (a); general LDMOS layout (b); cross section of source corner region a-a??? (c); cross section of stripe region b-b??? (d).
The DR-LDMOS consists of the regions shown in Fig 4. Stripe region (B) and drain corner region (C) maintain high breakdown voltage due to optimal charge balance between n-epi and P-TOP layer. However, source corner region (A) breakdown voltage is decreased dramatically due to the high surface electric field under the gate electrode caused by a broken charge balance between n-epi and P-TOP. To overcome this problem, the DR-LDMOS deploys an HVPWELL layer with rainbow shape at the source corner region as shown in Fig. 4c.
As the distance X3 between HVPWELL decreases, the breakdown voltage increases due to the reduction of the high surface electric field under the gate caused by a decrease of n-type charge regarding dilution of n-epi concentration. As shown in Fig. 5, the optimal distance (X4/X3) is between 0.7 and 0.9, and the breakdown voltage is over 750V at the NEPI1 condition.
FIGURE 5. Breakdown voltage with the variation of distance between HVPWELL (a) and measured I-V with optimal condition (X4/X3=0.8) of NEPI 1.
Two types of robust 700V DR-LDMOS transistors using thin epitaxial technology have been developed for level shifting and switching applications. The P-TOP layer is introduced to reduce on-resistance while maintaining high breakdown voltage for a switching transistor, while also increasing on-breakdown voltage for level shifting between low and high side regions. By optimizing JFET resistance of DR-LDMOS for level shifting, the on-breakdown can exceed 700V at the optimal condition (X1/X2=0.4) and off-breakdown voltage can exceed 900V. For switching applications, an HVPWELL layer of rainbow shape is deployed at the source corner region to reduce n-type charge of the n-epi region and achieve a breakdown voltage that exceeds 750V.
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4. Nam-Chil Moon, Bon-Keun Jun, Kyoung-Wook Kwon, et al, ???Design Optimization of two kinds of robust 700V DR-LDMOS using a thin epitaxial layer,??? PCIM presentation (Nuremburg, Germany)May 8, 2012
JAE SONG is executive vice president of marketing at Dongbu HiTek, Seoul Korea.
Solid State Technology, Volume 55, Issue 7, September 2012