Issue



The energy behind energy at SEMICON West


09/01/2012







At SEMICON West, keynoter Shekhar Y. Borkar, Intel Fellow and director of extreme-scale technologies at Intel, focused on the energy demands of ubiquitous computing, and how technologies developed for super computers will later be adopted into smartphones. The energy demands of today???s transistors, Borkar says, will not be sustainable at the exaflop data rate. At CEA-Leti???s presentations later that day, researchers agreed. So how can we achieve a new power consumption paradigm?


Different transistor-level technologies can address reducing power consumption. Borkar shared Intel???s 22nm 3D trigate transistor and voltage scaling at the circuit level. Intel???s trigate design reduces the required supply voltage and can be tuned for different thresholds. Intel has developed an experimental processor to demonstrate this work.


Borkar discussed the use of SoC for targeted efficiency and flexibility ??? using single-purpose blocks that are energy efficient along with the flexible blocks, such as microprocessor, to make a chip accommodate various operations. Borkar calls this ???valued performance.???


Other energy-saving options include stacking DRAM memory with a logic buffer to direct access to a specific page -- see the Hybrid Memory Cube -- and co-optimized circuits and interconnects.


At CEA-Leti???s research meeting, Hughes Metras, VP of strategic partnerships in North America, also projected that the next step in super computing, exascale, would be insupportably energy intensive. Leti proposes planar FDSOI transistors, silicon photonics for light-based data communication, and 3D for lower-loss and shorter interconnects.


Maud Vinet, Leti assignee at IBM, focused on planar FDSOI transistors. We already have the majority of the wafer processing technologies we need for planar FDSOI in bulk CMOS. The biggest change is extremely thin Si films, adding importance to Si loss. The smaller gate lengths of planar FDSOI prevent parasitics, for faster operation. Back bias allows the device???s threshold voltage to be tuned, a concept discussed during Intel???s keynote as well. Planar FDSOI offers 30% less power dissipation than bulk transistors. ???M.C


Solid State Technology, Volume 55, Issue 7, September 2012