Issue



Atomic layer deposition for metal gate integration


07/05/2012







MOHITH VERGHESE, ASM America, Phoenix, AZ.


High-k based transistors have introduced the semiconductor industry to increasingly complex metal gate integration schemes and novel, low temperature deposition techniques such as ALD.


As high-k/metal gate (HKMG) technology becomes mainstream for high performance and low standby power logic devices, it is useful to review the rapid evolution of integration schemes that has made this new process architecture possible. The introduction of high-k as the gate dielectric of the transistor was one of the most significant of recent process integration changes in the semiconductor industry. Replacement of traditional silicon oxide (SiO2) and silicon oxy-nitride (SiON) dielectric layers was difficult in itself, but it was quickly discovered that metal gate integration was the single most challenging aspect of proliferating HKMG technology in production. Whereas past technology nodes utilized highly doped polysilicon gate electrodes for NMOS and PMOS devices, the use of high-k gate dielectrics necessitated a shift to metal gate electrodes. High-k materials like hafnium oxide (HfO2) were found to interact negatively with polysilicon, causing a variety of issues such as high threshold voltages (VT) and increased equivalent oxide thickness (EOT)[1]. Metal gates, on the other hand, integrate well with the new metal oxide dielectrics, but can also come with a host of issues. Integration concerns such as film stability, compatibility with existing production flows, and contamination in manufacturing fabs have to be taken into account. However, the single most important factor in choosing the appropriate metal gate is effective work function control. The effective work function of the metal gate dictates the ultimate threshold voltage of the device which in turn allows lower power operation and higher clock speeds.





Figure 1. Work Function Requirements for CMOS Devices



Transistor work functions


NMOS and PMOS transistors have different effective work function requirements to align appropriately with the respective Fermi levels in the underlying silicon (Fig. 1). To enable low VT operation, band edge effective work functions are highly desirable (<4.1 eV for NMOS, >4.9 eV for PMOS) [2]. Metals have inherent theoretical work functions associated with them and it is possible to identify metal films which exhibit the required nominal values. However, effective work function is highly dependent on the interaction at the metal-dielectric interface and hence it is sensitive to metal thickness, deposition techniques, film composition/contamination and thermal budget. In fact, the same metal can exhibit a wide range of effective work functions after complete device integration. One verity is the drift of the effective work function of most metals towards mid-gap (~4.5 eV) upon exposure to thermal anneals (Fig. 2) [3]. Furthermore, only a few metals exhibit the required thermal stability to survive the lengthy device manufacturing flow. The industry quickly converged on titanium nitride (TiN) as the most effective metal gate for HfO2 based gate dielectrics. Novel low temperature deposition techniques like atomic layer deposition (ALD) are able to isolate a largely p-type version of TiN. However, thermal budget is still a concern and in traditional, gate first process flows, the TiN effective work function is driven to mid-gap after the high temperature, dopant activation anneals [4]. Some integrated device manufacturers (IDMs) have used innovative approaches to continue the use of gate first process flows along with a single mid-gap TiN based metal layer by the use of capping dielectric layers to modify the final effective work function of the device and maintain low VT operation [5].





Figure 2. Effect of Thermal Budget on Metal Work Function



Replacement gate processes


In recent years, some IDMs have transitioned to replacement gate (RPG) process flows where the formation of the high-k/metal gate stacks are performed after completion of all high temperature process steps such as dopant activation anneals. This enables a work-around the work function drift problems present in gate first integration and exploits the metals gate's native work function in the transistor [6]. While the result is a more complex integration scheme, the RPG flow gives unparalleled control of metal effective work functions. However, RPG flows also introduce more three dimensional challenges for deposition techniques. Removal of the dummy poly gate after spacer formation results in an opening that must be filled conformally with high-k and metal gate films with precise thickness control (Fig. 3). Because of its inherent conformality, ALD is a must for some of the critical steps of the formation of the metal gate stack for optimal control within the die and across the entire wafer. NMOS work function has been the most elusive as most pure metals with low work functions (e.g. Al, Ti, Ta) are both unstable on high-k (resulting in metal migration and high leakage currents)[7] and difficult to deposit conformally at a low temperature by thermal ALD [8]. Hence, early versions of RPG technology used combinations of ALD, physical vapor deposition (PVD) and chemical vapor deposition (CVD) for metal gate formation.





Figure 3. Planar Replacement Gate Device Structure



As shown in Fig. 3, the novel RPG NMOS metal stack that has become standard in the industry uses a thin TiN layer and Ti/Al mixtures to set the correct effective work function [9]. Although the thin TiN layer alone is not enough to set the appropriate band edge work function, controlled diffusion of Al from the layer above allows for a work function shift towards the conduction band without degrading gate leakage significantly [10]. The PMOS transistor utilizes a thin TaN barrier along with a thicker TiN layer above it to prevent movement of Al close to the metal/high-k interface. This TiN-TaN-TiN stack is also responsible for setting a high, p-type effective work function for the PMOS transistor [11]. The final step is an Al contact fill for both NMOS and PMOS transistors. The difficulty in effectively controlling this complex RPG flow for planar devices is compounded as gate length scales. Tighter gate pitches result in higher aspect ratios and reduced real estate for the multiple metal layers required. Conformal fills of the required pure metals are also extremely challenging and variations in thickness of the thin TiN and TaN layers results in difficulty in controlling the VT across multiple dies on the wafer and across different transistor channel lengths. Device reliability also becomes significantly challenging in highly scaled RPG devices.


Scaling the planar transistor to gate lengths below 22nm has required high doping of the channel and source/drain regions to control short channel effects. As a result, random doping fluctuation is now a leading VT variability issue [12]. A fully depleted device allows for a lighter channel doping or the complete elimination of doping in order to obtain better VT variability control. As a result, a transition to three dimensional, FinFET type devices is underway for the most advanced logic nodes. Furthermore, FinFETs can relax EOT/ Lgate scaling requirements as drive current enhancements can be achieved through better electrostatic control [13]. FinFETs also relax effective work function requirements for metal gates (typically by approximately 100-200 mV) due to the undoped nature of the fully depleted fins [14]. However, a work function span is still required and RPG process flows remain the best path to achieve appropriate NMOS and PMOS targets.





Figure 4. FinFET Replacement Gate Device Structure



The three dimensional channel region poses a larger issue for NMOS devices. While ALD TiN alone can achieve PMOS metal gate targets, PVD layers are no longer an option for setting NMOS work function. A non-conformal Ti/Al layer would result in variations in VT both around the fin and between transistors. PVD films can neither conformally cover the fin nor is there enough space to pursue the complex multi-layer solution that was implemented for RPG planar devices (Fig. 4). As a result a low temperature, ALD, n-type work function material is a requisite for successful NMOS FinFET devices. This requirement has to be coupled with the previously discussed prerequisites of thermal stability and metal migration control. Ideally, the metal gate would be able to set the appropriate work function at the thinnest possible physical thickness to allow for denser packing of the fins and the transistors and for better scalability to future nodes. Furthermore, the work function metal should be compatible with the contact metal material so that valuable real estate between transistors is not used up by electrically inadequate barrier layers.


Conclusion


High-k based transistors have introduced the semiconductor industry to increasingly complex metal gate integration schemes and novel, low temperature deposition techniques such as ALD. Although these techniques are already immensely leveraged for RPG planar devices, the additional requirements for three dimensional FinFET device structures will further propel ALD into new spaces. The industry will inevitably see less of a reliance on traditional CVD and PVD metal films and an intense focus on ALD equivalents or replacements. Metal ALD has clearly become an enabling technology for gate stack integration in front end of line (FEOL) with expansion possibilities into middle end of the line (MEOL) and back end of the line (BEOL) applications.


References



  1. C. Hobbs, et al., VLSI Tech Digest, (2003), p. 9-10

  2. I. De, D. Johri, A. Srivastava, and C.M. Osborn, Solid-State Electron, 44 (2000), p. 1077

  3. H. Y. Yu et al., IEEE Electron Device Letters, (2004), 25, p. 337

  4. Westlinder, J. et al., IEEE Electron Device Letters, (2003), 24, 9, p. 550-552

  5. S. Guha, et al., Applied Physics Letters, (2007), 90, 9, p. 092902-092902-3

  6. F. Arnaud et al., IEDM Tech. Dig., (2008), pp. 633-636,

  7. V. Misra, G. Lucovsky, G. Parsons, MRS Bulletin, (2002), p. 212-216

  8. B.S. Lim et al., Nature Materials 2, 749 - 754 (2003)

  9. Intel Xeon E5410 Microprocessor, Intel 45nm High-K + Metal Gate CMOS Process, Chipworks

  10. X. R. Wang, et al., Microelectronic Engineering, (2011), 88, 5, p. 573-577

  11. S. H. Bae, et al., VLSI Technology, (2004) p. 188-189

  12. S. Borkar, IEEE Micro, (2005), 25, 6, p.10-16

  13. B. Doyle, et al., VLSI Technology Digest of Technical Papers, (2006), p. 50-51

  14. W. Haensch, et. al., IBM J. Res. & Dev., 50, No. 4/5 (2006)


MOHITH VERGHESE is the senior technical product manager at ASM America, Phoenix, AZ where he is responsible for ALD and Epi technologies. Ph: 1-602-470-2736, email:  mohith.verghese@asm.com.


Solid State Technology, Volume 55, Issue 6, July 2012


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