Issue



Impact of charge during gate oxide patterning on yield


07/05/2012







JUNGTAE PARK, Samsung Electronics Co.; SUNGJIN CHO and JEFF HAWTHORNE, Qcept Technologies Inc.


Detection of non-visual defects in the steps prior to optical inspection was used to trace the cause of a silicon pitting defect.


Achieving high yields in a leading-edge semiconductor manufacturing facility requires a dedicated effort to identify and eliminate the causes of defects that result in yield loss. Process measurement and inspection tools play a critical role in this effort by quantifying process variability and identifying the root cause of specific types of defects. A wide range of optical inspection tools have been developed to detect physical defects such as pits, particles and scratches. However, up to 30% of yield loss in today's fabs is not traceable to physical defects. Many of these yield issues are caused by Non Visual Defects (NVDs). NVDs are defects that are not detectable by optical inspection, and include sub-monolayer residues, contamination, and process induced charging of dielectric films [1-3].


In this paper we discuss the detection and investigation of a silicon pitting defect. This physical defect was detected using standard optical inspection after an oxide wet etch operation, and resulted in yield loss at the end of line. Initial yield engineering efforts focused on varying the process conditions for the steps prior to inspection. This failed to eliminate the defect and was not successful in identifying the root cause of the pitting. Subsequent efforts focused on the detection of NVDs in the steps prior to inspection. This approach was successful in identifying the root cause, which enabled the optimization of the process and a significant reduction in the overall defect rate, leading to higher end-of-line yield.





Figure 1. Process flow prior to detection of the silicon pitting defect at After Clean Inspection (ACI).



Figure 1 shows the process flow prior to the point at which the pitting defect was detected. A wafer with a thermal oxide film is coated with photoresist. The resist is then patterned using lithography. This creates openings in the photoresist where the oxide film will be removed by the wet etch process. An optical inspection is performed after lithography (Post Litho) and prior to the etch operation. A wet etch of the oxide film is then performed in a low ammonium fluoride liquid (LAL), after which the photoresist is removed and the wafer cleaned. Finally, an optical After Clean Inspection (ACI) of the etched wafer is performed.





Figure 2. A defect map from a brightfield optical inspection tool used for ACI, and the SEM review image of one of the pit defects.



Figure 2 shows a defect map from a brightfield optical inspection tool used at ACI. A large number of physical defects were detected, primarily near the left edge of the wafer. Scanning Electron Microscope (SEM) review was used to classify the defects as pits in the silicon surface. The image on the right of Fig. 2 is a SEM image of one of these pits.


The pitting defect was detected at ACI on 100% of the production wafers, and the defect maps showed strong correlation to end of line yield. The defect was not isolated to a single tool or set of tools, suggesting that the defect was induced by the process. The initial assumption was that the defect occurred at the LAL oxide etch or the resist strip and wet clean operation. Experiments were run to vary the process conditions at these steps, but these variations had no effect on the number of defects. It was then decided to look at NVDs as a possible cause of the defect.





Figure 3. ChemetriQ inspection was inserted into three points in the process flow for detection of possible NVDs. NVD charge results identified the inspection point inserted prior to Post Litho Inspection as the source of the process induced charge (show in green).



The ChemetriQ?? inspection system from Qcept Technologies was used to inspect wafers at different points in the oxide etch process. This system uses a scanning surface potential difference imaging technique to generate fast, full wafer images of variations in the surface potential of a wafer [1]. Surface potential variations can be caused by several different types of non-uniformities such as sub-monolayer concentrations of contamination, including organics and metallic, and by charge trapped on or in dielectric films.





Figure 4. ChemetriQ charge map showing process-induced charge Post Litho.



The first study inserted ChemetriQ inspections at the same points in the process as Post Litho Inspection and ACI (Fig. 3). No residues or charge were detected at ACI, but at Post Litho charge patterns were detected on the product wafers. Specifically, high positive charge, resulting in peak surface potential values ranging from +4 to +9 Volts, was detected primarily on the left side of the wafer in the region of the pitting defect as shown in Fig. 4.


At this point, it was clear that the wafers were charged at Post Litho. An additional ChemetriQ inspection step was inserted after resist coat to better determine the source of the charge, as shown in Fig. 3. Figure 5 shows ChemetriQ charge maps before and after lithography. Charge induced potentials after resist coat are near 0 Volts. However, after lithography the surface potential increases to greater than 4 Volts. This clearly shows that the source of the charge was the lithography step (expose and develop).





Figure 5. ChemetriQ charge maps of product wafers after resist coat and after lithography. Charge induced potentials after resist coat are near 0 Volts. Charge levels are much higher after the lithography process, where charge induced potential is greater than 4 Volts.



ChemetriQ inspection was implemented at Post Litho to monitor charge levels on production wafers. Peak charge levels were calculated on a per-die basis, thresholded, and exported to yield management software via KLARF files. The peak charge levels were well correlated with pitting defects detected at brightfield inspection (Fig. 6).





Figure 6. High positive charge levels were thresholded and correlated with pitting detected by brightfield optical inspection.



Additional experiments were run in an attempt to modify the lithography process to reduce charging and, potentially, the number of pitting defects. It was found that by altering the lithography rinse process, peak surface potential values could be reduced to +3 to +5 Volts. In addition to reducing the overall charge levels, the optimized lithography process also reduced the number of wafers that had pitting defects from 100% to less than 20%, and fewer die were affected per wafer.


The success in reducing pitting defects by reducing surface charge provides strong evidence that charge on the photoresist prior to oxide etch was a direct cause of the pitting. This raises the question of how positive charge on an oxide film can lead to silicon pitting during etch. It is well known that hydrofluoric acid can electrochemically etch silicon if the wafer is anodized [4,5]. However, in this case no potential was applied to the wafer. Positive charge on the photoresist would have the effect of attracting electrons and repelling holes at the surface of the silicon, depleting p-type silicon of holes and eventually attracting enough electrons to invert the surface. This charge-induced biasing of the surface could be an important factor in accelerated etch of the silicon near the charged film, but additional work is required to understand the precise mechanism leading to pits.


In some cases, NVDs affect yield without creating a corresponding physical defect. For example, sub-monolayer metallic contamination can affect material properties resulting in yield loss. In other cases, NVDs can lead directly to physical defects through known mechanisms such as electrostatic discharge [3]. The pitting defect described here provides an interesting example where an NVD at one step in the process unexpectedly causes a physical defect at a later step in the process, which is then detected by an optical inspection tool. In this case the NVD, which is process induced charge, is a precursor to a physical defect, which is silicon pitting. This suggests that other physical defects might have precursor NVDs, such as charge or contamination, and that the detection of NVDs could provide useful insight into the cause of physical defects that are detected at later inspection steps.


Acknowledgement


This article is based on an oral presentation given at the 2012 SEMATECH Surface Preparation and Cleaning Conference.


References


1. K. H??ppner, et al; Advanced Semiconductor Manufacturing Conference; Novel In-Line Inspection Method for Non-Visual Defects and Charging, (2009)


2. S. Raghavan, et al; Semiconductor International Webcast; Key Cleaning Challenges in High-Density Flash Manufacturing, (2007)


3. J. Hallady, et al; Sematech Surface Preparation and Cleans Conference; Elimination of ESD Defects using DICO2, (2008)


4. Slimani, A. et al. (2009). Experimental study of macropore formation in p-type silicon in a fluoride solution and the transition between macropore formation and electropolishing, Electrochimica Acta, 54, 3139-3144.


5. V. Lehman, S. Ronnebeck, (1999). The Physics of Macropore Formation in Low-Doped p-Type Silicon, Journal of the Electrochemical Society, 146 (8) 2968-2975.


Also read: Non-visual defect inspection for comprehensive yield management


JUNGTAE PARK is senior engineer of defect analysis department at Samsung Electronics Co., LTD, Gyeonggi-Do, Korea. Tel: 82-031-209-0455, email: jtpark@samsung.com. SUNGJIN CHO is senior process technologist, application and development department at Qcept Technologies, 47354 Fremont Blvd, Fremont, CA. Tel: 510-933-1120, email: Jason.cho@qceptech.com. JEFF HAWTHORNE is vice president of advanced development at Qcept Technologies, 75 Fifth Street NW, Atlanta, GA. Tel: 404-526-6073, email: jeff.hawthorne@qceptech.com.


Solid State Technology, Volume 55, Issue 6, July 2012


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