From The ConFab: State of advanced packaging technologies


As packaging has played a larger and larger role in chip performance, form factor, and capabilities, Solid State Technology's The ConFab has increased its focus on back-end processes. Cue "Advanced Packaging and Progress in 3D Integration," a session chaired by Abe Yee, Nvidia, and featuring David McCann, senior director of technical business operations, GLOBALFOUNDRIES; Sandeep Bharathi, VP of engineering, Xilinx; Ron Huemoeller, SVP of advanced interconnect platform development, Amkor, and William Chen, VP, Advanced Semiconductor Engineering Incorporated (ASE).

2.5D and 3D packaging are coming together to enable the end-goal of silicon devices ??? high density, low power, low cost, high yield, small form factor heterogeneous silicon blocks integrated on one package, feeding a seemingly insatiable demand for video, Internet, etc. Society is shifting to "ambient intelligence," Chen said.

McCann pointed out the interconnection density increase enabled by advanced packaging, whether it be 2D like flip chip bumps (10k I/Os per IC) or 3D like TSV (50k I/Os). Stacking silicon interconnects enables lower latency and power consumption in higher density than traditional I/Os, said Bharathi, creating 100X the die-to-die connectivity bandwidth per watt versus high-speed serial or standard parallel I/O.

Bharathi explained Crossover SoCs ??? devices that combine multiple functions on a single device with heterogeneous die. With active die stacked atop active die in a 3DIC, Crossover SoCs raise thermal and mechanical challenges. Bharathi looked at a case study of stacked silicon interconnects in FPGAs at Xilinx, FPGA building block "tiles" organized in columns then combined to create an FPGA. The device combines a 28nm active die and 65nm passive interposer, with low-risk microbumps and TSVs; the silicon interposer reduces stress with low-k materials.

Huemoeller zeroed in on TSVs, which can take monolithic die to die slices, or be used to segment monolithic analog/logic/cache functions onto separate die. Stacking die frees up process node choices. Wafer yield goes up, and costs go down, with no form factor sacrafice. Quoting Samsung, Huemoeller said that TSVs interconnecting stacked die offer 8X better bandwidth and 50% power savings compared to PoP.

Advanced packages call for new materials and assembly and test methods. McCann pointed out that transistors and packaging are not 2 isolated silos. Copper-filled TSV interconnects add stress to the silicon. Thinning on transistors also must be characterized for potential impacts. The wafer processing steps are complicated for advanced packaging, and KGD testing is still developing, Bharathi added.

Expect >80% CAGR for 2.5D interposers through 2015 (300mm equivalent). 2.5D interposers can be made from laminate, glass, or silicon, each with pros and cons. Laminates are limited to larger line/space pitch than package designs will require. Glass vias can be very expensive. Silicon interposer production is one option for idle legacy foundry lines, said Huemoeller.

Chen points out that, over time, various advanced packaging methods, such as WLP, die stacking, and interposer interconnects, are converging. Parallel trends are emerging that use silicon interposers and 3D packaging with heterogeneous integration. Heterogeneous integration puts MEMS devices, memory, logic processors, and RF devices all on one substrate, in a small form factor.

Read a discussion of the packaging supply chain with these ConFab speakers at

Solid State Technology, Volume 55, Issue 6, July 2012

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