Thin die stacking for wide I/O memory-on-logic



Wide I/O DRAM is pushing thin wafer processing into high-volume manufacturing readiness.

Wide I/O interface memory-on-logic has the potential to be the long awaited killer application that will boost through silicon vias (TSVs) and 3D integration into high-volume manufacturing. Information transfer is rapidly transforming from text based communication to picture and video-based communication, which creates an insatiable demand for bandwidth. The convergence of smart phone and media server requires DRAM bandwidth >12GB/s in order to allow streaming of 1080p HD videos onto large displays. Conventional memory-logic interfaces ("narrow I/O interface") consume too much power at the input/outputs (I/Os) and do not allow scaling to multiple hundreds or thousands of I/Os. TSVs enable a significant power reduction at the I/O. Current DDR3 technology consumes 40mW per pin, whereas I/Os based on TSVs only consume 24??W per pin [1]. This power reduction by 1000x gives chip designers the freedom to implement 512 I/Os with the next device generation.

Wide I/O memory-on-logic is one of the most challenging 3D applications for various reasons:

??? Form factor is crucial since mobile applications are the primary drivers.

??? The individual memory layers require a thickness of 50??m or less.

??? For memory, bandwidth and power consumption are not the only important factors; total data storage capacity is at least equally important.

Figure 1. ZoneBOND??? carrier schematics and close-up

TSV integration

For these reasons, multiple memory dies have to be stacked. Initial designs require 4 layers, but 8+ layer stacks will follow very rapidly. In terms of chip stacking with TSVs, wide I/O DRAM will initially require stacking of 4 ultra-thin memory dies plus 1 logic controller. Companies have already successfully implemented manufacturing of memory-on-logic, as evidenced by recent wide I/O DRAM shipments. The key to success was a paradigm shift in TSV manufacturing. In the past, a "one solution fits all" approach had been envisioned by the industry, where an identical TSV manufacturing process would support power devices, image sensors, stacked memory and GPU-on-CPUs. For wide I/O memory-on-logic, however, specialized TSV manufacturing processes are required.

Reliable 3D integration schemes have now been developed, following system engineering principles where all aspects of the device manufacturing are considered simultaneously. In the past, engineers tried to use identical processes-of-record for frontside and backside RDL processes, leaving many integration issues to be addressed during TSV manufacturing. However, it turns out that co-engineering backside RDL and TSV manufacturing is the easier road to success. There are now multiple integration schemes for memory-on-logic.

Cost is, of course, another important factor beyond bandwidth, power and total storage capacity. The cost of TSV manufacturing correlates with the depth and the aspect ratio of the via. The cycle times for the process steps for via etching and via filling correlate with via depth and aspect ratio. For memory, silicon real estate comes at a premium so the TSV area consumption has to be minimized. The only way to minimize the TSV diameter and to keep the aspect ratio low is by reducing the TSV depth. Memory stacking with TSVs inevitably leads to the requirement to process ultra-thin wafers on front- and backside.

Thin wafer processing

Co-engineering of backside RDL, TSV and die stacking processes has changed the primary requirements for thin wafer processing. Temporarily bonding the device wafer to a carrier wafer enables wafer thinning and backside processing [2]. After backside processing, the thin device wafer is separated from the carrier. One key requirement is that this thin wafer is stackable, meaning that a) the wafer has to be particle and residue free and b) the thin wafer surface chemistry and physics has to be compatible with bonding and especially underfill processes. As memory-on-logic devices have at least 5 (without interposer) or 6 die levels (with interposer) both sides of the thin wafer have to be particle and residue free. Thermoplastic adhesives have the advantage that they allow single-wafer cleaning after debonding and that there is no modification of the device wafer passivation.

Stacking of memory sub-stack to logic controller is usually performed by chip-to-chip (C2C) or chip-to-wafer (C2W) stacking as memory die and logic die do not necessarily have the same size. Stacking of the memory dies (i.e., the assembly of the memory "sub-stack") can be performed as C2C, C2W and also wafer-to-wafer (W2W). Stacking of memory is well suited for W2W as all the dies have the same size, the volume is high and the yield is high.

Stacking of thin wafers can be performed either after the thin wafer is debonded or while the thin wafer is still bonded onto a carrier wafer. Bonding of the thin wafer while still mounted to the carrier wafer allows comfortable and safe wafer handling, but adds some complexity to the wafer bonding process. For ultra-thin wafers, stacking before debonding might be necessary. For C2W this means dicing while the die is still on the carrier, which destroys the carrier and adds to the overall costs. W2W allows re-using the carrier wafer.

Figure 2. ZoneBOND??? debonding is a 2-step process: during the release step the adhesive edge zone is dissolved; the thin device wafer is separated from the carrier during the debond step.

Cu-Cu bonding is the most promising process for memory stacking. Current activities are targeting a reduction of the bond temperature in order to reduce cycle time and cost of ownership, but also in order to facilitate permanent Cu-Cu bonding prior to debonding from the carrier.

Stacking of dies is typically performed by the OSAT whereas thin wafer processing is performed by the foundry. In either case, it is necessary to ship the thin wafers. Shipping of thin wafers on a film frame is quite well established, but nevertheless shipping of ultra-thin wafers with less than 50??m thickness results in small yield hits. As the wafers are very valuable at this point of the manufacturing processes (after complete front- and backside processing) the cost of yield is non-negligible.

The alternative approach is to ship the thin wafers while still securely bonded to the carrier and debond directly at the assembly site. This requires an innovative supply chain where the foundry performs temporary bonding and the OSAT performs the debonding. Such a supply chain is only feasible with the existence of standards for bonding and debonding processes and equipment.

Figure 3. EVG850 "XT Frame" Temporary Bonding and Debonding System

As previously mentioned, new TSV manufacturing processes are specifically engineered for different products, such as power devices or wide I/O DRAM, which typically means that different optimized adhesives are being used. LowTemp?? ZoneBOND??? debonding brought a revolutionary breakthrough toward standardization [2]. With this technology debonding is a function of the carrier, which makes the debonding process independent of the used adhesive. Figure 1 shows the ZoneBOND carrier wafer. In the center is a zone with reduced adhesion, whereas the edge zone provides full adhesion. Figure 2 shows the debonding process. First, the adhesive in the edge zone is dissolved in single wafer mode during the Edge Zone Release (EZR??) process. Then the device wafer is separated from the carrier wafer during the Edge Zone Debond (EZD??) process. The thin wafer is mounted on a film frame for subsequent singulation and assembly. The physical separation process happens at the interface between carrier wafer and adhesive film. During this debonding, the bumps are safely embedded in the adhesive film. No force is applied to the bumps during debonding. An open platform has been established which enables a versatile supply chain for ZoneBOND materials from multiple adhesive suppliers.

Temporary bonding/debonding was introduced for compound semiconductors more than 10 years ago, but in order to be ready for memory manufacturing, major changes to the equipment were required. The new EVG850 "XT Frame" Temporary bonding and debonding system is optimized for high volume memory manufacturing.

Wide I/O DRAM was the driving force that pushed TSV manufacturing in general and thin wafer processing in particular into high volume manufacturing readiness. For thin wafer processing, LowTemp ZoneBOND has enabled a standardization of equipment and processes. The open platform for adhesives has generated a versatile supply chain with multiple adhesive suppliers. The new equipment generation features integrated advanced process control on the module level, high throughput and optimized wafer cassette logistics.


ZoneBOND??? is a trademark of Brewer Science, Inc.

LowTemp??, EZR?? and EZD?? are registered trademarks of EV Group.


1. B. Patti, Lessons learned, Proc. IMAPS DPC 2011

2. T.Matthias et al., Room temperature debonding ??? An enabling technology for TSV and 3D Integration, Proc. IMAPS DPC 2012

DR. THORSTEN MATTHIAS is business development director at EV Group, St. Florian am Inn, Austria, ph: +43 676 84531148, e-mail: J??RGEN BURGGRAF is senior process technology engineer at EV Group. DANIEL BURGSTALLER is product manager at EV Group. MARKUS WIMPLINGER is corporate technology development and IP director at EV Group. PAUL LINDNER is executive technology director at EV Group.

Solid State Technology, Volume 55, Issue 5, June 2012

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