TSV inspection in 3D advanced packaging applications
REZA ASGARI, Rudolph Technologies, Inc., Flanders, NJ.
Laser triangulation provides fast, accurate and repeatable 3D measurement of TSV nails and microbumps.
Three-dimensional integrated circuits (3D ICs) using through silicon vias (TSVs) are gaining momentum as more and more technology challenges are being successfully addressed. Development projects are ongoing at semiconductor companies around the globe and some manufacturers have 3D ICs in production. 3D ICs offer several advantages such as faster communication, higher I/O, smaller footprint, lower power consumption, and more. It is safe to assume 3D packaging is here to stay.
FIGURE 1. TSV nails are formed by filling vias, usually with copper, etched into the wafer. The wafer is then flipped and mounted to a carrier wafer. A combination of processes is used to remove material from the wafer surface, leaving the ends of the copper fill protruding above the surface. These TSV nails will be matched to corresponding solder bumps on a stacked wafer or die to provide electrical connections. (Courtesy of Sematech)
TSV technology is a key technology for 3D ICs. Vias are etched into the silicon and filled with copper. The back side of the wafer is then thinned, typically using a combination of grinding and CMP, to reveal the end of the copper fill above the wafer surface (Fig. 1). This is often referred to as a copper nail. The height of these nails typically varies from 1 micron to 5 micron. A copper nail on one IC and a micro bump on another are used to stack two ICs to develop a 3D device. The height and co-planarity of the nails are critical parameters that must be correct to ensure the connectivity and, therefore, require inspection and measurement (Fig. 2).
FIGURE 2. On the left is an illustration representing TSV nails. The diagrams on the right illustrate one type of fault: non-uniform etching has created vias of varying depths, causing variations in nail height and failure of some nails to reveal at all.
Laser triangulation is a measurement technique that uses a scanned laser to collect 3D data points which can then be used to build a 3D model of the surface features. The speed and accuracy of laser triangulation have made it the dominant technology for three-dimensional characterization of solder bumps used in conventional packaging techniques such as flip chips. Microbumps and TSV nails used in 3D ICs are typically smaller, more closely spaced and more numerous, having diameters and heights as small as a few micrometers. The number of bumps and nails used in 3DIC schemes has grown explosively, with current roadmaps calling for as many as 1,000,000 per die and 60 million per wafer.
Existing metrology tools are significantly challenged to provide the speed and precision required to maintain sufficiently narrow process windows and ensure high yields. Heights of only a few microns require submicron 3D measurement precision. Diameters as small as 5 microns pose equally daunting challenges for 2D measurement. The large number of features places a heavy load on data storage and processing facilities. Finally, the measurement system must strike an optimal balance between precision and throughput if it is to be used in production.
FIGURE 3. Laser triangulation uses a finely focused laser and a position sensitive detector to measure feature height.
The inspection system (Wafer Scanner??? 3880, Rudolph Technologies) uses laser triangulation for 3D measurements of bump height and co-planarity (Fig. 3). A laser on the wafer surface at an angle of 45 degrees and focused to a spot size of 5 ??m scans a line 1.4 mm in length on the wafer surface while the wafer is transported in a direction perpendicular to the scanned line. Multiple scans provide coverage of the full wafer surface. A lens collects the reflected/scattered laser light and focuses it on a position sensitive detector. Changes in the location of the collected light on the detector provide height measurements with a resolution of 54 nm. The system has a 28 ??m depth of focus and an 8 MHz data acquisition rate. The combination of high scanning rate and wide scan path permits 100 percent 3D scanning of a 300 mm wafer in 23 minutes, at a throughput of nearly 2.5 wafers per hour.
FIGURE 4. a) 3D laser top view image.
FIGURE 4. b) 3D laser side view image.
During operation the system scans the wafer surface, simultaneously acquiring height data from both the tops of the nails and the surrounding wafer surface. The spacing of the data points can be varied to optimize efficiency. The system can display 3D data points collected on individual features as well as calculating various feature, die and wafer level results. Using data from the top of the nail and the immediately adjacent wafer surface to calculate height improves the accuracy and repeatability of the measurements.
A unique staggered scan technique further enhances the repeatability of height measurements. Staggering the scan increases the pitch in the direction of the line scan and reduces the pitch in the direction of the wafer movement, effectively spreading the data points more evenly over the wafer surface with no penalty in throughput.
Laser triangulation provides fast, accurate and repeatable 3D measurement of TSV nails and microbumps. In combination with camera-based 2D measurements it provides a complete metrology and defect inspection solution. The multiplicity of data points acquired on the top of each feature by the ultra-high resolution detector ensures measurement repeatability. The system can also measure heights of closely-spaced features where shadowing prevents the acquisition of data in some areas between bumps. The 8 MHz sampling rate and over 1 mm scan width provide production worthy throughput without sacrificing accuracy and repeatability. With feature sizes and pitches sure to decrease and numbers headed for tens of millions per wafer, the ability to tightly control processes and detect defects are essential to the success of 3DIC technologies and the profitability of 3DIC manufacturers.
Reza Asgari is wafer scanner product manager, Rudolph Technologies, Inc., Flanders, NJ.
Solid State Technology, Volume 55, Issue 5, June 2012