Lithography challenges for leading edge 3D packaging applications
Warren W. Flack, Manish Ranjan, Gareth Kenyon and Robert Hsieh, Ultratech, Inc., San Jose, CA. John Slabbekoorn, Andy Miller, imec, Leuven, Belgium
The lithography challenges associated with TSV fabrication for various devices structures are investigated.
The use of though-silicon via (TSV) technology was first commercialized by CMOS image sensor manufactures for use in high-end mobile phones . It is expected that memory companies will start utilizing TSV technology for stacking memory chips to meet the high data rate transfer requirements within the next few years [2, 3]. Lithography is one of the critical process steps that affect the final device performance and associated yield for TSV manufacturing. One of the unique lithography challenges during TSV process step is the need for back-to-front side alignment solution. This challenge arises from the fact that the 3D devices have active metallization levels on both sides of the device and when patterning the back side, the front side alignment targets are not visible using conventional alignment approaches. This paper investigates the lithography challenges associated with TSV fabrication for various devices structures.
Silicon test wafers were fabricated with a variety of films to evaluate the back-to-front side wafer alignment. The reference layer is defined in a standard damascene copper process and protected with a passivation layer. Next the wafers are flipped, bonded, and thinned to various thicknesses. Images of the embedded alignment target are shown for various silicon thicknesses and wafer surface quality. Experimental back-to-front alignment metrology data is shown as a function of silicon thickness for various film stacks.
The embedded lithography alignment target can be viewed using three different techniques as shown in Fig. 1. The lithography system used in this investigation implements a topside IR illumination configuration for back-to-front side alignment which provides flexibility in target number and placement on a 300mm wafer .
FIGURE 1. Three different techniques for viewing an embedded target for back-to-front side alignment.
The lithography system used for back-to-front side alignment is an Ultratech AP300 DSA. The stepper has a 0.16 NA, 1X Wynne-Dyson projection lens design, illuminated by broadband, three-wavelength ghi-line illumination. In this investigation two types of overlay tests were run on 200 mm wafers.
Single pass topside overlay test
The single pass topside overlay has alignment and metrology features etched in the top silicon surface. The base pattern wafers were created using an ASML PAS5500/750 deep UV scanner with a specially designed mix-and-match test reticle containing alignment targets and various metrology structures. These patterns were then etched 500 nm into the silicon surface to make artifact wafers. A complementary mix-and-match test reticle was used on the AP300 for single pass testing. Alignment of targets at the top surface of the wafer was performed using the off axis DSA camera. The photoresist was 1800nm thick IX845 exposed at 250mJ/cm2 in i-line mode. The resulting exposure wafers can be measured using conventional overlay metrology tools.
Double pass embedded overlay test
This technique measures overlay from embedded target alignment by forming structures at the top surface that can be measured using conventional topside metrology . The double pass test wafers were prepared using a copper damascene process. A dielectric layer consisting of 250 nm of SiO2 was deposited followed by an etch-stop layer and 600 nm of SiO2. Then a PAS5500/750 scanner was used to image a base pattern using a specially designed mix-and-match test reticle. After etching the 600 nm SiO2 layer, 1000 nm of copper was deposited to fill the trenches and Chemical Mechanical Polish (CMP) was used to expose the underlying oxide, leaving a flat surface with copper filled trenches. This was covered by a SiO2 passivation layer.
The copper damascene wafers were inverted and glued to a quartz carrier. The wafers were thinned using a grinding system to three Si thicknesses (100, 200, and 300 mm). The last step was polishing the surface by CMP to remove surface damage leaving an optically smooth surface. The resulting wafer cross section is shown in Fig. 2.
FIGURE 2. Cross section of test wafers with embedded damascene Cu targets.
A mix-and-match test reticle designed to match the PAS 5500/750 patterns was used on the AP300 for double pass testing. Two layers are sequentially aligned and exposed: the first layer is aligned to the embedded reference target and with the wafer oriented at 0?? rotation, and the second layer is aligned and exposed with the wafer oriented at 180?? rotation. Alignment of the embedded targets was performed using the off axis DSA camera.
Combining the two tests (single pass, and double pass) gives an effective method to calibrate back-to-front side overlay. The single pass test provides a means to monitor the full set of linear overlay terms, and the double pass test gives the relative mean bias between embedded target alignment and topside alignment.
Both single pass and double pass methods create overlay structures at the surface which can then be measured by a metrology tool or measured on the stepper using SSM. The SSM method was specifically designed to perform stepper-to-itself overlay testing for which both layers are produced in photoresist. All wafers in this study were measured using SSM per the overlay sampling plan shown in Fig. 3.
FIGURE 3. Overlay sampling plan on 200 mm diameter wafer consists of 21 measurements per field at 11 fields.
All metrology tools can introduce apparent errors known as tool induced shift (TIS) . These errors include asymmetries in the measurement tool interacting with the metrology mark , the materials contrast difference between layer 1 and 2 marks, and the algorithm for localizing mark features. A standard TIS calculation involves averaging two measurements taken at 0 and 180 degrees orientation.
For the single pass topside overlay test the TIS for SSM metrology was measured to be 113 nm and 39 nm for X and Y respectively. This error is primarily attributed to the SSM measurement construction which uses a single image model to capture layer 1 in etched silicon and layer 2 targets in photoresist. The materials contrast and the CD difference between the two layers affect the TIS error measurement for single pass testing. TIS errors in single pass testing with SSM can be minimized by matching layer 1 and layer 2 dimensions in process optimization. For the double pass embedded overlay test, the material contrast and CD error sources for TIS are avoided since both layers are patterned in the same photoresist.
Results and Discussion
Example image capture for embedded targets is shown in Fig. 4. It is clear that the non-CMP wafers in 4a have prominent scratch mark that could interfere with pattern recognition. To minimize this risk, the choice of target design should be composed of a variety of angles to make the target less sensitive to texture direction such as the split circle in 4b.
FIGURE 4. DSA camera view of (a) wafer after grinding, (b) wafer after grinding and CMP polish.
In cases where the appearance of a target is obscured, the use of a synthetically created target model helps the pattern recognition to disregard features that are non productive for pattern capture (Fig. 6).
FIGURE 5. Images of DSA targets through three thicknesses of Si. At 300 ??m the image gets grainier, but capture and overlay remain quite acceptable. Overall dimension of this target is 68 ??m.
Fig. 5 shows a metal target viewed through 100, 200, and 300 ??m silicon. Even at the thickest 300 ??m thick film the target image quality was good and no problems were observed for alignment capture or overlay performance.
FIGURE 6. Plot of mean error versus silicon thickness for double pass overlay.
In Fig. 6, overlay means in X and Y from the double pass embedded overlay test are plotted as a function of silicon thickness. The error bars denote ??1 standard deviation calculated from single pass topside data.
Test wafers with embedded Cu targets were fabricated in a variety of silicon thicknesses to evaluate the back-to-front side wafer alignment. Single pass topside overlay testing over an extended period of time shows that consistent overlay can be achieved well within the DSA specification of 2.0 ??m. More detailed double pass embedded target overlay testing shows that the effect of silicon thickness does not significantly impact the mean results relative to the single pass calibration. The results show that the simpler single pass topside test can provide reasonable accuracy for monitoring processes that align to embedded targets.
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5. Coleman, D. et. al, "On the Accuracy of Overlay Measurements: Tools and Mark Asymmetry Effects," Integrated Circuit Metrology, Inspection, and process Control IV Proceedings, SPIE 1261 (1990).
Manish Ranjan (lead author) is Vice President, Advanced Packaging and Nanotechnology Markets at Ultratech, Inc., 3050 Zanker Road, San Jose, CA 95124 USA; ph.: (800) 222-1213; email: email@example.com.
Solid State Technology, Volume 55, Issue 4, May 2012