Plasma etch challenges for FinFET transistors
KEREN J. KANARIK, GOWRI KAMARTHY, AND RICHARD A. GOTTSCHO, Lam Research Corp., Fremont, CA.
New constraints and challenges associated with FinFET manufacturing are reviewed from the etch point of view.
As the industry moves to 3D tri-gate FinFET architectures to overcome transistor scaling issues , additional etch challenges have appeared that may require new approaches to plasma etching. Compared with planar transistors, the performance of FinFET devices will depend more on etch because the multiple gates and vertical fin structures are created by the etch process. Not only are there more etch steps required to form these structures, there are also more surfaces of a FinFET transistor exposed to the plasma, resulting in the need for high-precision etching with minimal ??? ideally no ??? structural damage.
Shallow trench isolation (STI) etch processes for conventional planar devices have increased in aspect ratio with each successive technology node. In the case of FinFET structures, there is increased complexity because the fin is formed directly from the Si substrate, and therefore the STI structure and fin are etched simultaneously. Different feature profiles must be created during the same etch process because STI requires a tapered sidewall, while the silicon fin requires a vertical sidewall, as shown in Fig. 1. With FinFET devices, for the first time, the etch process creates the actual channel (the fin), so producing a precisely vertical fin with low surface state density is critical. Any unintentional variation in the shape of the fin (width, height, profile) or excessive surface state density caused by plasma etch-induced damage would alter the transistor channel.
FIGURE 1. The fin/STI etch requires creating both tapered isolation trenches and vertical fins, which will form the transistor channels.
After the fins are formed, the FinFET gate must be etched so as to wrap around the fin (Fig. 2). As with the fin/STI etch, the sidewalls of the gate must be etched vertically to reduce variability of the device parameters. To accommodate the 3D topography, the etch needs to stop on top of the fin while etching further down to the silicon substrate. Once the etch reaches the base of the structure, complete removal of residue from the 3D corner requires ~70-100% over-etch time, compared with ~30% for conventional planar gates. Throughout the entire exposure time, the process must avoid etching or damaging the exposed fin, which would adversely affect device performance .
FIGURE 2. FinFET gate etch needs to simultaneously maintain vertical walls and remove corner residue, while protecting the exposed fin from structural damage.
The spacer forms the mask for source/drain implantation, as well as encapsulates and protects the sidewalls of the gate. Like gate etch, spacer etch requires a directional process to prevent lateral consumption of the spacer material (CD loss), without damaging the exposed Si fin. In a planar transistor, integration schemes have typically included a liner film as a stop-layer to prevent Si loss during the etch process. In a FinFET device (and in many advanced-node planar devices), this liner film is omitted due to tight geometries, leaving the device fully exposed during the spacer etch. This is particularly problematic because a significantly longer over-etch is needed to fully clear residue at the bottom of the fin compared with planar transistors (~200-400% vs. ~30%). Consequently, the spacer etch is today considered the most challenging of the FinFET etch processes.
Challenge of atomic-precision etching
As described above, one of the biggest challenges in enabling FinFET formation is to directionally etch the transistor features without damaging them ??? etching with atomic precision. The requirement of directionality is essential because ions are one of the fundamental root causes of plasma-induced structural damage. At the molecular level, energetic ions (~10-1,000eV) cause the exposed film surface to "blur" due to a collision cascade that can spread and penetrate many monolayers deep. This produces a damaged region (the selvage layer) of mixed contaminants, dangling bonds, and voids that are beneficial for fast etch rates, but compromise precision.
Here we define the parameter "Etch Precision", PE, as the inverse of the number of damaged atomic layers that result from ion-enhanced etching. This can be expressed using measurable etch parameters:
where ERi = ion-enhanced etch rate (ignoring spontaneous chemical- or photon-induced etching), S = sticking parameter, JR = reactant flux, Ji = ion flux, ??i = ion energy, ??th = threshold energy, and ??sputter = sputter threshold energy. Ion-enhanced processes will have PE > 0, and values for current etch processes typically range from approximately 0.01 to 0.1, where higher values indicate that fewer layers of film have been damaged by the ions (Fig. 3). Results approaching PE ~ 1 have been realized under laboratory conditions with atomic layer etching (ALE), which uses alternating processes to remove one monolayer at a time . Unfortunately, today's ALE techniques produce etch rates that are too slow to be economically viable for manufacturing.
FIGURE 3. Higher Etch Precision (PE) indicates a more "pristine" or intact surface. Precision values for current etch processes typically range from ~0.01 to 0.1.
For practical purposes, the equation points to two conditions that improve PE for a given ERi. The first is to saturate the surface with reactants (increase S???JR). The second is to provide sufficiently energetic ions and surface-localized bombardment (increase Ji???(??i?? - ??th??), ??th < ??sputter). The difficulty is in satisfying both conditions concurrently for the duration of the etch process, for example, because the ions compete with reactant stickiness. This is particularly challenging for the plasma methods currently used for etching planar transistors.
Approaches to improve etch precision
One approach for improving PE is to lower electron temperature , which reduces the plasma potential and therefore lowers the ion energy to levels below those typically used for etch processes. Access to ??i < 15eV is possible with inductively coupled plasma reactors and other plasma sources and offers the benefit of a reactant-rich environment (saturates S???JR). However, the broader ion angle distributions at low energy will reduce directionality, causing CD loss (Fig. 4a vs. 4b). Moreover, the low-energy ions are unlikely to overcome ??th > ~50eV for FinFET film stacks. Therefore, etching with low ion energy is not considered a desirable approach for critical FinFET etches.
Another approach is time modulation of plasma parameters. For example, "sync pulsing" is one technique where source and bias powers are turned on and off in ~100??s cycles. When the powers are shut off, there is less dissociation and shallower ion penetration, which some claim results in higher PE . However, less dissociation can result in insufficient reactant flux for surface saturation (S???JR), which can lead to Si loss during FinFET etching (Fig. 4c). A promising alternative is "bias pulsing" in which the bias power is turned on and off, while the source power remains on. During the "on" phase, sufficiently high ion energy is provided to achieve directional etching in bursts that are less likely to cause damage. During the "bias-off" phase, the source power produces reactants that re-saturate the surface (increase S???JR). In this way, bias pulsing rapidly alternates between directional etching and surface saturation to deliver high-precision etching (Fig. 4d).
FIGURE 4. Comparison of different approaches for FinFET spacer etch. Bias plasma pulsing offers a viable approach for minimizing Si loss while maintaining directionality to prevent CD loss.
High-precision etching is more important than ever, and new etch techniques may be needed to achieve the requirements of 3D transistor architectures. While there is still work to be done, bias pulsing offers a viable approach to achieve directional etching with minimal structural damage that will be needed for manufacturing FinFET devices. ???
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The authors would like to thank Reza Arghavani, Joydeep Guha, Yoshie Kimura, and Ramkumar Vinnakota for their contributions.
Keren J. Kanarik, PhD, is a technical marketing manager in the Etch Product Group at Lam Research Corp., 4650 Cushing Pkwy, Fremont, CA 94538 USA; email: email@example.com
Solid State Technology, Volume 55, Issue 3, April 2012