Advanced packaging in the new decade
In the last decade, advanced packaging has emerged as an enabler of today???s electronic products. The impact of packaging, assembly, and test is increasingly felt in the semiconductor industry and package selection is important to the success of the end product. The industry has seen a package evolution in the past 10 years and the road ahead may require a package revolution. Issues for future packaging include handling and assembly of devices with low-k and ultra low-k dielectrics, especially with Pb-free bumps and fine pitch bumps such as copper pillar. When the first low-k wafers were shipped from the foundry to assembly houses, the same assembly processes and materials were used. No one realized that stresses in the assembly process would cause delamination within the IC structure that would result in reliability problems causing devices to fail. Because no one gave much thought to the assembly process, companies missed revenue shipments. Assembly and packaging houses scrambled to study the problem and eventually made process changes and adopted new formulations of materials such as underfill and mold compounds.
Fast forward to today. There is a power struggle emerging between some foundry players and the IC package contract and assembly test houses on who will do the assembly of die on silicon interposers. The discussion focuses on who will bear responsibility for certifying reliability if the foundry builds the interposer and assembly of that interposer is done at the packaging house. This will be more interesting to watch than a Japanese Noh play, but maybe the moves won???t be so subtle.
Not only is the assembly process important, but materials also play an increasingly critical role. Packaging and assembly of low-k and ultra low-k wafers has been an important topic of discussion at many recent conferences held by organizations such as IEEE CPMT and IMAPS. Presentations have discussed methods to minimize the potential for extreme low-k (ELK) delamination in flip chip packages with work focused on the design of the UBM structure, stress buffer layer materials, and types of substrates. Wire bond packages can also be impacted by the used of ELK materials in device fabrication and many companies are studying assembly and material requirements to solve potential issues.
Assembly of integrated circuits fabricated at the next silicon technology nodes will require changes in materials or new formulations of materials to handle the stresses of the future devices. Trends in 3D packaging indicate that new developments in materials and processes are likely to be required. Reliability concerns may change the type of bumps used, the underfill materials, substrate materials and construction.
The semiconductor packaging materials business also counts for an increasing amount of the revenue associated with the industry. The recent Global Semiconductor Packaging Materials Outlook published by SEMI and TechSearch International indicates that the market for semiconductor packaging materials was more than $22 billion in 2011 and is expected to grow to almost $26 billion by 2015. This includes organic substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.
Many IC makers have noticed that the cost of packaging devices is increasing rapidly, impacting margin and revenue. Choice of packaging solutions in the next decade will require careful cost/benefit analysis. Co-design of IC and package will no longer be a cute phase mentioned in PowerPoint slides, but a topic of serious discussion at any IC maker that plans to be successful in the next decade.
E. Jan Vardaman is president and founder of TechSearch International, Inc., 4801 Spicewood Springs Road, Suite 150, Austin, Texas 78759; email email@example.com.
Solid State Technology, Volume 55, Issue 3, April 2012