Evolution or revolution: the path for metrology beyond the 22nm node


Abraham Arceo, Benjamin Bunday, Aaron Cordes, and Victor Vartanian, SEMATECH, Albany, NY, USA

Metrology solutions are currently being investigated by SEMATECH to address the challenges of future nodes.

The 22nm node marks the beginning of a major transition from conventional scaling-driven planar devices to complex 3D transistor architectures, redefining future needs for lithographic, defect, and films metrology solutions for high volume manufacturing. Evaluation of critical dimension (CD), roughness, dopant distribution, and other parameters in FinFETs raises new metrology complexities, as the entire 3D structure becomes critical for process control, including fin and gate dimensions, profiles and roughness, and metal gate undercuts. Similarly, future 3D memory devices will include multiple gate-level structures defined by high aspect ratio (HAR) trenches and holes in multilayer stacks, which are major gaps in current metrology technology. No in-line non-destructive metrologies have achieved the sensitivity and resolution to image or measure CD, depth, profile, or contamination of such HAR features [1]. In addition, defect metrology inspection and review suffer from low sensitivity and inadequate throughput even for current 22nm defects of interest. To address these challenges, a robust metrology strategy should encompass the extendibility of conventional techniques that are approaching their fundamental limits, as well as development of new technologies.

FinFET metrology

Planar transistors are reaching their critical performance limitations due to undesirable short channel effects imposed by physical scaling. In 3-D FinFET or trigate devices, the gate surrounds the channel on multiple sides, resulting in higher drive current [1], better electrostatic control (lower off-state leakage), and lower supply voltage requirements than planar devices. To continue to scale with Moore's law, devices having 3D architectures will enter manufacturing in 2012 at the 22nm node.

Metrology demands for 3D structures and their more complex integration steps are considerably greater than for 2D devices. The ability to measure fin and gate dimensions accurately with good precision, and to detect subtle process changes for feedback or feed-forward control is essential to assure good device performance and high yield in high volume manufacturing (HVM). For example, variations in FinFET height (more of a concern on bulk Si substrates) can likewise lead to drive current variability. Sharp fin corners can affect threshold voltage [1], and gate dielectric undercutting can cause shorts between the gate and channel regions or Ion/Ioff variation. Fin line edge and width roughness, sidewall angle (SWA), profile, corner rounding, and gate dielectric undercutting are also critical process control variables. Some of the critical metrology steps entail critical dimension-scanning electron microscope (CD-SEM) measurements (resist and etch fin and gate CD and pitch; spacer width at the bottom; pre- and post-etch Hi-k/metal gate sidewall thickness on the fin; and sidewall line edge roughness). Additionally, scatterometry is required for fin height and gate profile, CD, and pitch (lithography and etch), buried oxide (BOX) recess under fin, gate height over fin after chemical mechanical polishing (CMP), high-k/metal gate thickness and taper on the fin and recess after gate etch, and spacer profile (Fig. 1).

Figure 1. Left: Cross-sectional diagram perpendicular to the fin showing the gate on the fin with spacer. Right:Diagram of a basic unit cell of a FinFET, demonstrating twelve important process control parameters.

Conventional metrology methods used in HVM, such as CD-SEM and optical scatterometry, may be challenged by the increased complexity of FinFETs. While CD-SEM demonstrates superior imaging capability, it has no sensitivity to fin height, layer recess, or SWA. Scatterometry is useful for FinFET metrology, but greater parameter correlation increases the measurement uncertainty, similar to increasing the number of variables in an equation. In Figure 1b, showing a diagram depicting a gate-on-fin structure, twelve parameters must be solved by the scatterometry software rather than only the five or six parameters typical for 2-D devices. One possible approach to improve the performance of metrology on complex structures is hybrid metrology, which combines the strengths of two or more metrology toolsets to provide a more comprehensive measurement of the same parameter than the individual techniques. Data obtained from one tool must be shared with another tool and used in a complementary or synergistic way to enhance the resolving power of both tools, thereby improving measurement uncertainty [2].

Several new metrology techniques are being explored at SEMATECH to improve measurement performance on FinFETs, including new technologies such as critical dimension small angle x-ray spectroscopy (CD-SAXS) [3]. The shorter wavelength (1.54?? for Cu Ka) for CD-SAXS and the lack of material dependence (no n and k sensitivities) allow measurements on smaller devices with less parameter correlation. Pitch and pitch variation can be obtained from major reflections and intensity decay with increasing order. The CD-SAXS envelope functions correlate to geometric form factors, and line width roughness (LWR)/line edge roughness (LER) information can be obtained from peak-broadening. Mueller matrix scatterometry [4] provides additional structural information associated with up to 16 spectral components compared to conventional scatterometry, which is important in measuring anisotropic 3D structures.

Dopant and carrier metrology for conventional planar devices has been performed primarily using secondary ion mass spectrometry (SIMS) and sheet resistance metrology on test pads. However, FinFET structures require novel ultra-shallow junction implant strategies because of shadowing effects on densely packed fins from conventional tilt implants. Metrology capable of measuring dopant and active carrier concentrations on vertical structures is needed, but currently poses a significant challenge. Three-dimensional atomic probe tomography (3D-APT) [5] combines field evaporation with time-of-flight mass spectrometry and a position-sensitive detector to provide atomic resolution imaging of the semiconductor device, including dopants. Similarly, scanning spreading resistance metrology (SSRM) is a candidate for active carrier metrology at nanometer spatial resolution. SSRM has demonstrated excellent performance in conjunction with 3D-APT and SIMS [6]. Transmission electron microscopy (TEM) techniques such as energy-dispersive X-ray (EDX) and electron energy-loss spectroscopy (EELS) are valuable in determining dopant concentration and distributions. As these implant metrology techniques are destructive, in some cases, it may be possible to create sacrificial test structures on selected die without affecting subsequent processing. Optically based implant metrology will also be more difficult on sidewalls and on structures having optically opaque layers.

3D memory metrology

Memory producers are migrating beyond planar designs to build multiple levels of gates into 3D structures. These vertical architectures lead to new challenges in semiconductor processing technology [7]. As shown in Fig. 2, the basic building blocks of these features are deep, high aspect ratio (HAR) trenches and holes in oxide, silicon, or multiple alternating layers of oxide and silicon.

Figure 2. Left: Diagram of pipe-shaped bit cost scalable (P-BiCS) flash memory cell, which consists of pipe-shaped NAND strings folded in a U shape [7]. This is an example of the types of 3D memory devices that will require HVM metrology. Right: Diagram of various measurement needs on such a structure.

3D memory structures present many metrology challenges due to their HAR characteristics. HAR contact holes and trenches at ITRS half-pitch dimensions are known gaps in CD and profile metrology; these same measurement limitations have, to some extent, already been apparent with etched contact holes and shallow trench isolation (STI) trenches in logic for recent ITRS nodes. Furthermore, the problem is increasing with shrinking dimensions. HAR etching is difficult, with 30:1, 40:1, or even 60:1 ARs necessary to form a vertical circuit path among stacked gates. Process control of the bottom of the CD, profile, and detection of polymeric etch residues is required for HVM. While TSVs may have a similar or higher AR, they are comparatively huge???3D memory device features will include hole and trench structures with bottom CD sizes at ITRS node dimensions [8], from 0.5 to 2 microns deep. This introduces an entirely new set of gaps in metrology capability as the quest for non-destructive measurements of such features has yet to achieve the necessary sensitivity and resolution. Moreover, the physics of these measurements is incompatible with the extremely deep and geometrically-confined volumes involved. Charged particle imaging techniques such as CD-SEM and helium ion microscopy (HeIM) [9] have sensitivity limitations arising from sidewall charging, as only a small fraction of scattered particles follow escape trajectories that reaches the detector. Also, many optical techniques, especially those that operate off-axis near the critical angle, suffer from a very small fraction of the interrogating light reaching the feature botto, and reflect upwards to the detector. Thus, in most cases, the various metrology techniques in their present forms will suffer low signal-to-noise ratios (SNRs) on such features.

Many technologies are being explored at SEMATECH to enable HVM of HAR features, including new technologies such as critical dimension small angle X-ray spectroscopy (CD-SAXS) [3], HeIM [9], and through focus scanning optical microscopy (TSOM) [10] and variations of existing technologies, such as Mueller matrix [2] and normal incidence scatterometry (polarized reflectometry), model-based infrared reflectometry (MBIR), high voltage SEM (HV-SEM) [11], environmental SEM (e-SEM) [12], and conventional low-voltage CD-SEM. Results are still forthcoming, but CD-SAXS and scatterometry at normal incidence, MBIR, and HV-SEM may have some capability in this application space. CD-SAXS is currently a lab technique, but X-ray sources with higher brightness offer possibilities for transforming this technique into a feasible HVM metrology tool. MBIR takes advantage of the transparency of the various applicable materials to infrared and thus may have sensitivity to some feature aspects. HV-SEM is being demonstrated as useful in providing the capability to charge HAR holes in such a way that reflected incident or secondary electrons can more easily escape the bottom of the feature. Normal incidence scatterometry may be feasible as more incident light can reach the bottom for potentially improved SNR.

Defect inspection and review

Future challenges for defect metrology go beyond merely extending the capability of current technologies to meet ITRS requirements [8]. In fact, in recent years the yield enhancement chapter has shown that the semiconductor industry consistently arrives at each new technology node without a long-term solution that combines defect sensitivity and throughput requirements at either development, ramp-up, or HVM phases[8]. The reason for this is that both defect inspection and review are approaching their fundamental limits, which cannot be easily circumvented with gradual improvements on workhorse toolsets [13]. In the specific case of inspection, optical simulations show that the defect contrast signal decays aggressively beyond the 22 nm node, and predict that DUV bright field tools are likely to lack useable signal at or beyond the 11 nm node. Further, it is also expected that wavelength scaling will not provide an acceptable solution, prompting the need to seek alternative technologies that rely on different contrast mechanisms that may bridge this gap. Examples of these include interferometric (phase shift signal) [14], near-field (sub-wavelength resolution), or fast probe microscopy [15]. This path-finding effort will have a steep learning curve in terms of the application space for these techniques and the engineering to translate them into manufacturing-worthy tools. An alternative path to achieve sub-11 nm inspection capability may be e-beam inspection. In this case, the challenge is not resolution but increasing the system throughput by several orders of magnitude, which will most likely require a breakthrough in e-beam column parallelization. Early efforts are currently driven by lithography needs, but could benefit the inspection application space [16].

Figure 3. There is a single defect in this 22nm-node SRAM array. Can you find it?

After defects are found (see Fig. 3 for an example), they must be identified and sourced to maintain yield, requiring increasing amounts of off-line lab analysis. As features shrink, the X-ray interaction volume used in EDX for in situ defect analysis (Fig. 4) is becoming larger than the sizes of critical defects. The only solution appears to be an explosive growth in the workload of the TEM characterization lab. The limitation to TEM is not capability but throughput. TEM requires extensive, time-consuming sample preparation. Moreover, the microscope itself is a complex device that traditionally requires hours of work by a highly skilled operator to obtain good results. The solution therefore is to focus on both problems. To this end, SEMATECH is working with leading suppliers to develop faster sample preparation techniques, by both optimizing existing technologies and testing novel methods such as plasma focused ion beam (FIB) and laser-based milling. SEMATECH is also working in cooperation with its strategic partners to develop higher speed TEM imaging capabilities. This includes testing the latest generation of high sensitivity and high throughput windowless detector systems and developing automated image setup and metrology on critical dimension scanning/tunneling (CD-S/TEM) systems.

Figure 4. Sample image of a high-speed EDX element map taken on a SEMATECH FinFET sample. Total collection time was 4 minutes.


As device technology transitions from traditional scaling to new architectures, new application needs are driving metrology towards evolutionary and revolutionary shifts in technologies and methodologies. Adaptation to new tool paradigms, enhancements of existing technologies, and productivity innovations will be critical to maintain process control and high yield in the coming technology generations. The SEMATECH Advanced Metrology Program is well positioned to develop solutions to address the measurement challenges of next generation devices.


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ABRAHAM ARCEO is a Metrology Development engineer at SEMATECH Advanced Metrology group. For the past three years he has been involved in film and defect inspection metrology development. BENJAMIN BUNDAY is the Project Manager of CD Metrology and a Senior Member Technical Staff at SEMATECH (Albany, NY, USA). For ten years he has led SEMATECH/ISMI's CD-SEM and OCD benchmarking, advanced CD technology evaluation and development efforts, and SEMATECH's Advanced CD Metrology Advisory Group (AMAG). AARON CORDES is a research engineer for Sematech in Albany doing work on AFM, TEM, and focused ion beam metrology. He is also a PhD student with SUNY Albany's College of Nanoscale Science and Engineering. VICTOR VARTANIAN is a metrology engineer at SEMATECH in Albany, New York. Before coming to SEMATECH, he worked at Freescale Semiconductor in Austin, Texas, where he worked on applications of strained silicon to advanced transistor design and analytical applications of FTIR and mass spectrometry to environmental issues in semiconductor manufacturing and in process optimization.

Solid State Technology, Volume 55, Issue 2, March 2012

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