Packaging with 3-D architectures
Microelectronic Consultants of NC
Research Triangle Institute's 3-D Architectures for Semiconductor Integration and Packaging Conference, or 3D ASIP (as it has become known) normally finishes off the "3D conference circuit" for the year and is a good gauge of how far things have progressed in the last 12 months. At the 7th 3D ASIP in Burlingame CA, there were several announcements, statements and rumors having significant impact on the 2.5/3D community.
Much of the "buzz" at this year's meeting certainly centered around the presentation by TSMC's Doug Yu, who made the case for the pure foundry model for 2.5 and 3DIC, stating that TSMC was readying full beginning-to-end interposer manufacturing. Yu said that sharing the fabrication process with OSATS was not the preferred option for TSMC because "the risk for the customer is too high" and therefore TSMC would "take full responsibility and accept full risk."
Since the profit margin for packaging and assembly is currently substantially less than that for a foundry like TSMC manufacturing chips, cost-sensitive customers appeared worried that packaging and assembly costs would increase substantially if turned over to foundries. Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing. "This is a new ballgame. The old ways of doing business are out of date for this new technology," Yu said.
When asked about the incorporation of other foundries' chips onto the interposer or chip stack, Yu said there is no need to go to other foundries/IDMs except for memory, and that TSMC would partner with one or more memory suppliers.
During my presentation detailing the status of 3DIC entering 2012, the issue of interposer categories came up. Basically interposers can be categorized as either being high density l/s ~ 1??m/1??m which could only be manufactured by CMOS fabs/foundries, and what we can call "coarse" featured interposers with l/s > 5??m/5??m. The latter could be fabricated by any of the OSATS who all have standard bumping and WLP processes capable of standard RDL. In a later presentation, Raj Pendse of STATSChipPAC indicated that 5??m l/s and sub 25??m TSV pitch was the transition point between OSAT and foundry capability.
While all the OSATS have such capability, products have not yet been announced that would use such coarse-dimensioned interposers and none of the OSATS have announced any intention to produce any interposers. One OSAT requesting anonymity later commented: "It is correct that we are not offering "coarse" interposers, although we have capability to produce them ??? this is because we don't see ourselves competing in that space with foundries and don't think it will be a viable business worth chasing."
Eric Beyne of imec also questioned whether coarse interposers would provide enough value to be integrated into products. Similar responses were received from other OSATS in attendance.
Lei Lei Zhang of NVIDIA made what could become the rallying cry of the upcoming 3D decade when she said: "Scaling is ending. Let's get over it and move our resources elsewhere." Zhang declared that for them bandwidth is the issue. She indicated that NVIDIA is likely to use a turnkey solution such as TSMC is offering with such 2.5D TSV solutions entering the NVIDIA roadmap with their TESLA and CUDA high end networking GPU product lines.
While Altera's Bradley Howe predicted that "there are 8-10 years left to scaling, and then 3D will be the solution," he was quick to show 2.5D prototypes they are readying for the market. With archrival Xilinx already sampling the market with 2.5D products, that's probably a good idea.
Solid State Technology, Volume 55, Issue 2, March 2012