3D integration: not a windfall for test
Mike Slessor, PhD, is CEO of MicroProbe, 617 River Oaks Parkway, San Jose CA 95134; ph 408.457.3900; www.microprobe.com
After a seemingly interminable run of being ???a year away,??? it is clear that 3D integration (or at least the silicon-interposer-enabled 2.5D version) now offers a viable path to achieve the performance, cost, and feature integration required of next-generation mobile devices. As with any significant shift in process technology, a redistribution of the value provided by different semiconductor supply-chain elements is likely here, along with a corresponding shakeup of the winners and losers in the supply chain.
To capitalize on this value redistribution, some in the test community are advocating the need for known-good-die (KGD) testing for every element of the 3D die stack prior to assembly. Intuitively, this is a reasonable approach. After all, who would want to kill a good 7-die stack by attaching a non-functional eighth die to it? Such a ???KGD for effective 3D integration??? position, however, leads to an interesting set of implications.
The most important of these implications is the test cost resulting from a universal KGD strategy. In many scenarios, this 100% test coverage for each component die and each die-stack subassembly would result in a cumulative test cost that exceeds the total target chip cost. Such a prediction is reminiscent of the (tongue-in-cheek) 1960s-era projection that the number of US physicists would exceed the entire American population in the next century ??? in each prognosis, at least one underlying assumption is flawed. In our 3D integration case, although the increased test coverage demanded by KGD would result in a significant increase in test equipment and consumable spending, it seems unlikely that a chip where the test costs exceed the COGs (cost-of-goods) budget would actually see the light of day.
Instead, it???s probable that chip manufacturers will deploy a more selective approach to determine the economically-optimal test coverage. A clear tradeoff exists between test coverage and cost, and the cost of packaging non-functional devices into a previously-functional stack. An excellent analysis of these tradeoffs was presented by an Advantest-Verigy team at this year???s SEMICON West ATE Vision 2020 Program. In all cases examined, the overall cost as a function of die-level test coverage has a minimum at less than 100% test coverage, i.e., the KGD approach results in a lower return-on-investment (ROI) than an optimized lower-coverage strategy.
Such an approach is not new to the semiconductor industry. In fact, a similar ROI-based approach to inspection and metrology has been employed in front-end wafer fabs for many years. Although 100% sampling (the analog of KGD) would probably generate the maximum die yield, it definitely results in the maximum inspection cost. As a result, sub-100% sampling (the analog of some-good-die) provides a higher ROI and lower total cost than complete 100% sampling, even though it may mean throwing a few die, sub-assemblies, and even complete die stacks in the trash bin.
However these strategies are employed to support 3D integration, the test supply chain must continue to execute on familiar initiatives that decrease the unit cost associated with each test insertion. In particular, continuing the roadmap advances in parallel multi-die test, built-in-self-test (BIST), and adaptive test techniques should continue to be a key focus for test equipment and consumable providers, and will provide cost-of-test improvements for all types of semiconductor devices, not just the 3D flavor.
Although it might make the grass in the test supplier neighborhood quite a bit greener, sweeping insertion of KGD test strategies with 3D integration might well kill the grass in the neighborhood where our chipmaker customers reside. Consequently, they???re unlikely to advocate and fund such an approach.
Solid State Technology, Volume 55, Issue 1, January 2012