Metallization processes for standardized wide-IO memory applications


Claudio Truzzi, Alchimer, Massy, France

Expensive vacuum-based, dry-process tools developed for sophisticated dual-damascene applications are not the fittest solution for the manufacturing of TSVs for 3D-IC applications.

Wide-IO memory is attracting substantial interest in the portable electronics space, with good reason ??? it combines performance enhancements and a smaller form factor with potential for substantial cost savings and reduced power consumption. Through-silicon vias (TSVs) are an important enabler for wide IO, and there is significant movement towards standardization of via structures, most likely on a via-last process with vias 10??m wide by 50 deep. Metallization of this type of structure poses a number of technical and economic challenges to existing deposition processes. This article will explore the pros and cons of several possible approaches, and propose a process flow that offers cost and performance capabilities that can help realize the outstanding potential of wide IO in the most effective way.

The ever-shrinking planar transistor model our industry has been based on since its inception is reaching its physical limits and is rapidly becoming unsustainable. It has been several years since the semiconductor industry began considering three-dimensional integrated circuits (3D-IC) and through-silicon vias (TSVs) as serious potential solutions for the exponentially increasing costs associated with ongoing technology node transitions. As usually happens with new technology introductions, most of the TSV alternatives available a few years ago have been shaken off, and mainstream solutions are now crystallizing around three major applications:

  1. Via-middle. TSVs are manufactured in wafer fabs after the front end of line (FEOL) and before the back end of line (BEOL). Typical applications include CPUs and graphics chips. TSV dimensions are in the 5-10??m range for diameter and 50-100??m for via depth.

  2. Via-last. TSVs are manufactured after the completely processed wafer has been thinned and bonded to a temporary carrier. Typical applications include memory stacks. Dimensions are driven by the wide IO memory interface standard being reviewed by JEDEC and are in the 8-15??m range for diameter, and 50-60??m for via depth.

  3. Interposers. Also known as 2.5D solutions, interposers allow few chips to be densely packed into a single module, and include TSVs. Applications include first-generation memory-on-logic modules for mobile devices. Dimensions are in the 10-20??m range for the diameter, and 100-150??m for the depth.

TSVs are fabricated by drilling holes in the wafer, typically using a specific Si-etch solution called Bosch process, followed by the deposition of an electrically insulating liner, a copper diffusion barrier layer and a copper seed film. The hole is then filled with a copper plating solution. A CMP step is typically performed to remove the overburden deposited on the wafer flat by the previous steps.

TSVs for wide IO standard applications are mainly of the via-last type. For such vias, after the silicon has been etched by the Bosch process, the BEOL inorganic layer stack also must be removed by a specific dry oxide etch process in order to expose the metal pad.

Traditional dry-process solutions

Let's consider how the average semiconductor engineer wishing to manufacture TSVs might think about implementing this new technology. The task has several interconnected aspects ??? choosing a process and equipment set has implications for materials and also for costs. And while this risk-averse industry has always shown a strong preference for field-proven approaches to production, the use of toolsets designed for other types of processing carries with it some unique legacy issues.

There is, of course, an extensive suite of equipment on the market today that was designed for production of the constantly shrinking planar transistor. The mere fact of familiarity provides a certain amount of reassurance; our hypothetical engineer and his or her colleagues would be familiar with the tools and their capabilities.

This approach would likely include chemical vapor deposition (CVD) for the isolation liner; CVD or ionized plasma vapor deposition (iPVD) for the barrier layer; iPVD for the copper seed film; electrochemical copper deposition (ECD) for the fill. This equipment set would dictate the material set: SiO2 for the isolation; TiN or TaN for the barrier; and Cu for the seed.

Let's consider some of the factors involved:

??? For TSV applications, these tools are typically over-specified and therefore unnecessarily expensive;

??? Because they are designed to deposit material on planar, not vertical, surfaces, dry tools often struggle to perform effectively in TSV structures;

??? The required materials are too stiff (SiO2), too resistive and too brittle (TiN, TaN).

The consequences include:

??? Micro-cracks in the isolation liner due to thermal mismatch between the copper plug and the silicon bulk, coupled with high elasticity modulus of SiO2.

??? Unacceptably thin barrier layers, to the point they become electrically discontinuous at the bottom section of the TSV sidewalls.

??? Too-thick copper overburden deposited onto the wafer flat to insure a minimum copper thickness at the TSV bottom (e.g., 1,500nm) on the flat to obtain 200nm on the bottom).

??? For wide IO standard TSVs:

??? Metal resputtering onto the TSV Si walls during the dry oxide etch step in via-last applications, when the etching plasma hits the metal 1 layer in the BEOL;

??? Micro-cracks in the metal pad, also induced by the dry oxide etch, which is an aggressive step.

As a result, this choice restricts the dependable TSV process window to an aspect ratio (bottom/top thickness) lower than 5:1 and to vias larger than 10??m. However, large Cu-filled vias inject unacceptably high stress (proportional to the square of the via diameter) into the surrounding silicon bulk, as well as linearly increasing parasitic capacitance with via diameter. An additional restriction is imposed on the upstream Bosch etch process: because these dry-process methods require very smooth TSV sidewalls, the Si etch process has to run very slowly (i.e., with reduced throughput), in order not to create scallops. Finally, the excessive Cu overburden on the wafer surface requires a long and expensive CMP step.

The bottom line is expensive equipment, underperforming materials, and compromised process windows. It all adds up to generate what many consider the main roadblock to a wider TSV adoption ??? excessive manufacturing cost. However, this cost is a direct consequence of the tool/material choice consciously made above. Alternative, production-ready TSV manufacturing technologies are available ??? today.

Figure 1. 5x100??m TSV lined with wet process isolation and barrier, showing excellent step coverage values.

Nanotechnology-based wet-process

One such alternative solution has been designed and developed from the ground up to address the specific requirements of TSV applications and to deliver higher performance at significantly lower cost. It is based on a radically new approach: all films (isolation, barrier and seed) are deposited by wet process [1]. The main advantage of this solution is that all films are conformally grown from the surface up, rather than being deposited onto it. This ensures the same thickness everywhere, independent of the surface topography, as shown in Fig. 1, which illustrates a 5x100??m TSV lined with wet-process isolation and barrier layers. We discussed this solution in detail in the April 2011 issue of Solid State Technology [2], concluding that all layers and fill can be deposited with one single semiconductor-grade plating tool, enabling a large reduction in CoO per wafer as compared to dry process approaches.

Figure 2. Typical wide IO TSV dry process flow.

Figure 3. Wide IO TSV wet process flow.

One interesting evolution of this wet process approach is its ability to simplify the wide IO standard TSV manufacturing flow and at the same time solve the major problems of the dry process flow, as indicated above. Figure 2 shows a typical wide IO TSV dry process flow with an indication of the occurrence of metal resputtering on the TSV Si sidewalls and metal pad micro-cracks. Figure 3 illustrates a shorter wide IO TSV wet process flow that consists of:

  1. Bosch silicon etch.

  2. Wet oxide etch. This step does generate an undercut at the bottom of the via. Undercuts represent a problem for dry process solutions, because the material cannot be correctly deposited. However, since fluids can find their way to the most recessed corners, wet-process layers can conformally grow onto undercuts, as well. The metal pad should be protected by a barrier layer for this step to be effective.

  3. Selective isolation deposition. A unique property of this wet isolation layer is the possibility to selectively grow onto silicon only under given conditions ??? no isolation layer will be deposited on the inorganic dielectric or onto the metal pad, simplifying the process.

  4. Conformal barrier deposition. The wet barrier layer, on the other hand, grows onto a large number of different materials. In one single process step, the barrier is grown onto the wet isolation layer, the BEOL dielectric and the metal pad.

  5. TSV Cu fill. Because no seed is necessary, the TSV can be filled using a direct-on-barrier plating approach.

CoO/wafer comparison chart

Steps 2 through 5 are performed exclusively on wet tools (wet processors, plating equipment) ??? the resulting CoO per wafer for wide IO memory standard TSVs is more than 50% lower than for a traditional dry-process, as indicated by the comparative chart shown in Table 1.

Table 1. CoO comparison chart.

Assumptions: Via Last

??? Wafers: 30K 300mm wafter starts per month

??? Dry process CoO: as per EMC3D model

??? Cost model assumptions: as per SEMATECH

??? Etch Rate: Bosch Etch Rate can be doubled with Wet Process

??? Overburden for Dry: 800nm Cu seed + 0.6??m plating = 1.4??m overburden

??? Overburden for Wet: no Cu seed + 0.6??m plating = 0.6??m overburden


Maskless backside isolation

This new generation of nanotechnology-based wet-process films provides process simplification, performance boost and cost reduction beyond TSVs. A typical example is the deposition of the isolation layer after the via-last process described above. For wide-IO memory standard applications, after wafer backside CMP, the bulk of the silicon wafer is exposed again and requires an isolation layer before plating the under bump metallurgy (UBM) and bonding the micro-bumps directly onto the TSV plugs. Silicon oxide or organic materials are typical materials used for this isolating layer. Organic materials, however, tend to crack beneath the UBM pads during the thermo-compression bonding process required to bond the micro-bumps. Moreover, both organic and inorganic layers are deposited as blanket layers and have to go through a photolithographic step to open the exposed TSV backside again in order to make electrical contact with the UBM pad.

When the wet-process isolation layer is used, the process flow is more streamlined because of the selectivity to silicon of this wet isolation film. Instead of being deposited as a blanket layer, under certain conditions this film grows selectively on silicon only and leaves the metal TSV plugs exposed ??? no lithographic step is required, and a cost-effective maskless backside isolation (MBI) layer deposition process is achieved, as shown in Fig. 4.

Figure 4. Self-aligned maskless backside isolation layer deposition with wet process.


Expensive vacuum-based, dry-process tools developed for sophisticated

dual-damascene applications, are not the fittest solution for the manufacturing of TSVs for 3D-IC applications, as they are too expensive, utilize underperforming materials, and force compromised process windows. A proven, wafer-fab compatible alternative solution exists, based on a new nanotechnology-based wet-process approach, developed from the ground up to specifically address 3DIC issues in general, and TSV requirements in particular. This solution offers superior performance and, when applied to wide-IO memory standard TSV applications, it cuts in half the cost of TSV manufacturing, and it simplifies the "post-TSV" process flow by removing the need for a complete photolithographic cycle.


1. D. Shur et al, "Through-silicon via metallization: A novel approach for insulation/barrier/copper seed layer deposition based on wet electrografting and chemical grafting technologies," MRS Fall Meeting 2008, Boston

2. Claudio Truzzi, "Wet-process technologies for scalable through-silicon vias," Solid State Technology, April 2011.

Claudio Truzzi is CTO at Alchimer SA, Z.I. de la Bonde, 15 rue du Buisson aux Fraises, 91300, Massy, France;ph.: +33 (0)1 69 75 43 43;

Solid State Technology, Volume 55, Issue 1, January 2012

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