Issue



Atomic layer deposition goes mainstream in 22nm logic technologies


11/01/2010







 

Executive Overview

Atomic layer deposition (ALD) will be used in multiple areas of the 22nm logic process flow despite initial concerns about the technology's viability for high-volume manufacturing. Each application space creates a unique need for manufacturing equipment configuration and technology variations – from single-wafer ALD systems for extremely tight process control, batch ALD systems for low COO operation, to mini-batch systems for a meld of COO and process control for multi-layer applications. Selection of the appropriate manufacturing toolset is as critical to eventual technology adoption as the process itself, and final implementation will require the correct toolsets to ensure that the ALD films can be deposited in a cost efficient manner.

 M. Verghese, ASM, Phoenix, AZ USA;  J. W. Maes, ASM, Leuven, Belgium; N. Kobayashi, ASM, Tokyo, Japan

Since its invention in the 1970s, atomic layer deposition (ALD) has been used in a variety of applications ranging from electroluminescence display manufacturing to industrial coatings [1]. Over the last decade, the semiconductor industry has slowly been adopting ALD reactors for critical layers where the benefits of ALD enable scaling and improved performance. With the upcoming transition to 22nm, process flows are being adapted to allow ever more ALD layers. As a variant of chemical vapor deposition (CVD), ALD techniques capitalize on surface saturation reactions to deposit extremely smooth, dense, and highly conformal films through a process that is relatively insensitive to fluctuations in process temperature and reactant flux. The ALD process relies on sequential introduction of the reactants into the reaction space, separated by inert gas purges, such that repetition of the ALD cycles results in a monolayer by monolayer growth of the deposited film. Thickness of the film can then be precisely controlled by adjusting the number of ALD cycles.

Process considerations for single-wafer tools

DRAM manufacturers were the first to use ALD to ensure conformal deposition of high-k dielectrics in high aspect ratio capacitor structures. Aggressive scaling of device dimensions and the subsequent requirement of low thermal budgets to control dopant diffusion continue to push the entire semiconductor industry to displace conventional CVD, plasma enhanced CVD (PECVD), and sputtering techniques with novel ALD processes in critical areas such as transistor gate stack formation and spacer defined double patterning. The low throughputs that are typically associated with ALD techniques have been a barrier to its adoption in mainstream production flows. However, these concerns are being addressed by intelligent equipment design to optimize the ALD process and hardware for individual application spaces. At the 22nm node, the logic industry will use ALD in several key process steps – both in front end transistor formation and in back end metallization and interconnect. Each application has highly specific requirements and calls for different hardware configurations for the optimal production solution.

Single-wafer ALD chambers are ideal when the application demands extremely thin films with precise thickness and uniformity control. Single-wafer systems can also most easily handle difficult precursor chemistries such as low vapor pressure, decomposition prone liquids and solids since ALD cycle times are typically short (in the order of a few seconds) and the source delivery systems can be placed in close proximity to the reaction chamber. Purge efficiency can be optimized relatively easily in single-wafer systems and as a result, these chambers are ideal for pure ALD deposition.

Figure 1. Need for complete ALD high-k/metal gate solution in 22nm logic transistors.

Single-wafer ALD systems also have high precursor utilization efficiencies and hence, are a good fit for processes that use expensive precursor materials. For example, high-k dielectrics and metal gates for transistor gate oxide and electrodes require deposition of films as thin as 10Å while maintaining within wafer uniformities of <1%, 1σ. Hafnium-based high-k gate oxides typically use hafnium chloride, a solid precursor, for its excellent electrical performance when compared to metal organic chemistries [2]. Single-wafer systems tend to be the best choice for gate oxide deposition as they are very capable of delivering this highly condensable precursor. Furthermore, replacement gate devices require multiple, conformal metal films <50Å thick to ensure that space remains for a gate contact fill (Fig. 1). Single-wafer plasma-enhanced ALD (PEALD) is also used for the deposition of silicon oxide, silicon nitride, and silicon carbon nitride gate spacers. PEALD enables low-temperature deposition (<400°C), excellent conformality, and lower wet etch rates than films deposited by plasma enhanced CVD (PECVD). Film stress can also be varied from compressive to tensile by varying plasma processing conditions [3]. Techniques such as PVD and CVD are unable to attain the step coverage, thickness control, and cross-wafer uniformities required for such an application; single-wafer ALD has been gradually replacing these techniques in high performance logic gate structures since the 45nm node [4]. By the 22nm node, all primary gate stack materials will be deposited by ALD processes. The advent of three-dimensional architectures such as FinFETs, and the film conformality requirements that come therewith, will ensure that ALD will be the deposition technique of choice for the next several generations of advanced logic gate stack structures.

Batch tools for thicker films/high-aspect ratios

When film thicknesses are less than one hundred angstroms thick, ALD process times are typically no longer than a few minutes. Single-wafer tools then give acceptable throughput performance and short turn-around times. However, for some applications, the process times are inevitably longer. This can occur when thicker layers are required or when films have to be deposited in high-aspect ratio structures. Substrates with high-aspect ratio structures have a larger surface area than planar wafers and usually require a higher precursor dose and subsequently need longer pulses and purge times to enable effective gas transport into and out of the structures. Also, some ALD chemistries can have lower growth rates than others and some processes may require relatively long pulses to ensure complete surface reactions to achieve the desired film quality.

The throughput and cost-of-ownership (COO) performance of batch ALD approaches with ~100 wafer loads in one reactor can be substantially better than that of single-wafer systems. Pulse and purge times have to be longer in batch reactors because the volume of the reactor is larger and the gas transport depends more on diffusion (rather than forced convection) than in single-wafer systems. However, the total increase in cycle time is smaller than a factor of 100, more on the order of 10-50. Process optimization in a batch system is more complex than in a single-wafer system but for ALD chemistries that result in self-limiting ALD surface reactions, relatively good uniformities and step coverage can still be achieved. The precursor flow and total dose that is delivered to the batch reactor is typically much larger than in single-wafer applications, especially when high aspect ratio device structures are involved. However, techniques such as direct liquid injection (DLI) can be used to mitigate precursor dose delivery issues as long as the vapor pressure of the precursor is sufficiently high. Low vapor pressure precursors (which also can be solid powders) are more troublesome in batch equipment due to risk of condensation and decomposition associated with the high residence time in the reactors.

ALD titanium nitride using titanium chloride and ammonia meet all the criteria required to make batch processing an attractive option. Titanium nitride films are used in several applications in logic devices: electrodes for replacement gates, electrodes for embedded DRAM devices, barrier films in tungsten contacts, and through- silicon-via (TSV) structures. Required film thicknesses are in the range of 20−150Å.

Figure 2. Step coverage of batch pulsed CVD TiN film in 32:1 trenches.

The process can be run in two modes: a strict ALD mode where completely separated titanium chloride and ammonia pulses are used (resulting in a growth rate of ~0.3Å/cycle), but also in a second mode in which one of the two pulses is actually a CVD pulse. In the pulsed CVD mode, a higher (3-5x) growth rate can be achieved. Batch reactors are able to run ALD-like processes such as pulsed CVD, with good results. The resulting film resistivity is a function of deposition temperature. In the ALD mode, one can use about 100°C lower deposition temperature to achieve the same resistivity as films deposited by the pulsed CVD mode [5]. Figure 2 shows an example of the deposition of a thicker layer of titanium nitride in a high aspect ratio structure. A highly conformal film is achieved, with step coverage of better than 95%, using the ALD-like pulsed CVD process mode in a batch reactor. Batch reactors can run at a throughput of greater than 30wph per reactor for 10nm films. These results demonstrate that batch-type ALD reactors are an attractive tool choice for some of the new ALD applications in future logic devices.

Mini-batch or multi-wafer ALD systems

When deposition of thicker films using complex precursors is required at reasonable throughputs and with short turn around times, a mini-batch or multi-single-wafer ALD system is the most appropriate. Mini-batch and multi-single-wafer ALD reactors meld the flexibility of single-wafer systems with the productivity of batch reactors. Typically, a mini-batch reactor processes four to five wafers together in one reactor and a multi-single-wafer system processes four to five wafers in individual reactors packaged in one module. These types of reactors can result in improved COO when compared to single-wafer systems as they occupy less floor space and rely on fewer, shared sub-systems. For example, gas panels, RF systems, and pumps can be combined for use on a mini-batch system whereas single-wafer tools would require multiple individual sub-systems. In addition, creative design of mini-batch systems can allow the use of direct plasma to enable plasma-enhanced ALD processes.

Spacer-defined double-patterning (SDDP) will likely be introduced to manufacture highly scaled lines and spacers for 22nm logic devices. In this technology, a conformal, ALD silicon oxide (SiO2) film is deposited directly on photoresist at extremely low temperatures. This is followed by an anisotropic etch-back process that results in the formation of SiO2 spacers that act as hard masks with smaller pitches. For this application, a mini-batch (multi-single-wafer) system is useful - ensuring high throughput in a system that can utilize direct plasma to enable deposition at near room temperatures. PEALD SiO2 using a mini-batch system results in conformal deposition at low-temperatures (<100°C) with within-wafer and wafer-to-wafer uniformity < 1%, three sigma. Throughputs can be achieved at >45wph per reactor at 20nm film thickness with high equipment utilization due to in situ remote plasma cleaning capability.

One cycle of PEALD SiO2 consists of 3 steps: chemisorption of an aminosilane precursor on the substrate, purging the precursor by inert gas flow, and plasma-assisted surface reaction of chemisorbed precursor with reactant gas. The RF-based plasma pulse is <400ms in length. Growth per cycle (GPC) of PEALD SiO2 increases with decreasing deposition temperature [6]. This GPC temperature dependence indicates the ALD reaction is limited by the desorption rate of the physisorbed precursor, which increases with increasing deposition temperature. Because this is an ALD process, film thickness is proportional to cycle number and thickness can be precisely controlled. These PEALD films have been confirmed to not cause plasma damage to the underlying substrate/films as the RF power during the deposition process is much smaller (<50W) than that of conventional PECVD.

Figure 3. PEALD SiO2 deposition on resist at 50ºC.

As shown in Fig. 3a, 300Å of a conformal SiO2 film can be deposited directly on resist at 50°C without any damage. Furthermore, in situ treatments can be used to widen the space between lines and/or reform the resist shape. Figure 3b shows an example of in situ treatment before SiO2 deposition. In this case, the resist is slimmed isotropically by ~65Å. Within wafer uniformity of the treatment process is typically <2%, 3σ. This is a good example showing the process flexibility gained by using a mini-batch system, while sustaining the high throughputs required for manufacturing.

Conclusion

Overcoming the initial barriers to adoption has required the creation of several toolset configurations to address the unique issues in specific applications. Single-wafer, batch and mini-batch ALD solutions are available, each with thermal and plasma enhanced capabilities, and selection of the appropriate manufacturing toolset is as critical to eventual technology adoption as the process itself. In very cost sensitive markets such as memories, cost-of-ownership (COO) will be a main driver for equipment selection. In foundry or other logic applications, equipment choice is more a mix between COO, turn-around time and process performance considerations and choices of equipment type have to be made with careful regard to the specific application.

References

1. C. Goodman, et al., "Atomic Layer Epitaxy," Jour. of Appl. Physics, R65-R81, 1986.

2. D. Triyoso, et al., "Physical and Electrical Characteristics of Atomic-Layer-Deposited Hafnium Oxide Formed Using Hafnium Tetrachloride and Tetrakis(ethylmethylaminohafnium)," Jour. of Appl. Physics, Vol. 97, 124107, 2005.

3. H. P. W. Hey et. al., "Ion Bombardment: A Determining Factor in Plasma CVD," Solid State Technology, pp. 139-144, April, 1990.

4 . L. Niinistö, et. al., "Advanced Electronic and Optoelectronic Materials by Atomic Layer Deposition: An Overview with Special Emphasis on Recent Progress in Processing of High-k Dielectrics and Other Oxide Materials," Physica Status Solidi (a), 201, p. 1443–1452, 2004

5. E. Granneman, et al., Batch ALD: Characteristics, Comparison with Single-wafer ALD, and Examples, Surface and Coatings Technology, Vol. 201, p. 8899 – 8907, 2007.

6 . A. Kobayashi, et al., Temperature Dependence of GPC with PEALD-SiO," Proc. 10th Inter. Conf. on Atomic Layer Deposition, p. 31, 2010.

Biographies

Mohith Verghese earned a BS in chemical engineering from the U. of Texas at Austin and a MS in chemical engineering from the U. of Arizona. He is technical product manager of ALD technologies at ASM America, Phoenix, AZ, USA; ph: +1-602-470-2736, email:  mohith.verghese@asm.com

Jan Willem Maes received his PhD in applied physics from Delft U. of Technology and works at ASM Belgium on ALD and EPI process application development projects.

Nobuyoshi Kobayashi earned a BS, a MS, and a PhD in solid state physics from the U. of Tokyo. He is director of PECVD and PEALD technologies at ASM Japan, Tama in Tokyo.

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