Dielectric materials evolve to meet the challenges of wafer-level packaging
The role of dielectric materials in wafer-level packaging has evolved to meet the changing requirements of new and more advanced chip designs and packaging technologies. These advances in dielectric materials have paralleled changes to both the integrated circuits and their corresponding packaging methods. As consumers demand more functionality in smaller and lighter devices, more and more sophisticated ICs are being designed. This in turn has challenged packaging houses to come up with methods to connect these higher density ICs with their devices. New packaging methods are leading dielectric materials suppliers to adjust their chemistries to provide innovative products.
Toshiaki Itabashi, DuPont Semiconductor Fabrication Materials, Kanagawa, Japan
Polyimide dielectric materials have traditionally served as stress-buffer passivation layers (SBPs) on ICs that were wire-bonded to lead frames and encased in mold compound . Two failure modes of this packaging scheme were stress-induced die cracking and molding compound delamination. Die cracking results from the stresses induced by the mold compound due to the mismatch between the coefficient of thermal expansion (CTE) of the molding compound and the silicon chip. If the mold compound delaminates from the surface of the IC, a void is created where moisture can permeate, leading to corrosion.
To alleviate these issues, a polymeric, secondary passivation layer is applied over the primary silicon nitride passivation layer. This secondary layer cushions the device from the molding compound stresses and provides better adhesion. Polyimide-based materials have historically been used for SBP layers due to relatively low stress levels, proven chemical resistance, and good thermal and mechanical stability.
Redistribution layers in wafer-level packaging
As the evolution of portable electronic devices progressed, all the components in the device had to become smaller, lighter, and higher-performing. Flip-chip packaging moved contacts from the bulky molded lead frame to solder balls on the surface of the chip. The IC was then simply flipped over and reflow soldered to the substrate in a much more compact manner .
|Figure 1. In redistribution layer packaging, the polyimide dielectric layers – shown as PI(1) and PI(2) – are used to create the redistributed contact pads on the top surface of a chip.|
To accomplish this, the wire bond pads located at the edges of the chip had to be re-routed or redistributed across the surface of the chip. There are several methods for this, but most involve adding a dielectric layer to the surface of the IC, selectively removing portions of the film to expose the original bond pads. On top of this dielectric layer are plated copper traces from the bond pads to the sites of the solder balls (Fig. 1). Often a second dielectric layer is put on to cover the copper traces. Solder is either screen-printed or placed and reflowed to form the solder ball grid on the top surface of the chip .
Polyimide materials were quickly adopted in this new application. New polyimide chemistries evolved that retained their good chemical resistance, thermal and mechanical properties but, in addition, were copper compatible, adhered well and had broad processing latitude. The most widely used materials are solvent-developed, meaning an organic solvent is used to develop away the polymer in the areas it was not needed. With the focus on more environmental stewardship, many manufacturing operations were looking to reduce their use of organic solvents.
This desire to reduce the use of organic solvents led to the introduction of polybenzoxazole (PBO)-based dielectric materials. These were processed with an aqueous based developer, in fact, the same one used for photoresists. PBOs have similar properties to polyimides, but while they cannot hold up to high processing temperatures compared to polyimides, they tended to fully cure at lower temperatures and exhibited properties that helped RDL-packaged chips survive drop tests of handheld devices.
Taking fan out packaging beyond redistribution
As the demand for more and more features on electronic devices grows, the ICs have evolved into higher and higher functionality with more outputs. The ability to successfully redistribute a new layer of contacts over the surface of the chip reaches its practical limit with I/O counts above 200 contacts, due to the limited area available for placement of solder balls.
To increase the surface area available for solder ball placement, the chip can be embedded in a slightly larger epoxy frame, creating a technology called embedded wafer-level ball grid array (eWLB) . In this case, the redistributed contacts cannot only be positioned over the chip but "fanned out" to the edges of the epoxy frame. The redistribution is accomplished in the same manner as before. A layer of dielectric material is applied to fill any gaps and smooth the surface across the chip and epoxy frame. The copper traces are applied next and they fan out across the entire surface area. A final dielectric layer covers the traces except where the solder balls will be placed.
But while the redistribution process is similar, the new packaging scheme requires another evolution in dielectric materials. Because the frame is epoxy, it cannot survive the processing temperatures needed to cure polyimides or most PBO materials. Higher functioning ICs may incorporate embedded memory in the chip's design. This circuitry is very sensitive to process temperatures and survivability drops dramatically with increase in temperatures. In addition, advanced technology node wafers will use lower-k dielectric materials, which are themselves temperature sensitive.
|Figure 2. Polybenzoxazole (PBO) dielectric materials – shown as PI(1) and PI(2) – are used in fan-out packaging methods, because their lower curing temperature is compatible with epoxy packaging materials.|
Once again, the dielectric materials have had to keep up with the demands of the packaging technology, which is in turn, responding to the needs of the device designers. By modifying a PBO formulation, a new material has been developed that cures as low as 200°C. The trade-off is a reduction in the mechanical and chemical resistance properties of the dielectric, but work is underway to find a suite of process chemicals that will allow a robust process for volume manufacturing (Fig. 2).
What's ahead for dielectric materials?
As the semiconductor industry drives toward higher and higher data transfer speeds, 2.5D and 3D packaging schemes are being developed. In 2.5D packaging silicon interposers with through vias provide the interconnectivity. In pure 3D, the dies themselves have the vias and are stacked one upon the other. Both of these packaging structures use very thin (<50 micron) active dies that will require redistribution layers, adhesives and underfill materials. All these materials may require different mechanical, thermal and chemical properties than the incumbent products of today.
Work is underway developing these materials including: 1) the use of polyimide material as a temporary adhesive for bonding thinned wafers to a carrier wafer for processing; 2) a polyimide material as a permanent adhesive for bonding of wafer/chip stacks; 3) the use of a PBO dielectric material to bond backside circuitry onto thinned wafers (where the lower temperature curing is needed so as not to damage structures on the wafer); and 4) new over molding compounds for semiconductor packaging materials to help prevent die shift in fan out packaging.
According to John Hunt of ASE, as WLCSP packages have increased in I/O counts to greater than 300, the current polymer dielectrics do not provide enough stress buffering to provide consistent reliability performance through drop and temperature cycle testing. New polymers that are capable of buffering the die structures from the package stresses will be required, and once again materials will continue to evolve to meet the requirements of advances in packaging.
A special thanks to John Hunt of ASE, Doug Heden of HD Microsystems and to Anthony Rardin of DuPont Wafer Level Packaging Solutions, for their important contributions to this article. HD Microsystems is a trademark of HD Microsystems.
1. J.L. Wyant, C.C. Schuckert, "Qualification of Spin Apply, Photodefinable Polymer for Packaging of Automotive Circuits," Solid State Technology, Nov. 2000.
2. M. Hiro, C.C. Schuckert, "Thicker Film Photodefinable Polyimides," Advanced Packaging, Oct. 2000.
3. G. A. Riley, Flipchips.com Tutorial #72 – Redistribution Layers.
4. S.W. Yoon, et al., "Next-Generation Embedded Wafer-Level BGA (eWLB) Technology," Chip Scale Review, July-August 2010.
Toshiaki Itabashi (Toshi) received his baccalaureate from Nihon U. and is Application Development Leader, WLP global at DuPont Semiconductor Fabrication Materials, DuPont Electronics Center, KSP R&D,D342,3-2-1, Sakado,Takatsu-ku, Kawasaki, Kanagawa, 213-0012, Japan; ph.: +81-44-850-8277; email Toshiaki.Itabashi@jpn.dupont.com.