Planar fully depleted SOI: the technological solution against variability
It is well known that the planar fully depleted silicon-on-insulator (SOI) (FDSOI) architecture is a technological booster of the CMOS performance, thanks to better electrostatics than devices on bulk. This article shows that it also greatly improves the variability of the electrical characteristics, thanks to an undoped channel. This leads to good matching performance.
F. Andrieu, O. Weber, J. Mazurier, O. Faynot, CEA-Leti, Grenoble, France
Fig. 1. The thickness of the buried oxide (BOX) for our FDSOI devices is 145nm, 25nm or 10nm. The film thickness is ~7nm. Threshold voltages are adjusted by the gate-first work functions (targeted work functions are only ±150mV around the midgap). The technological details of the process integration, as well as the main recent results, are given in references [1-3].
Figure 1. TEM image of a transistor on FDSOI with a Tbox=145nm thick Buried Oxide (BOX), L=30nm gate length and a mesa isolation.
This technology mainly addresses low-power applications, even if it is compatible with wafer-level or process-induced stressors for high performance . In particular, it yields a 22% energy-consumption reduction at a given speed for ring oscillators at the 45nm node compared to the same circuit on bulk . Other details about this technology, its performance and capabilities can be found in reference . Finally, one of the main advantages of this technology is the low variability obtained.
The variability issue and solution
For the 20nm CMOS technology node and below, the variability of the electrical characteristics is becoming as important as the electrical performances themselves. Especially, the threshold-voltage (VT) variability is a key for the stability of the SRAMs, which represent a huge proportion of an integrated circuit area. Indeed, improving the VT variability directly lowers the SRAM dispersions and, in turn, the minimal supply voltage (VDDmin) of the memory blocks.
Historically, for CMOS on bulk, the dopant concentration in the channel of the transistors (Ndop) increases node after node (by a factor k) when the device dimensions (the active width W, the gate length L and the effective gate oxide thickness in the inversion regime Tinv) are scaled by a factor 1/k . This scaling law is only based on electrostatic considerations and not on variability considerations. However, for sub-65nm CMOS, one of the most important showstoppers is the VT variability, which is no longer negligible. Actually, the VT standard deviation varies
as when it is limited by the random dopant fluctuation (RDF). This means that the intrinsic variability of CMOS on bulk theoretically degrades node after node (by a factor k1/4). For the moment, the solution used by IC manufacturers to keep the VT standard deviation of the nominal device quite constant with the scaling is not to play on the channel doping but to slow down the (gate length L and supply voltage Vdd) scaling or to counterbalance by electrostatic improvements (Tinv lowering or junction optimizations) or by design solutions. However, for the 20nm node and below, considerations on the dynamic power consumption require a Vdd scaling and electrostatic/performance considerations already require a challenging Tinv.
In this context, we propose another paradigm based on the planar FDSOI with undoped channels. In this architecture, the scaling is not governed by the channel doping but rather by the film thickness below the gate (Tsi) . This enables an excellent electrostatic behavior (better than CMOS on bulk) without any intentional channel doping. Such devices thus resist the root cause of the RDF (i.e., the channel doping) and simultaneously improve the electrostatics. Indeed, FDSOI is really an electrostatic booster, similar to the Tinv reduction. This enables a lower sensibility of the VT vs. the gate length (L) and, consequently, an additional reduction of the second major source of variability in bulk devices, namely line edge roughness (LER). This latter indeed influences the VT standard deviation following:
(σL being the effective channel-length fluctuation). Finally, the two major sources of variability (RDF and LER) are strongly or even completely reduced thanks to the FDSOI architecture. This is evidenced by Fig. 2, which shows that the LER-induced fluctuation (in blue and red) can be neglected compared to the "surface" sources of variability attributed to the gate stack (charge or gate work-function fluctuations), even down to L= 25nm.
|Figure 2. Pelgrom plot with VT measured in the linear and in the saturation regime for TSi=8nm.|
Variability performance of FDSOI devices
Thanks to the undoped channel, we highlight a low variability, as evidenced by Fig. 3 and . It is worth noting that this performance was reproduced on FDSOI by another group . It exceeds the one obtained on bulk devices or on FinFETs (not shown here). Indeed, for 3D devices and, contrarily, as for planar FDSOI architectures, VT strongly depends on W. Thus, there is an additional contribution induced by the fluctuation of the fin width (Wfin), which is the smallest dimension of FinFETs:
For planar FDSOI, however, SOI thickness (TSi) is the smallest dimension. However, Tsi is not defined by the lithography but rather by the Smart Cut process. This guaranties a very good process uniformity of Tsi. We demonstrated that the Tsi uniformity now reached by SOI wafer manufacturers (Tsi range around 10Å ) is in the specifications for the 20nm node.
|Figure 3. Benchmark of the matching factor vs. the gate length for bulk or FDSOI devices [7,8].|
We checked that this outstanding variability performance is conserved in the following cases:
- With the introduction of mechanical stressors 
- With either 145nm thick or 10nm thin BOX 
- With or without back-biasing the substrate below the BOX
Finally, it must be stressed that the aforementioned local variability (namely the matching or the statistical variability) is the major part of the total variability over the whole wafer. The other part is the systematic variability. With systematic variability only, the electrical performances of all the devices on all the dies would be well known, modeled and mastered (by the process and the design). With local variability, the performances are not known; only the random distribution of performances is known. FDSOI architecture is the technological solution to minimize this uncertainty in order to proceed with the CMOS scaling.
To summarize, FDSOI technology exhibits outstanding variability results, thanks to the use of an undoped channel, and to the good control of silicon film thickness already reached today on commercial SOI wafers. Therefore, variability performance is much better than for planar bulk technology, for which variability is governed by random dopant fluctuation within the channel, and much than for FinFETs, for which the fin width fluctuation is the limiting parameter. This constitutes a key advantage of FDSOI technology, which offers today the only viable solution for scaling the supply voltage; it therefore keeps the circuit power consumption under control for the sub-20nm technology generations.
SmartCut is a trademark of Soitec.
- C. Fenouillet-Beranger, P. Perreau, L. Pham-Nguyen, S. Denorme, F. Andrieu, L. Tosti, et al., "Hybrid FDSOI/Bulk high-k/Metal Gate Platform for Low Power (LP) Multimedia Technology," IEDM Tech Dig., 2009.
- F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J-P. Noel, C. Fenouillet-Béranger, et al., "Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond," accepted by the Symposium of VLSI Technology, 2010.
- F. Andrieu, O. Weber, S. Baudot, C. Fenouillet-Béranger, O. Rozeau, J. Mazurier, et al., "Fully Depleted Silicon-On-Insulator with Back Bias and Strain for Low-Power and High-Performance Applications," invited talk at IEEE ICICDT, Grenoble, 2010.
- SOI Consortium website: http://www.soiconsortium.org/pdf/SOIconsortium_FDSOI_QA.pdf
- R.H. Dennard, F.H. Gaensslen, H-N. Yu, V.L. Rideout, E. Bassous, A.R. Leblanc, "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," IEEE of Solid State Circuits, 9, 5, p. 256, 1974.
- V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, et al., "Strained FDSOI CMOS Technology Scalability down to 2.5nm Film Thickness and 18nm Gate Length with a TiN/HfO2 Gate Stack," IEDM Tech Dig., pp. 61-4, 2007.
- O. Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet, F. Allain, P. Scheiblin, et al., "High Immunity to Threshold Voltage Variability in Undoped Ultra-thin FDSOI MOSFETs and Its Physical Understanding," IEDM Tech Dig., pp. 641-4, 2008.
- K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, D. Shahrjerdi, et al., "Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications," IEDM Tech Dig., p. 49, 2009.
- J. Mazurier, O. Weber, F. Andrieu, F. Allain, C. Tabone, A. Toffoli, et al., "High Performance and Low Variability Fully-Depleted Strained-SOI MOSFETs", accepted for the IEEE SOI Conf., 2010.
Francois Andrieu received his MSc and his PhD in applied physics from the National Institute of Polytechnic Grenoble (INPG), and is manager of the FDSOI CMOS device project at CEA-Leti, 17 rue des Martyrs, 38 054 Grenoble Cedex 9, France; e-mail : email@example.com; tel : +33 (0) 4 38 78 27 52.
Olivier Weber received his MSc and his PhD in applied physics from National Institute of Applied Science in Lyon (INSA) and is a research engineer at CEA-Leti.
Jerome Mazurier received his MSc in applied sciences and is currently a PhD candidate, working on FDSOI variability at CEA-Leti.
Olivier Faynot is senior scientist and manager of the Innovative Device Laboratory at CEA-Leti.