Issue



Cost-effective advanced copper metallization using ECPR


10/05/2010







Executive Overview

A new methodology is required to enable the cost-effective deposition of thick, tightly-spaced copper structures. In this review, we introduce the technology of electrochemical pattern replication (ECPR). ECPR enables the aligned deposition of 3-10µm thick copper with ≥2µm spacing between features. The ECPR process eliminates the need for copper CMP and photolithography equipment and the related consumable slurry materials, photolithography resists and solvents. This ECPR process delivers damascene-like feature control at <50% of the cost compared to dual damascene targeting analog and RF devices, IPDs, redistribution layers (RDL) and advanced packaging markets.

M. Thompson, P. Möller, M Fredenberg, D. Hays, W. Van den Hoek, D. Carl, Replisaurus, Kista, Sweden

Copper has replaced aluminum as the standard transistor interconnect metallization material of choice for advanced logic devices (microprocessors, ASICS) and memories. Copper is also increasingly utilized in power management devices, CMOS imagers, and integrated passive devices (IPDs) (inductors, resistors and capacitors) to improve both the performance (speed) and the energy efficiency of these devices enabling longer battery life in mobile consumer electronics products. Dual-damascene processing has been widely adopted as the integration scheme for copper metallization of advanced logic devices in metal layers one through ten, but due to its high cost per layer ($75-$200) and the requirement to use chemical mechanical polishing (CMP) to remove excess copper from non-patterned areas, dual-damascene is not viewed as a viable alternative for the final levels of thick (3-10µm) metal used as the bridge layers to the package. To meet this new challenge, we have developed a technology called electrochemical pattern replication (ECPR).

Metallization

The evolution of dual-damascene. Historically, transistor-level interconnect has been based on a subtractive aluminum process due to its low cost and ease of processing. However, as the number of metal levels began to increase in the mid-1990s, semiconductor manufacturers were forced to evaluate alternatives due to device power and speed requirements that could not be met using the subtractive aluminum process. Copper became the natural choice due its low resistance and high current carrying capability. However, copper cannot be easily reactive ion etched like aluminum, so new techniques had to be developed using blanket copper deposition into dielectric patterns followed by CMP – the dual-damascene process. Dual-damascene was chosen first by IBM [1], then increasingly across the industry as the copper metallization method of choice.

Dual-damascene typically requires a minimum of eighteen process steps to complete a single layer of interconnect. These steps include multiple dielectric and photoresist depositions, dielectric etching, resist exposure and develop, barrier metal deposition, seed layer deposition, electrochemical plating of copper and chemical mechanical polishing of both copper and copper diffusion barrier layers.

To achieve further device speed and performance advantages, dual damascene processing evolved to incorporate advanced low dielectric constant insulating materials (low-k) [2]. These materials required further evolution of the CMP, lithography and etching processes, thus resulting in added expense and integration risk compared to the subtractive aluminum processes dual-damascene replaced. Designers of advanced logic and memory devices have found these changes necessary to achieve the electrical performance demanded by end users. The economics of dual damascene remain costly and sometimes cycle-time prohibitive for the final thick layers of metal for ASIC, RF devices and logic top layer interconnects.

Through-mask plating. Through-mask plating is another production approach to producing copper patterns without requiring a copper pattern-etch process. This method has been widely utilized in the advanced semiconductor packaging arena for the redistribution layer (RDL) process.

Through-mask plating typically requires twelve steps. The first four steps are spin-on of a photo sensitive dielectric layer, exposure and develop of this layer, followed by a descum process. The remaining eight steps of the through-mask plating process sequence consist of seed deposition, the spin-on, exposure, develop of the photoresist, descum, plating, resist strip, and finally, seed etch.

Through-mask plating, while significantly lower in cost than dual-damascene, is limited in its ability to produce thick, closely-spaced features without re-entrant metal sidewalls. In addition, the minimum resolvable space achieved with this technology for thick (>5µm) lines is on the order of 10µm, thus limiting the number of interconnects that can be routed between the pads in an RDL layer. These limitations, which are beginning to impact advanced logic packaging, have created a market need for a new methodology that will provide simple, cost-effective processing for thick, finely-spaced copper metal features.

The future: ECPR. ECPR combines the precision and resolution of advanced lithography with the efficiency of electrochemical deposition into a single electrochemical metal printing step [3,4]. ECPR uniquely combines high resolution, dimensional accuracy, high metal deposition rates and low cost per layer, thereby bridging the gap between front-end of line and back-end of line metallization methodologies.

ECPR process flow

Compared to the eighteen process sequences for dual damascene and the twelve for through-plating, ECPR requires only seven steps. The first four, spin-on of a photo sensitive dielectric layer, exposure and develop of this layer, followed by a descum process, are identical to the through-mask plating sequence. The deposition of a barrier / seed layer on top of a patterned photoactive dielectric, the printing of the metal layer as the pattern is defined by the electrode (from this point forward to be known as the master) utilized during the printing of the metal and the final seed etch step. Note that the latter two are performed in the Integrated ECPR tool. The physics and electrochemistry of the ECPR plating process provides market-leading metal thickness uniformity within die and across the wafer by design, thus eliminating the need for post-metal deposition CMP.

Figure 1. ECPR process sequence.

ECPR's simplicity lies in the use of a patterned electrode (the master as defined above) which is pre-filled with copper. The pre-fill is performed using conventional electroplating. The copper that is pre-filled into the master is then partially transferred (printed) onto the target wafer during the ECPR process (Fig. 1). This pre-fill is done in parallel with other wafer processing activities in an integrated ECPR production tool. The master is reusable unlike the temporary photoresist template or mandrel utilized in through-mask plating.

As no lithography is required for the metal definition portion of the ECPR process, the investment in spin coaters, exposure and develop tools and resist materials (including solvents typically used to process the resist) is eliminated, further reducing operational costs and total capital investment. Typically, eight different tools are required in through-mask plating: a seed PVD tool, a resist coater, an exposure tool, a resist developer track, a descum tool, an electroplating tool, a resist strip tool and a seed etch tool. A single ECPR tool can replace seven of these eight tools. A PVD seed tool and an ECPR tool combined deliver an entire metallization line used to create one layer of patterned copper on the wafer. Integration of the pre-fill, master cleaning, and seed layer etch into a single ECPR tool also eliminates additional wafer handling and queuing between individual tools, thereby reducing both fab cycle time and cost.

ECPR master: a unique pattern transfer element

The master is patterned using advanced lithography tools and micro-electrical-mechanical systems (MEMS)-like etching processes found in standard CMOS fabs. The base material for a master is silicon substrate sized for the dimension of the target product wafer. Advanced lithography techniques are used to define the features on the master. These sub-micron resolution features are then repeatedly transferred to high resolution printed copper patterns without the need for subsequent lithography.

During the ECPR process, the master is brought into contact with the target wafer creating micro plating-cells across the target wafer surface. These micro cells, between the electrode embedded in the master and the target wafer, significantly reduce the volume of electrolytic solution required to transfer ("plate") the copper features from the master to the target wafer compared to traditional through-mask plating.

Sidewall performance

Advanced MEMS and CMOS process technology yields near-vertical sidewalls of the features in the master, which translate into near-vertical sidewalls of the copper patterns on the target wafer. This eliminates one of the problems commonly found with through-mask plating, i.e. the tendency for the exposed and developed resist patterns to display curved sidewalls as the thickness increases with decreasing line spacing. ECPR can produce features with aspect ratios of 2:1 or greater where line spacing is ≥3µm, and line thickness is ≥5µm. These results have proven to be very difficult to achieve with through-mask plating. Figure 2 illustrates the capabilities of ECPR to produce these thick, fine-pitch metal structures. These types of structures are increasingly important to the implementation of integrated passives on advanced RF devices for mobile electronics such as those which integrate WLAN, Bluetooth and GPS functionality into a single die.

Figure 2. Copper coil structure: 10μm-thick, 5μm spacing, 20μm-wide.

Printed copper within die uniformity by design

The variability of line width and spacing causes thickness non-uniformity problems for through-mask plating due to the difference in localized electrical field densities caused by the different opening sizes in the plating template. Areas with low pattern density experience higher current density, resulting in accelerated localized plating rates and therefore thicker deposits. Areas with high pattern density experience lower plating rates (due to much lower current densities), and therefore produce slower plating rates and proportionally thinner deposits. The combination of the two creates non-uniformities in the resulting copper thickness, which is problematic for IPDs as well as for power devices that are designed to maximize the thickness of the copper deposited in order to reduce series resistance.

Figure 3. As-plated copper thickness uniformity for ECPR and through-mask plating using the same mask pattern.

Micro cells are, by design, pattern insensitive as they isolate each and every feature to be printed into a unique small plating cell. The micro cell for one line, for example, is electrochemically isolated from the next large pad or other feature – thus eliminating any transport effects or current crowding that would lead to copper thickness variation as a function of feature size. This leads to a fundamental improvement in as-plated copper thickness uniformity. Figure 3 shows a side-by-side comparison on the same single level copper metal process monitor electric test structure with a wide range of line widths, line spacing and pattern density. ECPR plated copper thickness uniformity half-range for this vehicle was 7% within a die; through-mask plating yielded a thickness uniformity half-range of 42%.

This improved uniformity, together with the vertical sidewalls of printed metal patterns, help to reduce the (design – produce – measure – redesign) cycle times required today for sophisticated RF devices. ECPR's highly predictable process offers "What you draw in CAD is what you get on your wafer," and will require fewer simulations and/or evaluation cycles during pre-production verification. In addition, a higher percentage of top-performing die should be realized from each wafer, reducing the distribution being realized at wafer-probe during the binning process.

This "by design" process result for ECPR is in contrast to both dual-damascene and through-mask plating both of which have significant challenges dealing with a wide variety of line widths and line spaces on the same chip. In the case of dual-damascene, the polishing rate is faster where there are dense narrow metal features and slower where there are isolated narrow metal features, so dishing and/or cupping of the polished surface can occur. The ECPR process eliminates the considerable cost and time required to integrate additional dummy (also known as "slotting") features into the layout of the dual-damascene structures that older processes required to minimize the CMP dishing effects.

ECPR printing with sub-micron alignment

The final component of the integrated ECPR tool is its ability to print copper lines aligned with sub-micron overlay tolerances to previously deposited layers. This is achieved by the use of a proprietary inter-substrate alignment scheme, based on high resolution measurement optics, planar high-precision wafer stage assemblies and software algorithms, and is shown schematically in Fig. 4. The ECPR process chamber and fluidic management system are integrated in a compartmentalized module that confines the corrosive electrochemical processes away from sensitive high precision mechanical and electrical sub-systems. The system performs aligned metal printing in a dry-in/dry-out wafer sequence.

Figure 4. Schematic of the ECPR alignment system.

The alignment results (Fig. 5) have been achieved by using transparent calibration wafers to first find the correction factors for the tool, then by continuous aligned wafer print cycling, measuring alignment errors between the two wafers in superimposed position after each transfer. Proof of concept measurements confirm < 150nm alignment errors during 35 consecutive cycles, measured on wafer center line, left and right side, 15mm from the edge on 200mm wafers.

Figure 5. Measured alignment errors, left (L) and right (R) side of a 200mm glass wafer.

Conclusion

The need for copper metallization is rapidly expanding beyond application in high-end logic devices and advanced memories into mainstream applications such as analog circuits, power management, integrated passive devices and advanced packaging applications. Metal layers in excess of 5µm thick are becoming increasingly common, with 8μm (or more) thick layers being found in everything from Intel's 45nm process [5] to ESD devices from OnSemiconductor. Consumers continue to press for lower cost, next-generation electronic products that improve their lives and entertain and amuse their families. ECPR's advantages of low cost, fine pitch, >2:1 aspect ratio plating of near vertical sidewall copper metal features without advanced lithography and excellent uniformity will prove to be very attractive for both front-end of line and back-end of line metallization processes.

Acknowledgments

The authors wish to thank our collaborators at CEA Leti in Grenoble, France, the Fraunhofer Institutes in Munich and Berlin, Germany and the KTH Royal Institute in Stockholm, Sweden for their support and the use of their facilities.

References

  1. D. Edelstein et al., "Full copper wiring in a sub-0.25 µm CMOS ULSI technology," Proc. IEEE-IEDM, 97, 773 (1997).
  2. A. Singh, G. Dixit, R.S. List, S.W. Russell, A.R.K. Ralston, D. Aldrich, et al., "Overview of Process Integration Issues for Low K dielectrics," Electrochemical Society Proceeding, 97-8, 102 (1997).
  3. P. Möller, M. Fredenberg, M. Dainese, C. Aronsson, "Metal Printing of Copper Interconnects Down to 500nm using ECPR – Electro Chemical Pattern Replication," Microelectronic Eng. 83 1410–1413, (2006).
  4. M. Fredenberg, P. Möller, M. Töpper, "Novel Multi-layer Wiring Build-up using Electrochemical Pattern Replication (ECPR)," IEEE ECTC Proc., 585 (2009).
  5. P. Moon, et al., "Process and electrical results for the on-die interconnect stack for Intel's 45 nm process generation," Intel Tech. Jour., vol. 12, issue 2, 87-92, (2008).

Mike Thompson, Chief Technology Officer at Replisaurus Technologies, Inc., 7 parvis Louis Neel – BP 50, 38040 Grenoble, CEDEX 9, France; ph.: +33 438 49 1304; email mt@replisaurus.com 

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