3D activity at SEMICON West
At the TechXspot session on "Bridging the Gap," Steve Bezuk of Qualcomm shared his views on mobile device packaging. For first generation heterogeneous stacking Bezuk thinks that current design tools will suffice till the full design suited capable of full chip reconfiguration are available. No unique thermal issues have come up so far vs. what is normally seen in 2D packaging. Bezuk indicates that Qualcomm will be going with vias-middle through-silicon vias (TSV). Detailed Qualcomm cost models are showing that the cost adder for 3D at 45nm and below should be ~10%.
At Suss Microtec's "3D IC Bonding and Thinned Wafer Handling Workshop," Calvin Cheung, VP of engineering for ASE, indicated that consumer markets are now driving, and will continue to drive, 3D IC in ASE. His company is a strong supporter of interposers for mechanical integrity reasons. "We currently need an interposer to bond 28nm low-k die," he said. "Right now it is impossible to stack these mechanically unstable materials into a reliable 3D stack in any other way." During a follow-up panel session, Cheung indicated that TSMC has all but announced that interposers will be used in upcoming 3D product introductions, and that ASE will be ready.
Robert Lanzone, VP of new technology development for Amkor, indicated that the company has backed off its focus on backside TSV fabrication, which he feels is well under control, and is now focusing heavily on the unit operations required to handle TSV middle wafers which they expect from the foundries soon. Below 40µm pitch, Amkor will move from Cu/Sn eutectic bonding to some form of Cu-Cu direct bonding, he indicated. Yu-Hua Chen, deputy division director of ITRI, announced the group expects its 300mm 3D line to be qualified by 4Q10. A team of >150 professionals are now fully engaged in 3D design, build, and test.
Fresh off a cash infusion by the Panasonic Ventures Group, Alchimer held a workshop focusing on its TSV fill process. SS Lee, CEO of the Korean materials and equipment supplier Lenix, introduced the company's modular process equipment for running the Alchimer "fully wet" via fill process, and indicated that a 300mm process development line is now operational in Korea. Claudio Truzzi, CTO of Alchimer, presented cost-of-ownership (CoO) modeling showing that the wafer cost for the EMC-3D process is really >$250 vs. the ~$150 that the EMC-3D consortium has previously reported—indicating that "equipment depreciation alone is >$120/ wafer at 10K wafer starts/month." That's a challenge to which the EMC-3D is sure to respond!
Riko Radojcic, director of engineering at Qualcomm CDMA Technologies, defined design for 3D as "managing choices and managing chip-to-chip interactions". In the next 3-5 years, he sees 3D design flow as using existing EDA products—and echoing the remarks of his colleague Steve Bezuk, indicated that Qualcomm can "manage the current 3D design flow using current EDA products."
Markus Wimplinger, corporate technology and IP director for EV Group, sees "some but not all" of the company's customers being ready for 3D IC production in the 2011-2012 timeframe. The only 300mm 3D IC line in production today is STMicroelectronics' CMOS image sensor line, but he noted qualification is underway right now at several major customers and should be finished by 4Q10. He also sees interest in wafer-to-wafer bonding on the upswing again after bottoming out (vs. die-to-wafer) around 12 months ago.
Mark Allison, VP of strategic marketing for Verigy, indicated that some large customers are putting pressure on them for 3D solutions but that others "are still waiting to see further clarity in the 3D
infrastructure." Several 3D test "challenges" have been identified, such as probe size vs. TSV size and making sure the DFT pads (design-for-test) don't alter the electrical performance of the TSV due to added capacitance and inductance. The company is looking at putting test capability into proposed interposers.
Damo Srinivas, senior director of 3D applications for Novellus, sees the main advantage of their recently announced suite of tools for 3D and wafer-level packaging (WLP) as being "throughput," and therefore lower CoO. He claims that the company's Sabre plating system (originally developed for damascene processing) has been optimized for 3D and that its "grain distribution control" technology actually reduces "copper protrusion" CTE issues by 10×. — Dr. Phil Garrou, contributing editor
For more blogs from Phil Garrou, visit: www.electroiq.com/index/packaging/packaging-blogs/ap-blog-display/blogs/ap-blog.html