Etch pushes limits of physics and chemistry


Click to EnlargeRichard A. Gottscho,
Lam Research Corp., Fremont, CA, USA

At the forefront of etch technology today are several longstanding issues that create challenges for nearly every etch application, such as aspect-ratio-dependent etching and materials selectivity. Because etch is involved in forming the critical structures of every semiconductor device, resolving these issues is essential as the industry continues to scale to smaller dimensions. However, these challenges grow increasingly difficult as we face fundamental limits posed by the basic laws of physics and chemistry. To enable continued device shrinks, innovative workarounds and new solutions will be needed.

When some of these etching requirements are examined, the challenges are obvious. For example, the transport of reactive species is fundamentally dependent on feature dimensions; however, aspect-ratio-independent etching is desired because device layouts are typically comprised of different features with widely different dimensions. Yet, treating each feature separately is expensive. Another factor: it is often vital to stop etching within one atomic layer or risk, for example, degrading transistor performance. Essentially, infinite selectivity is demanded under conditions where etchant bombarding energies are many times greater than substrate binding energies.

Ideally, every millimeter of silicon would be used to make devices – zero edge exclusion. However, the edge of the wafer creates discontinuities electrically and chemically, requiring a delicate balancing act to achieve a quasi-uniform result. Furthermore, for maximum yield, it is vital to "kill" the "killer" defects, but at dimensions below 28nm, the sizes of killer defects are too small for modern metrology to detect.

Also challenging is the fact that as scaling costs increase in some areas, such as lithography, they must be reduced in others, and a prime target is the cost of consumables for etch. Ideally, etch systems would contain no consumable parts, but to date, no materials have been identified that neither etch (eroding away) or sputter (creating defects and contamination).

In spite of these fundamental limitations, progress is being made in a number of areas. For example, to deal with aspect-ratio-dependent etch rates and profiles, etch recipes make use of rapid changes in wafer temperature to minimize the effects of side-wall scattering and sticking. As these effects become more severe at smaller dimensions, however, circuit designs will also need to be altered and the number of mask levels increased. In moving toward zero edge exclusion, one strategy is careful control of temperature both at the wafer's edge and on components next to the wafer.

While we can't always measure particles that produce killer defects, we know how to manage their transport to and from the wafer. Particles become negatively charged in a plasma, but only when the plasma is extinguished can they fall onto the wafer and become micro-masks or killer defects. Therefore, it is imperative to run the plasma continuously, even while etching through a complicated film stack where all recipe parameters are changed for each layer. While continuous etching is more complex, it helps to maximize throughput and lower overall cost-of-ownership.

To address the growing trend of increasing recipe complexity, more independent control parameters are needed, and some success has been achieved simply by separating approaches for meeting within-die, within-wafer, wafer-to-wafer, and chamber-to-chamber requirements. Further development along these lines seems obvious, as is the avoidance of unnecessary compensation, which only serves to increase complexity and narrow process windows.

Despite these many challenges, innovations in etch have successfully overcome potential roadblocks in the past, and I am confident that we will continue to find new solutions to allow the industry's continued learning and advancement.

Richard A. Gottscho, PhD, is Group VP and GM of Etch Businesses at Lam Research Corp., 4650 Cushing Parkway, Fremont, CA, 94538; email

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