Analyzing noise in modern MOSFETs


Executive Overview

In highly-scaled MOS devices, performance might be affected by individual atomic-scale features of the device structure, such as the position of the dopant atoms in the transistor channel [1] and electrically active defects in the gate dielectric. The latter was shown to generate noise in the drain current [2], which is essentially small fluctuations of the output current, caused by a carrier in the channel hopping in and out of a defect in the dielectric. Such noise significantly reduces design margins, so it is therefore critical to identify the defects responsible for noise to provide feedback for process improvement. Here we demonstrate that a comprehensive analysis of the noise measurements allows electron trap characteristics to be extracted, opening the door to greater understanding of the defect's nature.

D. Veksler, H. Park, C. Young, B. Taylor, SEMATECH Albany, NY USA; G. Bersuker,
R. Jammy, SEMATECH, Austin, TX USA

For a small transistor in which the actual defects are few, it is possible to observe the impact of a single trap. Figure 1a shows how the transistor drain current switches between two levels as a single trap absorbs, then emits, a single electron, thus producing random telegraph signal (RTS noise). The lower and higher current states correspond to the filled and empty trap, respectively. (The dashed line in Fig. 1a guides the eye.) A transistor with two different traps can have four different current states (either, both, or none filled); clean observations of eight distinct levels have been measured in transistors with three traps [3]. As the number of traps increase with the device area, the individual levels become indistinguishable. The low frequency portion of the noise spectrum of a large area device is a result of the overlapping Lorentzian-type signals of individual traps, which capture and emit within a range of frequencies (the spectrum of the corresponding noise power is a function of frequency; each dashed line in Fig. 1b schematically represents the noise spectrum of an individual trap.) (Fig. 1b). Therefore, RTS in MOSFETs with sufficiently small area can provide information about the properties of individual electron traps, while the low frequency noise of large area devices may be better suited for assessing the overall trap density.

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Figure 1. a) Typical two-level RTS signal in a high-k MOSFET. b) Schematic noise power density spectra: two-level RTS signal described by a Lorentzian function (dashed line) with its corner frequency, fcorn, determined by the average capture and emission times of the trap; superimposition of multiple Lorentzians in a large area device form a 1/f spectrum (solid line).

Low-frequency noise in MOSFETs

Conventional RTS analysis, which is based on the ratio of trap capture to emission times, uses a detailed balance equation, which takes into account the relative difference between the Fermi level and trap ionization energy at various gates and drain biases [4-6]. This analysis allows such characteristics as the trap thermal ionization energy and spatial position to be extracted while avoiding explicitly considering electron trapping/detrapping mechanism. However, knowing the defect energy alone is not sufficient for identification of the defect nature. To obtain additional defect characteristics, the analysis should be based on a wider set of independent experimental parameters contained in measured RTS, specifically, on the data sets of both trap capture times and emission times. For this purpose, we have to describe the physical processes of the electron trapping and detrapping.

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Figure 2. Schematic representation of the electron trapping process: a) tunneling to the trap; b) structural relaxation of the trap displacements of the lattice atoms around the defect; c) Total energy diagram, taking into account electron and phonon subsystems.

Electron transitions in condensed media using the concept of multiphonon-assisted (non-elastic) processes (see, for instance, [2,7] and references therein) were considered for a variety of physical phenomena. The specific case of electron trapping at the bulk defect in the gate dielectric can be considered (Fig. 2), within this approach, as a combination of two coherent processes [8]:

Electron tunneling from the transistor channel to the trap (Fig. 2a), with the probability

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Rearrangement of the lattice atoms forming the trap (Fig. 2b) to accommodate an additional electron charge, with the probability [9-11]

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Here xT is the trap distance from the substrate; λ is the characteristic electron tunneling length; Ip(x) is a Bessel function of an order p; is an equilibrium number of phonons; p = E0/??ω, S=Erelax/??ω, with E0 the total energy difference between the initial (trap is empty) and the final (electron in the relaxed trap) states of the system and Erelax the energy associated with the displacements of the atoms in the dielectric (the trap relaxation energy) caused by electron trapping; ω is the characteristic phonon frequency associated with these displacements; and T is an ambient temperature.

The process (ii), called the "structural relaxation," might significantly affect the trapping dynamics. Indeed, to form a new atomic configuration around the trapped electron, the lattice atoms must leave their initial equilibrium positions, which is, in general, associated with the system overcoming an energy barrier, EB=(Erelax-E0)/4 Erelax kT [2,10] (Fig. 2c). This barrier is responsible for retarding the electron trapping (and detrapping) process:

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In Fig. 2c, Q is the generalized coordinate of the atomic displacements in the system. Solid and dashed parabolas correspond to the full system potential energy in the empty and filled traps, respectively. Erelax is the energy corresponding to displacements of the lattice atoms ???Q. E0 is the energy lost by an electronic subsystem after a trapping event.

Within the Shockley Read Hall (SRH) approximation (which is found to be adequate for the RTS analysis), the capture and emission times can be expressed as follows:

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Here vt is an electron thermal velocity, n is electron concentration in the substrate, σ0 is the electronic component of the trap capture cross-section, EF is the Fermi energy in the substrate, Fox is the electric field in the oxide, e is the electron charge, and ET is the trap energy.

The critical importance of considering structural relaxation is obvious when one attempts to estimate the electron trapping time based exclusively on the elastic trapping model [12]. The time for an electron capture by a bulk defect in a modern MOSFET, calculated excluding the contribution of the dielectric lattice rearrangement, was found to be several orders of magnitude shorter than the measured ones [13,14], indicating that the trapping times are not determined by the electron tunneling probability.

Thus, a comprehensive analysis of the noise data should consider the total system energy including phonons in the dielectric along with the electronic subsystem. Such a description connects the measured values (the capture/emission times) to the trap's relaxation energy, which is a unique trap characteristic serving as an important marker of the defect's structure, in addition to the trap energy, location, and capture cross-section.

What may one learn from the noise measurement?

Examples below demonstrate extraction of the essential trap characteristics using the comprehensive noise analysis, which considers trap relaxation. In case of high-k MOSFETs, the noise data were collected on several small (W/L = 0.3µm/0.1µm) transistors with the 1nm SiO2/3nm HfO2/TiN gate stack, in the temperature range of 300K-345K. The average capture and emission times and their dependencies on the gate bias (Fig. 3) and temperature were extracted from the RTS data. These dependencies were reproduced theoretically using Eqs. (1-4). The traps in the high-k MOSFETs under investigation were found to reside in the interfacial SiO2 layer, sandwiched between the HfO2 and Si substrate, around 0.3nm from the substrate interface; the trap energy was ~ 3eV, counting from the conduction band edge of the SiO2 dielectric. At such short tunneling distances, the capture and emission times are controlled by the structural relaxation process (Eq. (2)). The relaxation energy was found to be rather high ~ 1.7 – 1.9eV. (The experimental error for extracting the relaxation energy is on the order of a few tenths of an eV.)

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Figure 3. Experimental (dots) and calculated (lines) average capture (circles) and emission (squares) times for a 1nm SiO2/3nm HfO2/TiN nFET. T = 300K, 330K, and 345K. A theoretical fit is performed with a single set of trap parameters for the entire range of gate biases and temperatures.

The extracted defect parameters, including the trap relaxation energy as the metrics of the trap lattice distortion upon electron capture, were compared with the results of ab initio calculations of several possible configurations of oxygen vacancies in SiO2 [15]. The comparison allows the traps contributing to noise to be identified as neutral (or V- after electron trapping) oxygen vacancies in the interfacial SiO2 layer of the MOSFET gate stack. This conclusion is also supported by evidence that the interfacial SiO2 layer in high-k MOSFETs is rich with the oxygen vacancies due to its interaction with the overlying high-k layer [16]. V- vacancy traps with similar characteristics were also identified from the RTS data collected from transistors with SiON/poly-Si gate stacks [8].

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Figure 4. a) Schematic of the TANOS band diagram. Extracted trap positions and energies are indicated. b) Noise spectral density for a stressed TANOS device. c) Analysis of 1/f noise data in TANOS devices. Filled and open symbols correspond to characteristic times (1/2πfcorn) of pre-existing and stress-generated traps, extracted from noise measurements. Lines are the theoretical fit.

The same approach was applied to interpret low frequency noise data from TANOS trapping memory transistors (W/L = 0.5µm/0.1µm) with a tunneling SiO2 dielectric of 4.5nm, (see Fig. 4a for a schematic of the TANOS gate stack structure). The measurements were performed using the standard noise measurements setup on fresh devices and then repeated after 1000 cycles of program/erase stress (the spectra in Fig. 4b were measured on the cycled devices). Peaks in the low frequency noise spectra corresponding to pre-existing (observed also in fresh devices spectra) and generated (observed after program/erase operation) traps are indicated in Fig. 4b by dashed lines. The dependencies of characteristic times, τEτC/(τEC)=1/2π fcorn, corresponding to the positions of the "peaks" in Fig. 4b vs. the gate bias, VGS, for pre-existing and stress-generated traps in a TANOS device are shown in Fig. 4c. A theoretical fit of these dependencies yields the values for the trap parameters. Both pre-existing and stress-generated traps contributing to the peaks in the low frequency noise spectra exhibit low relaxation energies, Erelax, ≈ 0.1eV and were found to be located deep within the SiO2 dielectric (1.26 and 1.6nm from the Si interface, respectively). (See also Ref. [8].) Note that the practical available frequency range of the noise measurement setup limits the observable spatial and relaxation energy window: the traps with lower Erelax can be observed farther away from the interface with the Si substrate (to keep the characteristic times above the low limit determined by the measurement frequency) [8].


The above self-consistent analysis of the charge exchange process between the semiconductor and defects (electron traps) in the dielectric opens up the possibility of identifying the defect responsible for low frequency noise characteristics. The theoretical approach employed, which takes into consideration a multiphonon trap relaxation process, reproduces experimental data in a given device with a single set of defect characteristics across the entire range of temperatures and gate biases. The analysis demonstrates consistent results over a variety of gate stacks (high-k/metal, SiON/poly, SiO2/SiN) used in the experiments.

The employed analysis allows the trap relaxation energy associated with the rearrangement of lattice atoms to be extracted. This energy represents a fundamental feature of the atomic structure of the defect and can be used to identify defect characteristics. In particular, the experimental values obtained for the relaxation energies indicate that the defects observed by the drain current RTS in high-k/metal gate devices are oxygen vacancies in the SiO2 layer close to the Si substrate. This analysis can be extended to other electrical characterization measurements that are based on the electron trapping/detrapping process, specifically charge pumping.


The authors would like to thank Dr. J. P. Campbell and Dr. K. P. Cheung of NIST for useful discussions.


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Dmitry Veksler is doing post-doctoral research in the electrical characterization group at SEMATECH, 257 Fuller Road, Suite 2200, Albany, New York 12203, USA; ph: 518-649-1141; e-mail

Gennadi Bersuker received his MS degree in physics from Leningrad State U., St. Petersburg, Russia, and a PhD degree in physics from Kishinev State U., Kishinev, Moldova and is a SEMATECH Fellow, at SEMATECH.

Hokyung Park received a BS in avionics from Korea Aerospace U. and an MS and PhD in material science and engineering from Gwangju Institute of Science and Technology, Korea. He is a device characterization and reliability engineer at SEMATECH.

Chadwin D. Young is a member of the technical staff at SEMATECH.

Bill Taylor received his PhD from Duke University and is a program manager at SEMATECH.

Raj Jammy is VP of materials and emerging technologies at SEMATECH.

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