Copper electroplating approaches for 16nm technology
Electrodeposition processes have evolved to achieve increasingly fast bottom-up copper growth in the features, as well as high nucleation densities that protect the thinnest areas of copper seed as the plating process begins [1-3] to take advantage of the improved seed layers in smaller features. This combination of PVD and electroplating has already been extended to fill feature dimensions beyond what was believed possible several years ago, and efforts are now directed toward development of processes capable of filling 1X nm memory structures and 16nm logic interconnects.
Jonathan Reid, Andrew McKerrow, Sesha Varadarajan, and Greg Kozlowski, Novellus Systems, Inc., San Jose, CA USA
Since its introduction as a manufacturing process in 1999 [4-7], copper electrochemical deposition (ECD) has demonstrated a robust capability as the manufacturing process for forming void-free integrated circuit interconnects, with dimensions ranging from sub-30nm lines to large pads. To a large extent, the extendibility of Cu electrodeposition to 28nm has been achieved as a result of PVD seeding processes that enable the formation of increasingly thin and conformal seed layers. It is these seed layers that enable continuous film coverage on a barrier surface without pinching off features due to excessive deposition on the top sidewall of the structure.
ECD process capabilities
For ECD, the process capabilities required to fill lines with sub-20nm dimensions will be defined largely by the profiles generated by the evolving barrier-seed process. Direct scaling of existing PVD barrier/seed and Cu electroplating remain the target for much of the 1X development effort. As illustrated in Fig. 1, this scaling begins to dramatically increase the feature's aspect ratio before plating, since several nanometers of metal deposition on the feature sidewalls is required for effective barrier properties and continuous seed coverage. Thus, for success at 1X dimensions, the need for more efficient bottom-up ECD processes and the ability to plate on minimal seed thickness increases sharply.
|Figure 1. Evolution of typical pre-ECD feature aspect ratio as a function of logic device generation.|
Alternatives to PVD-only barrier and seed layers for 1X dimensions include the replacement of the PVD barrier with a thinner and more conformal CVD film; partial feature fill using high plasma density PVD Cu; or processes in which thin conformal Cu films are electroplated directly onto liner films such as Ru  or cobalt. These alternative process flows reduce feature aspect ratio before electroplating and generally improve sidewall barrier/seed coverage, enhancing the extendibility of the ECD process. Regardless of the barrier/seed process sequence chosen, numerous enhancements to the electroplating process will be required for 1X generation interconnects.
For 1X electroplating applications, precise and uniform across-wafer control of the current waveform—as well as additive adsorption on the copper seed during the first several tenths of a second of plating—will be critical to the rapid void-free filling of features. Several Sabre hardware capabilities ensure optimum current uniformity across the wafer.
As the wafer enters the plating solution, a current must be applied to initiate nucleation and inhibit seed dissolution. For precise current density control, the applied current must scale with the immersed surface area during the 20-100msec period when the wafer enters the bath. On the Sabre tool, this is achieved using a capability called potentiostatic entry, which holds the voltage applied to the wafer constant until the wafer is fully immersed, thereby generating a constant current density. Potentiostatic entry has the additional benefit of allowing the initial current to scale with pattern density across a variety of product types.
Once the wafer is fully immersed in the plating solution, the current applied to the wafer is normally directly controlled to achieve maximum wafer-to-wafer precision. However, achieving a constant current density across the wafer during the first 1-2 seconds after entry remains critical because it is the local current density that impacts ongoing nucleation and additive adsorption, and hence, fill capability. As seed layer thickness decreases to the 10nm range used for 1X generation interconnects, the resulting sheet resistances increase into the range of several ohms/sq. This results in a large voltage drop through the seed layer between the wafer edge – where electrical contact to the wafer is made – and the wafer center, resulting in much higher current density at the wafer edge.
To counteract this voltage drop across the seed layer and ensure uniform deposition, the system utilizes three key current shaping elements known as the high resistance virtual anode (HRVA), the dual cathode, and the Iris. HRVA is designed to have an electrical resistance greater than that of the copper seed layer, and is placed close to the wafer and performs the function of a large swamping resistor. It forces equal current flow to all surfaces on the wafer but it alone is sufficient to ensure uniform current density at seed thickness as low as about 40nm; however, for thinner seeds, the dual cathode is also required.
The dual cathode is a secondary cathode surface surrounding the perimeter of the wafer, onto which the plating current is diverted by application of an independently-controlled current. This element is used to dynamically draw current away from the very edge of the wafer where the HRVA's effectiveness becomes insufficient. As seed thickness decreases into the range of 5-10nm, it becomes necessary to dynamically control current density across much of the outer 30-100mm of the wafer perimeter in order to generate a uniform current density during the first stages of plating. Usually, the dual cathode and IRIS effects are required only during the first few seconds of plating, since the conductivity of the seed layer increases quickly during plating. Combining HRVA with the dynamic use of the dual cathode and iris results in a uniformly-plated thickness profile evolution, and consistent across-wafer fill rates even on very thin seeds. Figure 2 shows the resulting thickness and fill evolution for deposition on 300mm wafers seeded with 5nm PVD Cu.
|Figure 2. Evolution of plated thickness profiles and fill rate uniformity across 300mm wafers on 5nm seed a) without and b) with dynamic current modulation.|
Uniform mass transfer of additives to the wafer surface is achieved using a combination of wafer rotation and flow which allows selection of diffusion layer thickness in the 20-100μm.
Seed protection; nucleation density
It has been known for many years that seed protection and high nucleation density is best achieved using high entry voltages and high initial current density . These conditions reduce the possibility of Ostwald corrosion across seeds of varying roughness, diminishing the potential rate of copper oxidation and increasing the density of nucleation in general. An effective combination of entry voltage and initial current control is required to maximize the capability to plate on very thin seeds without sidewall voids, while still allowing rapid bottom-up filling. However, usually a high voltage that improves nucleation and growth on thin seed layers results in degraded fill rate performance, and increases the chances of seam voids forming before bottom-up fill is complete.
Recent advances in initial current and voltage control on the tool have improved the ability to combine high entry voltages with effective filling. Using this feature – multiwave entry – the initial potentiostatic control of the wafer transitions to a more complex waveform that continues to enhance nucleation so that seed oxidation and Ostwald corrosion are reduced. Besides these effects, multiwave entry is designed to improve the uniformity of additive adsorption across a variety of feature densities. Because of diffusion effects, the relatively high concentration of suppressor additives in electroplating baths often adsorb more rapidly in isolated features – or in features at the edges of dense arrays – than they do in features in the dense array areas themselves. When this happens, the fill rate in the isolated features is slowed relative to the features in the dense arrays, and complete fill without center voids becomes more difficult. Multiwave entry modulates the adsorption of the suppressor and can equalize the fill rates across all feature densities. Figure 3 shows a typical result where this feature is used to increase the fill rate in features near the edge of an array of dense features.
|Figure 3. Fill evolution comparison at the center and edge of dense arrays of lines using a standard plating process and using two types of multiwave recipe modulation, multiwave 1 and multiwave 2.|
As feature size has decreased from 130nm to the 20nm range, the times required for complete fill have decreased from ~30s to the range of one-two seconds. In the case of relatively large features, a reliable bottom-up filling mechanism based on suppression of current on the wafer field by suppressor additives, and accumulation of current accelerating additives in the features, was well established [10,11]. When filling times decrease to 1-2 seconds, there is little time to accumulate the accelerating additive in the features, and the effectiveness of this mechanism diminishes . Novellus' processes have partially adjusted to this change by using modified concentrations of accelerating additives and decreasing the current density to lengthen the time during which accelerating additives can adsorb. Additive chemistry changes are also essential to improve filling.
Most additive development work is directed toward using stronger and faster acting current-suppressing additives to reduce Cu growth rate on the wafer field relative to growth in the feature. This approach has the added benefit that larger voltages must be applied to the wafer to generate a given current density, thus improving nucleation and inhibiting Ostwald corrosion. Limits to this approach are set by the requirement that the suppressor must be displaced within a feature by accelerating additives during traditional bottom-up fill, and by a general observation that the consistency of plated film quality is diminished with extremely strong suppressor additives. In an alternate or potentially complimentary approach, suppressor additives with very high molecular weights and relatively low solution concentrations may be chosen so that their diffusion rate into small features is relatively low . This can allow a transient suppression gradient between the wafer field and the feature base, and generate bottom-up fill in the absence of accelerating additives.
Although additive and current waveform effect dominate fill capability, characteristics of the electroplating bath such as temperature, ionic concentrations, and corrosion potential must also be optimized for 16nm performance. While demonstration of filling capability based on optimum additive, electrolyte, and waveform selections is essential, the critical ability to consistently achieve this performance across 300mm wafers with highly resistive seed layers has also been demonstrated.
Sabre is a registered trademark of Novellus Systems.
1. D.C. Edelstein, Y.J. Mii, G. A. Sai-Halasz, "VLSI on - Interconnection Performance Simulations and Measurements," IBM J. Res. Dev., 39, 383, 1995. 2. P.C. Andricacos, et al., "Damascene Copper Electroplating for Chip Interconnections," IBM J. Res. Dev., 42, 567, 1998.
3. D.C. Edelstein, et al., "Full Copper Wiring in a sub-0.25 micron CMOS ULSI Technology," Tech. Dig., IEE Inter. Electr. Dev. Meeting, 1997, 773.
4. P.C. Andricacos, "Copper On-chip Interconnections: a Breakthrough in Electrodeposition to Make Better Chips" Interface, 8, 32, 1999.
5. C.L. Beaudry, J.O. Dukovic, "Faraday in the Fab: A Look at Copper Plating for On-chip Wiring," Interface, Winter 2004, 40.
6. P.M. Vereecken, et al., "The Chemistry of Additives in Damascene Copper Plating," IBM J. Res. Dev., 49, 3, 2005.
7. J.D. Reid, "Copper Electrodeposition: Principles and Recent Progress," Jpn. J. Appl. Phys., 40, 2650, 2001.
8. T. Ponnusawamy, et al., "Reliability of Cu/Ru/TaN Interconnects," Advance Metallization Conf. Proc., Sept 23-26, 2008, Del Mar CA.
9. S. Mayer, R. Contolini, V. Bhaskaran, B. Jackson, J. Reid, "Integration of Copper PVD and Electroplating Processes for Fill of Damascene Features," Proc. of the 196th Meeting of the ECS.
10. J. Reid, S. Mayer, "Factors Influencing Fill of IC Features Using Electroplated Copper," pp. 53-62, MRS Jour. 1999 Advanced Metallization Conf. Proc. Red Book Series, M. Gross, editor, MRS Press, Warrenton PA, 2000
11. T.P. Moffat, et al., "Superconformal Electrodeposition of Copper," Electrochem. And Solid-State Lett., 4, C26, 2001.
12. R. Akolkar, U. Landau, "Mechanistic Analysis of the Bottom-Up Fill in Copper Interconnect Metallization," J. ECS, 156, 351, 2009.
13. J. Reid, J. Zhou, "Leveler Molecular Weight and Concentration Impact on Damascene Copper Electroplating Bath Electrochemical Behavior and Film Properties," ECS Trans., Vol. 2, No. 6, Jan., 2007.
Jonathan Reid received a PhD in Chemistry from the University of North Carolina at Chapel Hill and is a Fellow at Novellus Systems, Inc., 4000 North First St., San Jose, CA 95134 USA; 503-685-8353; email: email@example.com.
Greg Kozlowski received a MS In Operations Management from Rensselaer Polytechnic Institute and is a Director of Operations at Novellus Systems, Inc., 4000 North First St., San Jose, CA 95134 USA; 503-885-6637 email Greg.Kozlowski@Novellus.com.
Andrew McKerrow received his PhD in Chemistry from Queen's University, Kingston, ON, Canada, and is a Director of Technology at Novellus Systems, Inc., 4000 N. First St., San Jose, CA 95134 USA; 503-885-6361, firstname.lastname@example.org.