Issue



System integration is key to optimum test cell performance


05/01/2010







Executive OVERVIEW
The typical test cell used for IC final test consists of the tester, load board, socket, and test handler, including a package dedicated kit. Clear standards for functionality and interfaces have been defined and are well established for each of these elements. Standardization has numerous advantages for matching test components from multiple suppliers. Nevertheless, these sharply defined functions limit the potential optimized performance of the overall system. This article applies the methods of value engineering to overcome these limitations.

 Gerhard Gschwendtberger, Multitest elektronische Systeme GmbH, Rosenheim, Germany

Each of the final test elements for standard ICs has clearly defined functions in the test set-up (see Figure 1). The supplier of each single element strives to optimize each element, however, optimizing each single element and function will not necessarily provide optimized system performance and the resulting test accuracy and yield. While such standardized, multi-vendor solutions may suffice for standard IC testing, more advanced applications such as RF, fine-pitch, high pin count, MEMS, and extreme thermal test requirements, cannot be adequately served and total operating costs will be inflated.

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Figure 1. System integration in final test.

Based on the approach of value engineering, the overall function-to-cost ratio needs to be critically analyzed.

Thermal considerations

Temperature accuracy during test (i.e., temperature drift of the device under test [DUT]) becomes a more significant performance factor for a test cell. Many end applications require keeping the DUT temperature as constant as possible during electrical test. The temperature drift of the DUT is based on the thermal energy, which gets lost over the test socket and board, and the energy that is provided by the test handler and absorbed by the package. The goal is to reach balanced energy flows and transformations; especially for small and/or high pin count devices, this is often difficult or impossible to ensure because the electrical connections via the test socket to the load board acts like a large heat sink. Traditionally, the handler and kit must fulfill this function of keeping the package at the handler set temperature during test.

To provide the most cost-effective solution, it is highly efficient to consider the test socket and load board as parts of the thermal system. If the architecture of the test socket and/or load board minimizes the energy that is lost from the system, this may significantly push the technical envelope regarding high-end temperature accuracy during test. Better temperature stability of the DUT during the test can be achieved by adding thermal insulation to the test socket or load board. Additionally, the energy distribution onto the package can be supported and optimized by the test socket and/or the load board. Examples include combined air routings between kit/socket and load board, which of course require a fully integrated engineering approach. With respect to considering "temperature accuracy during test," an integration of the various parts of the system will provide substantial performance improvements without significant cost increases.

Electrical (frequency performance) considerations

The test socket together with the load board defines the high-frequency behavior of the electrical system. Although it is well understood that in many cases the load board is the main contributor to bandwidth limitations, poor test socket selection can become the performance limiter. It is important to select the correct socket that will not limit this performance. Many high-performance RF test sockets, however, have significantly higher costs of ownership due to lower lifespan, board wear, or high maintenance efforts (cleaning) in production environments. From the value engineering perspective, it makes more sense to look into the complete system (load board and socket) to optimize overall performance. Sometimes, only minor modifications to the board, based on RF simulations, can result in a higher bandwidth performance of the system. Simultaneously, production-worthy test socket solutions can be implemented into the system and create a much lower cost of test due to better lifespan, cleaning cycles, and reduced test cell downtime.

Mechanical considerations

There are various mechanical areas of integrated test solutions that can be optimized. Device alignment (positioning accuracy between package and test socket) is one of the most critical performance parameters in an automated test system, significantly impacting test yield and lifespan of consumables, which are key factors for overall cost of test. Device alignment very much depends on the package geometry, manufacturing processes and tolerances; there is no exclusive way to align IC packages. However, it seems that there are many different concepts in the market depending on which handler type or socket is used.

From the value engineering point of view, there should be alignment concepts that provide the most value (alignment accuracy) at the best cost (of test), which means the function of device alignment has to be executed in that area in which an optimum performance-to-cost ratio can be achieved. In many cases, a state-of-the-art test handler plus kit can provide the necessary positioning accuracy — in these cases, alignment features at the test socket (that usually are quite costly) are unnecessary. Additionally, the tolerance chain between the handler plunger and test socket can be optimized if the handler kit and socket are seen as one system. Again, to achieve the best value vs. best cost of test, it may be necessary to discard the common design standards and create new, more integrated ones.

Conclusion

There are many areas within a test system in which a more integrated approach can improve performance and reduce cost. This potential can be used if traditional functional standards are analyzed and optimized. New technical requirements for the test system, such as MEMS applications, high current/voltage applications and new package types, etc. are already pushing this way of functional integration.

Biography

Gerhard Gschwendtberger received his Dipl. Ingenieur from U. of Applied Science, Rosenheim and is the Business Unit Manager Contactors, at Multitest elektronische Systeme GmbH, Aeussere Oberaustrasse 4 - D-83026 Rosenheim; Germany; ph.: +49-8031-406-124; email  g.gschwendtberger@multitest.com

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