Market and technology trends in advanced packaging
Recent advances in device miniaturization trends have placed stringent requirements for all aspects of product manufacturing. Traditionally, device manufacturers and wafer foundry companies have achieved improved device performance by conventional front end scaling. However, packaging technology has recently become a performance bottleneck for leading edge devices. Hence, companies are increasingly investing in advanced packaging technologies to improve system level performance.
Manish Ranjan, Ultratech, San Jose, CA USA
Although flip chip technology has been in existence for the past thirty years, the ramp in wafer bumping has only begun over the past several years. In addition to eutectic flip chip bumping, a number of new bumping technologies including copper pillar, lead free solder and 3D packaging technologies such as fan-out wafer-level packaging and through silicon via (TSV) are being developed to meet future device packaging requirements. This article discusses some of the market and technology trends along with key lithography challenges for advanced wafer bumping applications.
Advanced bumping technologies
Rapid adoption of leading edge technology nodes (Fig. 1) has necessitated accelerated use of flip chip packaging technology. It is estimated that the majority of logic devices fabricated at sub-45nm technology node will utilize advanced packaging technology. In addition to traditional eutectic solder bumping, there has been increased adoption of advanced bumping technologies such as copper pillar and 3D packaging technologies. Key drivers for these technologies are discussed below.
|Figure 1. Wafer fabrication on advanced technology nodes. Source: VLSI Research|
Copper pillar. The primary drivers for copper pillar processes include superior electrical performance, thermal advantages and form factor considerations. Additional advantages include lowering the bump critical dimension floor, and continued downward scaling of the passivation opening size, extensions to higher I/O densities. The copper pillar process also provides options for tighter silicon and package routing pitches that can lead to higher pin densities and reduced die sizes.
3D packaging (fan-out WLP). During the past few quarters, there has been considerable momentum for adoption of fan-out wafer-level packaging technology. The introduction of this technology addresses the pad limitation consideration with traditional WLP, while delivering miniaturization and potential low-cost packaging advantages. Additionally, fan-out WLP technology can effectively leverage the current flip chip and WLP equipment infrastructure, thereby creating a cost-effective technology solution. It is estimated that fan out WLP solutions will be employed by a larger number of suppliers to address the packaging requirements for rapid growth in smart phone shipments (Fig. 2).
|Figure 2. Smart phone shipments (millions of units). Source: Gartner|
3D packaging (TSV technology). The primary drivers for the adoption of TSV technology include performance and form factor advantages. Key end products such as image sensors and power amplifier devices utilize TSV on the back side of the silicon chip. Future 3D TSV applications include DRAM, processors for computing and graphics, FPGAs, as well as processor and memory stacks for wireless products .
Key photolithography challenges
Photolithography is one of the key process steps affecting the final device performance. Key challenges observed during this process step are discussed below.
Imaging considerations for solder bumping. Successful imaging for advanced packaging processes include the ability to expose both thin and thick resist films. To meet the current and future technology requirements in a cost effective manner, end users have transitioned to 1X stepper technology. The use of stepper technology provides an ability to project the aerial image at various depths within a thick photoresist film which is especially critical for thick resists used in straight wall electroplating and copper pillar applications. Furthermore, 1X steppers illuminate a much smaller area during each exposure step and therefore deliver superior illumination performance resulting in improved CD uniformity. Lastly, the use of enhanced global alignment delivers significantly superior overlay performance in comparison to the two point global alignment method utilized by contact and proximity aligners thereby resulting in superior yield performance and associated cost savings.
3D process considerations for fan-out WLP. Unlike a typical silicon wafer, the die within the reconstituted wafer are not positioned in an accurate systematic array. The locations of the chips have a random error component due to the accuracy of the pick-and-place tool as well as to the shrinkage of the molding compound material during the compression molding process. While considerable improvements have been made with the pick-and-place equipment, it is very difficult to control the random shift of the silicon die during the compression molding process. This creates significant challenges in aligning subsequent metal layers to the device contacts.
The use of 1X stepper technology enables end users to use an enhanced global alignment routine whereby they can select multiple die to create an alignment map prior to the wafer exposure. The use of this alignment algorithm during exposure using stepper technology also provides significantly better overlay capability by addressing defects such as mask run out, isotropic wafer scaling, rotation errors and orthogonality errors. Furthermore, this technique is well suited to address the concern with positional accuracy of the die after the compression molding process. This, in turn, will allow end users to utilize fan-out WLP technology for leading-edge design rules with smaller pad openings and tight overlay requirements.
3D process considerations for TSV applications. Three-dimensional packaging technologies have gained increased acceptance for meeting the packaging requirements of devices such as CMOS image sensors. These advanced system-in-package (SiP) techniques require TSVs to allow very high density vertical interchip wiring of multiple device stacks. Lithography techniques utilizing dual side alignment technology is one of the preferred methods for creation of these through silicon via structures. The challenge for a dual side alignment design is to view this embedded alignment target, and expose a pattern on the back side of the wafer that is aligned to the device pattern on the front side. Furthermore, it is critical to ensure seamless processing of front end and back end photolithography layers on the same equipment for cost considerations .
It is expected that packaging technologies will continue to play an increasingly important role in overall semiconductor innovation and leading edge device fabrication. Successful volume manufacturing for varied advanced packaging processes demands innovation and joint collaboration efforts within the entire manufacturing and equipment supply chain.
1. P. Garrou, J. Vardaman, "3D Through Silicon Via: Infrastructure and Markets," customized market research report.
2. W. W. Flack, E. M. True, R. Hsieh, D. Fuchs, R. Ellis, "Development and Characterization of a 300mm Dual-Side Alignment Stepper," SPIE Conf. Proc., #6520-101, 2007.
Manish Ranjan received a master of business administration from The Wharton School of Business in Philadelphia and an MS in industrial engineering from State U. of New York at Binghamton. He is VP, advanced packaging technology/nanotechnology market at Ultratech, Inc., 3050 Zanker Rd., San Jose, CA 95134 USA; email firstname.lastname@example.org.