Electroless NiAu on thinned wafers enables cost efficient prototyping
The electroless deposition of nickel and flashgold is a pure batch process that deposits metal on any non-passivated surface. The Fraunhofer Institute for Silicon Technology ISIT offers both electroless deposition of NiAu and semiconductor process based pad modifications. This article discusses the use of electroless NiAu technology for prototyping.
Dirk Kähler, Fraunhofer Institute for Silicon Technology ISIT, Itzehoe, Germany
Electronic and PowerMOS wafers are usually fabricated in large batches and sold as single packaged die. The package sizes are permanently shrinking, nevertheless, advanced products often require bare die mounting to save additional space or gain additional performance. On a large scale production level, it is quite easy to get diced or undiced wafers even with 'exotic' pad finishes. For prototyping or small scale production, however, the situation is quite different. Manufacturers usually don't like to sell single wafers – not only because of the amount of administrative work for handling and billing, but for two less obvious, but much more important reasons. First of all, wafers are usually equipped with confidential test structures that are located in the dicing street, and, second, the number of bad dies on the wafer can easily be counted – a number that manufacturers like to keep confidential.
If a prototype customer is successful in getting an undiced single wafer, what one will end up with is a standard wafer with aluminum, or seldom, copper bond pads. Aluminum is a perfect choice for wire bond applications, but it is useless for soldering, Ag sintering, or gluing. To overcome this material incompatibility, different pad modifications can be used as follows:
Semiconductor process-based pad modifications. Utilizing the equipment of semiconductor or MEMS foundries, a variety of pad modifications including different kinds of galvanic bumps, are possible. Unfortunately, many process steps are required resulting in high initial costs for process setup and lithography masks.
Electroless NiAu (ENIG). The electroless deposition of nickel and flashgold is a pure batch process that deposits metal on any non-passivated surface. On the wafer front side, these are usually the pad openings. Since no lithography is required, the process is very cost effective for single wafer processing as well as serial production. Depending on the nickel thickness, which is usually in the range of 2µm to 20µm, the resulting bumps are well suited for reliable soldering, Ag sintering, or gluing applications (Fig. 1).
|Figure 1. a) Colorized electron microscope images of nickel gold bumps a) 5µm high b) 20µm high;|
The Fraunhofer Institute for Silicon Technology ISIT offers both technologies: Semiconductor process based pad modifications, and electroless deposition of NiAu. The choice of technology depends on the final product. The semiconductor-based processes are very flexible since additional tasks like pad redistributions can be solved. However, these processes are limited to a wafer thickness of several hundred microns. If thin wafers have to be handled, an expensive rigid carrier technique has to be used. Another drawback is the required compatibility of the wafer diameter to the capabilities of the foundry. At Fraunhofer ISIT, the wafer geometry is limited to 8'' diameter.
|Figure 2. A thinned 6'' wafer with NiAu under bump metallization.|
The electroless NiAu process has less stringent requirements. The default process works on 6'' and 8'' wafers with backside passivation and standard wafer thickness. If the wafer backside is metalized, deoxidized, or subjected to backgrinding, a liquid resist or tape will be used to protect the wafer back. The tape solution is also used for thinned wafers. It has been shown that 6'' and 8'' wafers can be handled without problem at a thickness of 70µm (Fig. 2). In addition, Fraunhofer ISIT is also able to handle unusual, e.g. rectangular wafer geometries, or even broken wafers.
Dirk Kähler received his diploma in physics from the U. of Hannover in 1998 and his PhD in electro engineering with distinction from the U. of Bochum in 2003. He is a packaging specialist at the Fraunhofer Institute for Silicon Technology ISIT, Fraunhofer Str. 1, D-25524, Itzehoe, Germany; email: firstname.lastname@example.org.