Automated inspection improves yield, reduces manufacturing cost of 3DICs


Executive OVERVIEW

This paper describes collaborative efforts at Sematech's wafer-to-wafer (WtW) 3D interconnect line at the College of Nanoscale Science and Engineering (CNSE), University at Albany, State University of New York, to develop standards and best practices for automated inspection for the next generation 3DIC and TSV processes.

Rolf Shervey, Rudolph Technologies, Inc., Bloomington, MN USA

It appears now that the next big technology driver for inspection and metrology equipment will likely be 3D integrated circuits (3DIC), which stack two or more chips vertically and connect them using through silicon vias (TSV) that pass through the wafer substrate.

3DICs enable the continuing effort to provide faster, more functional devices that are simultaneously smaller and more power-efficient. Somewhat ironically, 3DICs may allow the industry to extend Moore's Law by circumventing the need for continuing 2D shrinks on which Moore based his original observations.

TSVs appear now to be the best way to interconnect the chips in a 3DIC because of the many advantages they offer; chief among them is enabling higher densities of interconnects, which will result in faster devices with lower power consumption. For example, by integrating memory above a processor die with 1,000 pins of TSVs, the resulting parallel connection can reduce power consumption in the interconnect to less than one-tenth that of a conventional interconnect [1]. They also offer the ability to manufacture interconnects in situ or along with die-level packaging processes, instead of requiring separate device-level integration at wire bonding.

Most proposed TSV process flows require the finished wafer to be returned to the wafer fabrication process for TSV creation. Wafer-level and chip-scale packaging technologies were the first processes to propose returning a "back-end wafer" to the front-end process for RDL (redistribution layer) deposition and subsequent steps. TSVs promise to deliver the best advantages of both system-on-chip (SoC) and system-in-package (SiP) technologies, while achieving the optimum balance of functionality, low cost, and the quickest time to market. There is much key learning in inspection and metrology that can be applied between these parallel technologies—knowledge that, if shared and applied correctly, will result in a shorter learning curve for 3DIC/TSV processes.

Wafer inspection specifics

While there are many well-established technologies for automated inspection of the front-side of the wafer, inspecting the bevel of the wafer is still a relatively new concept. The need to inspect the wafer's bevel has only recently become apparent, due in large part to manufacturers' desire to extend the usable area of the wafer as close to the wafer edge as possible, and attempts to control defectivity in immersion lithography applications. Bevel inspection is equally important to 3D interconnect manufacturing.

Because the wafers are bonded together during the 3D process, it is important that the equipment (including the robotic wafer handler) is able to handle an ~1550μm-thick wafer pair, equivalent to two standard SEMI M1 300mm diameter wafers at 775± 25μm total thickness each [2]. Because this is not yet common throughout the industry, it was found that there were several challenges to be addressed specific to handling bonded wafers.

Adjustments to the cassette mapping, for example, were necessary so that the robot would not detect the wafers as a cross-slot or mistakenly double-slotted pair. In addition, robot speed was reduced until safe wafer handling could be assured. Because two wafers are twice as massive as one, robot end effector bow has to be monitored carefully.

Inspections were performed for in-line manufacturing monitoring using a Rudolph Technologies AXi935/E30/B30 Advanced Macro-Defect Inspection System after various 3D interconnect steps, and also as specifically designed experiments meant to test the capabilities of the equipment.

Wafer inspection for foreign material (FM) and other defects that may have been introduced during wafer processing is a common application. In one example, wafers that went through a wet process and subsequent drying were found to have slight discolorations across the wafer, which were assumed to be oxidation. This may have been induced by the process itself or by storage methods used for these wafers. Discovering these defects resulted in savings associated with avoiding further wafer processing and potentially more costly rework later. These defects would most likely not be found using manual inspection.

The edge inspections are performed by a dedicated module that is part of the cluster, and has independent cameras for edge top (ET) and edge normal (EN) views. In addition, two sources of illumination are available for each camera. High scattering defects in partially patterned and non-patterned ET areas are best detected using dark field (DF) illumination and algorithms.

A low grazing angle is used to illuminate the defect without illuminating the underlying patterns and to detect defects based on scattering intensities. Once detected, the system marks the location of defects for later color image capture with bright field (BF) illumination. To verify the bond process, inspections were performed after wafer bonding, and before thinning the top wafer. This method allowed process problems to be detected before investing additional processing resources in defectively bonded wafers.

In the bonding process, there is a chance for foreign material (FM) to be introduced into the bond area, or between the wafers. FM in this area may have become lodged and may be difficult to remove by conventional cleaning techniques; it may lead to voids between wafers that result in electrical opens.

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Figure 1. Wafer edge chipping on the bevel (image captured in DF illumination).

Wafer edge inspection is also of critical importance in detecting wafer damage that may result in costly equipment downtime when defective wafers break. Handler-induced edge chips (Fig. 1) have been found to later cause wafer breakage because they are prone to brittle fracture. Good separation of the BF and DF channels is critical to isolate the detection of this type of defect. An edge chip can be seen clearly against the dark background in DF because the color noise from the BF channel does not interfere with detection.

Edge-top inspection of wafer

As the wafer edge becomes very thin—like a knife edge—during grinding, it has a chance of breaking. To avoid this, the top wafer can be trimmed prior to the thinning step (Fig. 2). The edge trimming process can be monitored for process problems, such as cracking or chipping.

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Figure 2. Diagram of edge-trimmed, thinned wafer on carrier wafer.

To inspect for defects in this edge trim zone only, a narrow region of interest should be defined so that other variations can be ignored (Fig. 3). Examples of defects of interest were found in some samples, which provided evidence of an out-of-tolerance trimming process (Fig. 4).

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Figure 3. Region of interest showing the trim line.

The most often neglected area on a wafer is the backside. Traditionally, the backside of a wafer has been considered of little importance in typical wafer processing. It is eventually ground away, and the fact that defects occur there during processing may be taken for granted.

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Figure 4. Defects on the trim line.

In 3D interconnect manufacturing however, the back of the wafer plays a more critical role because of the depth and complexity of the processing steps, which often involve wafer flipping. It is also safe to assume that 3D interconnect processing requires at least several times more wafer handling, multiplying the opportunities for creating backside defects.

During the inspection of sample wafers, many different types of defects were found. Because standard requirements for the backside of the wafer are not well defined, the challenge was to determine which defects were critical and which were unimportant.


Wafer bonding and the challenges that accompany it are unique to the 3D interconnect manufacturing process, and demand new equipment and methods to address emerging inspection and metrology requirements. Existing automated macro inspection tools, however, are capable of detecting many of the defects that occur in the 3DIC and TSV processes, and serve as an excellent platform for identifying needs and refining specifications. There are also important parallels between 3D interconnect manufacturing and wafer-level chip-scale packaging (WLCSP) that can provide valuable guidance for 3DIC process development. Future work at Sematech will include defining both inspection and metrology requirements for die-to-wafer (DtW) integration, as well as establishing standards and best practices for in-line inspection and control of 3D interconnect manufacturing as a whole.


This article is based on work presented by the author at the International Wafer Level Packaging Conference (October 2009). The author would like to thank the engineers at Sematech who contributed to this paper, in particular: Raymond Caramto, Jamal Qureshi, Andy Rudack, Pratibha Singh, and Chris Taylor.


1. R.C. Johnson, 3-D Chip Stacks Standardized, EE Times, July 10, 2008.

2. R. Goodall, 300mm Test Wafer Specifications for 0.25μm Technology,
International 300mm Initiative, June, 1997.


Rolf Shervey is a graduate of the U.S. Navy's nuclear power program and is assigned to International Sematech; he is a senior applications engineer at Rudolph Technologies, 4900 West 78th Street, Bloomington, MN 55435 USA; 952-820-0080;

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