Issue



Lithography perspective for the 22nm half-pitch


02/01/2010







Executive OVERVIEW

At the 22nm half-pitch (hp) node designated in the International Technology Roadmap for Semiconductors (ITRS) [1], the industry will have the choice between two competing lithography solutions, depending on their product roadmaps. In some cases, companies may even use both. The two competitors are extreme ultraviolet lithography (EUVL) and 32nm hp 193nm immersion double-patterning lithography (DPL) extended to multiple patterning lithography techniques. This article discusses the two technologies, comparing status of key solutions required for both as well as the challenges that remain.

Stefan Wurm, Sematech, Albany, NY USA

For DPL, the extension towards 22nm hp, though technically feasible, will be economically challenging. This realization is driving innovations not only on the technical side but also in layer-by-layer DPL approaches.

Despite progress, EUVL still must meet a challenging timeline—ready for pilot line introduction in 2011 and high-volume manufacturing (HVM) introduction in 2013. Key to its success is the availability of EUV mask tools for blank inspection, aerial imaging review, and patterned mask inspection. Enabling these tools on an aggressive timeline will add a significant business challenge to the technical challenges.

To share the risk and cost, the industry is adopting new business models for collaboration among mask blank suppliers, mask tool suppliers, mask shops, device manufacturers, and consortia. If successful, this will enable EUVL for 22nm hp and a lithography technology likely to support lithographic patterning for 11nm hp and below.

EUV source

EUV power requirements are specified at 115W at IF for 5 mJ/cm2 resist and 200W at IF for 10mJ/cm2 resist. This power must be delivered at the IF within a 2% bandwidth centered about the 13.5nm wavelength. Radiation produced by the plasma source outside this bandwidth (i.e., out-of-band radiation) needs to be suppressed to avoid compromising the image contrast.

Over the past decade, the industry has developed two EUV source technologies: discharge produced plasma (DPP) and laser-produced plasma (LPP). Today, LPP sources can deliver ~50W of stable output power at IF if a 5 sr collector mirror is used [2]. DPP sources have demonstrated 14W at IF with a three-shell collector, which could go to 34W at IF if a nine-shell collector developed for beta-type sources were used [3].

Click to Enlarge
Figure 1. EUV source readiness for 22nm hp pilot line and HVM.

Figure 1 shows how sustainable EUV source output power compares with pilot line, mid-cycle insertion, and HVM requirements. Pilot line operation will require throughputs of 30-40 wafers per hour initially. Several pilot line-capable resists with the required resolution and 12-15mJ/cm2 sensitivities are available today, setting the required source power at 25-30W. As shown in Fig. 1, this requirement is being met.

Some DRAM and Flash manufacturers would like to introduce EUV into manufacturing before the 22nm hp node. Figure 1 designates this timeframe as 25-27nm mid-cycle insertion; this will require source power that can support a stable throughput of ~60 wafers per hour. With resist sensitivity at 10-11mJ/cm2, ~ 50W at IF will be required. While an LPP source is already demonstrating the power level to support this target, it must still demonstrate stable long-term operation in a fully integrated source collector module with power directly measured at the IF.

DPP sources currently used in alpha tools have also made progress. Recently, 14W at IF has been demonstrated. The consolidation of DPP source suppliers may help concentrate efforts such that scaling issues, which are seen as more severe for DPP than for LPP sources, can be addressed. Both technologies still need significant engineering resources to enable at least one to meet the 200W at IF level projected for manufacturing tools.

With power requirements for second/third-generation EUVL exposure tools rising to >500W at IF, source scalability raises issues. Progress has been made in mitigating debris and protecting source collector mirrors. As source power increases, mitigation and protection methods must become even more efficient, and managing thermal loads will become more challenging.

The first beta-type EUV source to be integrated with a beta-type exposure tool was shipped this summer; more sources are being assembled that will be integrated into the beta tools that will ship in 2010. While EUV sources still face significant integration hurdles for HVM, they are on track to support pilot line production in 2011 and early manufacturing in 2013.

EUV mask

As chip manufacturers prepare for pilot line introduction, mask yield and the infrastructure to achieve it have resurfaced as top critical issues. Substrate and mask blank defect levels have steadily improved, but more slowly than expected. While past progress in defects had been measured against the goal of a defect-free mask blank, the industry is now concentrating on enabling a realistic mask yield that can support EUVL introduction. This practical approach acknowledges that defect requirements will be different for the more defect-tolerant DRAM and Flash applications than for the less-defect tolerant MPU and Logic applications.

Setting the critical defect size to 25nm and 18nm for mid-cycle insertion (25-27nm hp) and 22nm hp introduction, and using empirical defect scaling laws [4], the best mask blank data translate into ~0.4 defects/cm2 @ 25nm and 1.0 defects/cm2 @ 18nm.

Click to Enlarge
Figure 2. Zero-defect mask blank yield as a function of the percentage of printable defects; the yield function assumes a simple Poisson model. The percentage of printable defects depends on feature size with 10-20% of defects printing for larger geometries and higher percentages for smaller geometries. Today's defect level is ~1 defect/cm2 @ 18nm equivalent size.

As shown in Fig. 2, a realistic pilot line target is 0.02-0.04defects/cm2. Therefore, the gap between current capability and pilot line requirements for mid-cycle insertion is ~10X, while the gap for a 22nm hp pilot line is ~25X. For HVM, a realistic target is~0.01 defects/cm2, which leaves a gap of ~50X and ~100X between current levels and mid-cycle HVM and 22nm hp HVM specifications, respectively. Assuming a 2013 HVM introduction, about four years are left to improve mask blank defect levels by ~100, which is not an unrealistic goal.

Figure 2 looks at first pass yield only. The capability to repair two to three defects per mask blank would significantly improve mask yield. Also, DRAM/Flash applications have a higher defect tolerance than MPU/Logic applications. With a typical redundancy of 4-5X for DRAM/Flash, a 10X gap between current mask blank defect levels and pilot line requirements is a conservative assumption. The volume demand for mask blanks by early EUVL adopters, such as DRAM/Flash manufacturers, will enable the learning cycles to reduce mask blank defects to a level acceptable to MPU/Logic manufacturers.

The two major contributors to mask blank defects are defects already in the substrate and defects added during multilayer deposition. Reducing defects and simultaneously meeting stringent mask flatness requirements is a challenge. The flatness of reflective EUV masks is driven by the need for pattern placement accuracy on the wafer. Recently, however, it has been recognized that some mask non-flatness can be tolerated if the pattern written on the mask can be adjusted such that the final image on the wafer is the same as for a flat mask with no flatness compensation.

First results show this is feasible, at least to correct low-order non-flatness terms, such as a simple bow. It now seems likely that greater non-flatness can be tolerated [5]. Relaxing the flatness specification will make meeting substrate defectivity specifications easier. Current multilayer deposition tools can likely achieve pilot line mask blank defect targets; however, achieving HVM specifications will require a new generation of tools, the first of which is expected to be operational at Sematech in 2011.

Meeting mask blank defect goals for pilot line and HVM will require a capable EUVL mask inspection
eview tool infrastructure. To address this, a Sematech-led technical working group is defining the technical requirements, assessing current capabilities, and developing plans to support pilot lines using available tools as well as developing a plan for HVM inspection and review tools. In parallel, a business working group is addressing funding to develop new HVM inspection
eview tools.

The technical working group has reached consensus on tool specifications for pilot line and 22nm hp HVM, including mask substrate inspection (optical), mask blank inspection tool (actinic and optical), aerial imaging (actinic), and patterned mask inspection tool (actinic or optical). Any new tool that meets these specifications must be extendable to the 16nm hp node.

Current inspection tools, with improvements, will support pilot line needs, but printing inspection will need to be substituted for aerial imaging, with some support from existing R&D actinic review capability (e.g., Sematech's AIT). Also, blank suppliers must be able to access improved substrate and blank inspection capability; these can be improved versions of current 266nm wavelength tools or 193/199nm wavelength tools that are now available; however, the substrateinspection capability of 193/199nm tools still must be demonstrated.

Deep ultraviolet (DUV) 193/199nm patterned mask inspection tools will also be used to inspect mask blanks. One such tool has already demonstrated it can likely support the final blank development phase and pilot line inspection requirements [6]. Optical patterned mask inspection (OPI) capabilities for pilot line production are already offered by multiple suppliers.

For 22nm hp HVM, actinic pattern inspection (API) cannot be ready, but with some additional development 193/199nm (OPI) will be; however, if the industry must rely on OPI for 22nm hp, actinic blank inspection (ABI) will most likely be needed. There are two options to obtain ABI capability: develop a standalone ABI or use API tools for ABI. If OPIs can detect all defects an ABI tool finds, the real need date for ABI could be pushed out to when API tools will be available, making the development of a separate standalone ABI tool unnecessary.

There is no viable HVM mask-tooling scenario without an aerial imaging tool; even if an API with aerial imaging capabilities would be possible in 2013, the industry would prefer a standalone tool. Improved high brightness source technology is required for all three actinic tools. While improved sources will most likely support aerial imaging and ABI tools, API requires a much brighter source that still must be developed.

While the technical aspects of these tools are now better understood, the business case to enable them remains challenging. Sharing the risk and cost of developing the inspection
eview tools among all EUV stakeholders will be crucial.

EUV resist

Today, more resists from more suppliers are close to meeting 22nm hp pilot line requirements. Recently, image modulation down to 16/17nm hp has been demonstrated for chemically amplified resists, and dense features in the low 20nm are routinely being achieved [7-9].

The current performance of the best resists from seven resist suppliers is summarized in Fig. 3. Clearly, meeting the resolution and sensitivity targets for 25-27nm hp and 22nm hp insertion are well within reach or already achieved. Although LWR has been further reduced, a significant gap remains towards meeting DRAM/Flash and MPU/Logic requirements.

Click to Enlarge
Figure 3. Resolution, LWR, and sensitivity data from seven suppliers. Pilot line targets for resolution and sensitivity are being met while the LWR gap still must be addressed.

The current best LWR data is 5-6nm at < 25nm hp features sizes. For pilot line introduction targeting memory products, ~4 nm LWR will be sufficient, while microprocessor products will initially require ~2 nm. Both targets are significantly relaxed from the 1.2nm ITRS target. Therefore, there is a ~1.5X and a ~3X gap to meet pilot line requirements for DRAM/Flash and MPU/Logic, respectively.

For HVM, DRAM/Flash is expected to require 2.2nm, and MPU will require 1.2nm; therefore, the gaps for HVM at 22nm hp are ~2.5X and ~4.5X for DRAM/Flash and MPU/Logic, respectively. Continued improvement of resist materials combined with post-exposure LWR reduction and an etch process that reduces LWR is expected to close this gap, as is already being demonstrated by several companies [8,9]. While some tools, with some restrictions, can support optical projection imaging down to 16nm hp [7], higher numerical aperture micro-exposure tools will eventually be required to extend resist research towards 16nm hp and below.

Conclusion

EUVL has clearly gained momentum over the past year. The industry will see beta exposure tools delivered in 2010, with several chip manufacturers planning to start pilot line operation in 2011. While a 2013 HVM introduction date is now widely accepted, this momentum must be maintained and the industry must coordinate resources to enable the mask inspection
eview tools to support HVM introduction. If this can be achieved, and progress in source, mask, and resist technology continues, EUVL will soon be used in manufacturing, with critical layer exposures prhaps starting before 2013. Innovation and progress in double patterning continue, and feature sizes down to 22nm hp are being demonstrated. Customized layer-by-layer approaches using a multitude of double patterning options optimized for specific applications start to address some of the cost concerns for extending immersion lithography with double patterning to smaller feature sizes. In the end, chip manufacturers must decide which technology to use based on its availability and cost and the requirements of their product roadmap.

Acknowledgments

The author would like to acknowledge his colleagues in Sematech's lithography division and at GlobalFoundries, Intel, and Samsung for valuable discussions.

References

1. International Technology Roadmap for Semiconductors, http://public.itrs.net/

2. 2009 International Symposium on Extreme Ultraviolet Lithography,October 18-21, 2009, Prague, Czech Republic; www.sematech.org/meetings/archives.htm#litho

3. M. Corthout et al. in ref. 2.

4. A. Rastegar, P. Kearney, and C.C. Lin, Sematech, private communication.

5. J. Sohn et al. in ref. 2.

6. D. Wack in ref. 2.

7. P. Naulleau et al. in ref. 2.

8. T.R. Younkin et al. in ref. 2.

9. C. Koh et al. in ref. 2.

Biography

Stefan Wurm received his doctorate in physics from the Technische Universität München, Germany, and is the Associate Director of Lithography at Sematech where he is on assignment from GlobalFoundries. Contact: Sematech, 257 Fuller Road, Albany, NY 12203, USA; 518-649-1000; media.relations@sematech.org.

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