Modeling of stress and narrow-width effects in shallow trench isolation
Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors. Although its function is intended to be electrically passive, as device dimensions shrink, the influence of STI on the transistor characteristics becomes stronger. This article describes two such examples of interaction between STI and transistor performance. The first example examines the impact of STI on the threshold voltage of narrow-width transistors—the so-called narrow-width effect. The second example addresses a larger area by considering the stresses induced by STI on nearby transistors. Both effects can be accurately simulated with TCAD, allowing technologists to optimize the process to account for and mitigate the impact of these effects. Compact modeling approaches to account for the effect in design flows are also described.
Ricardo Borges, Synopsys, Mountain View, CA USA
The silicon-silicon dioxide (Si-SiO2) interface is arguably one of the most technologically important interfaces of any material system. The interface is formed through well-controlled oxidation and deposition techniques, and its low defect density enabled the now ubiquitous MOSFET to prosper and eventually dominate as the transistor of choice for high-density digital and analog integrated circuits. The vast literature reporting on its properties spans several decades and includes a whole treatise .
Beyond its electrical characteristics, it is well known that the Si-SiO2 interface affects the redistribution of dopant impurities during silicon processing. More generally, the volume of large SiO2 regions, as used in STI, also imparts stresses on the adjacent silicon regions. As device dimensions shrink, the processing and mechanical interactions between Si and SiO2 regions become more important and, in some cases, such as the ones illustrated here, have a large and unavoidable impact on transistor electrical characteristics.
During silicon processing, ion implantation of dopant impurities dislodges silicon atoms from their lattice sites, which are known as interstitial silicon. The subsequent annealing process repairs some of this lattice damage with the reinsertion of interstitial silicon into vacant lattice sites, but some interstitial silicon atoms remain and play an active role in the diffusion and electrical activation of the dopant impurities.
Boron, in particular, relies on the availability of interstitial silicon for its diffusion. High concentrations of interstitial silicon consequently enhance boron diffusion, a phenomenon known as transient-enhanced diffusion (TED). TED is an undesirable effect in high-scaled MOSFETs, where ultra-shallow junctions (USJs) are an essential aspect of the scaling. On the other hand, interstitial silicon atoms also diffuse through the silicon and recombine at the Si-SiO2 interface, which, in turn, acts as a sink for these interstitial silicon atoms, affecting their concentration in the silicon and the attendant diffusion and concentration of the dopant impurities.
The result of this interaction is particularly pronounced in NMOS transistors, where the boron concentration can decrease substantially in proximity to the STI edge relative to the center of the channel . In narrow-width devices, this STI proximity effect extends well into the core of the transistor, resulting in a significant decrease in the average channel doping concentration and the threshold voltage.
To investigate these effects quantitatively, we resort to three-dimensional TCAD simulation using Sentaurus simulators . The simulations are based on a generic 45nm CMOS process that features 40nm gate length, 160nm poly-to-poly pitch and high-k gate dielectric with metal gate. The metal gate is intentionally stressed to enhance electron mobility in the channel of the NMOS transistor. The PMOS transistor, on the other hand, relies on compressive stress from silicon germanium (SiGe) pockets to enhance the hole mobility.
In addition to these intentional stress sources, unintentional stress from the nearby STI alters the stress fields in the transistor active regions in ways that vary according to the transistor width. This effect is shown in Fig. 1 for the NMOS transistor.
|Figure 1. Longitudinal stress ZZ (top) and vertical stress YY (bottom) stresses for various transistor widths.|
The stress distributions for the longitudinal component are similar for the range of simulated transistor widths, and retain their tensile character as required to enhance electron mobility in the channel. The vertical stress distributions, conversely, undergo drastic changes as the transistor width approaches its minimum dimension and becomes increasingly compressive (blue contours). This can be explained by the proximity of the STI sidewall, which applies a compressive stress to the adjacent silicon as a result of its volumetric expansion during oxidation.
Figure 2. Width dependency of threshold voltage for NMOS transistor with gate length of 40nm.
The combined effect of the changing stress fields and doping concentration due to TED result in variation to the drive current and threshold voltage as a function of transistor width. Figure 2 shows the roll-off of the threshold voltage as the transistor width is reduced, a key characteristic of the narrow-width effect.
A similar effect is typically observed in PMOS devices. This roll-off of the threshold voltage is generally undesirable, as it adds complexity to compact modeling of the transistor and circuit design. By capturing these effects in simulation, process engineers can explore alternative processes to partially mitigate or eradicate this effect for both bulk and silicon-on-insulator (SOI) technologies .
Layout proximity effects
Layout proximity effects due to stress stem from the feature-size scaling and layout-process interactions inherent to strained silicon engineering used in advanced CMOS technologies. Proximity alludes to the non-local aspect of stress fields, which can range over several microns from the source of the stress. This means that any given transistor is subject to stresses generated well beyond the boundaries of its active region. The stress sources can be intentional—as in stress liners, SiGe source-drain regions, gates with stress memory, etc.—or unintentional, as in the case of STI stress.
The impact of STI stress on transistor performance has been studied since the inception of STI processing, supported by detailed modeling studies . Subsequently, compact models were enhanced to account for the effect, as in the case of the length of diffusion (LOD) model added to the BSIM4 family of models.
The rising importance of stress engineering to enhance transistor performance at the 45nm node and below has spurred new modeling efforts beyond LOD to comprehensively and accurately account for its layout proximity effects. The modeling is complex due to the directional dependency, variation of stress sources, and sensitivity to layout context.
Directional dependency occurs because the mobility sensitivity to stress (piezoresistance effects) may change drastically in sign and magnitude from one direction to another. For instance, 1GPa of compressive longitudinal stress (parallel to L) yields ~70% enhancement in hole mobility in PMOS, but the same amount of stress along the transverse direction (parallel to W) degrades the mobility by ~70%. For NMOS devices, both longitudinal and transverse tensile stresses enhance the electron mobility, but vertical tensile stress reduces it.
The materials introduced as stress sources cause variations in the transistor channel by virtue of their intrinsic stresses, topographical forms and boundary conditions. Besides STI, new stress sources intentionally used in the process—embedded SiGe, single or dual-stress liners in the form of etch stop layer (ESL), stress memorization technique (SMT)—all exhibit distinct stress behaviors and interact in a complex manner.
The layout affects stress in the silicon because it defines the boundary conditions of the stress field for a given process technology. Each layout feature, such as the edges or corners of the STI, contributes to stress variation with an interaction range of up to 2μm. This means that one must look beyond an isolated transistor and include all layout parameters within the window of interaction in order to properly account for the stress proximity problem, as depicted in Fig. 3.
|Figure 3. Window of proximity analysis for evaluating the stress and electrical performance of a specific transistor.|
Stress, in turn, alters carrier mobility (and ultimately, the transistor drive current) via piezoresistance effects. The mobility change relative to stress free mobility μ0 is given by
where stotalxx, stotalyy and stotalzzare channel stress components along the longitudinal, transverse, and vertical directions, with the corresponding piezoresistance coefficients πl, ρt, and πv, respectively. Since stress-free transistors seldom exist in advanced CMOS technologies, the mobility ratio of a device (μ) to a given reference structure (μref) is used to scale SPICE parameters,
where ρref is evaluated from Eq. (1) for a reference device. In the context of BSIM4 models, one has :
A compact model for stress proximity effects can be obtained if basic functions describing the geometric dependence of the stress are established and are then linearly superimposed to yield the total stress of each component,
where stypexx (rij) is the basic function describing the longitudinal stress components from a given type of stress source (STI, ESL, SiGe, etc.). A similar expression is used for the other components: stypeyy (rij and stypezz (rij.
This type of model can be used with a layout processing engine to calculate the unique stress condition of each transistor, the impact on the electrical characteristics, and the instance-level changes needed to the transistor compact model parameters.
Although the ways in which stress fields from various sources combine to yield complex patterns are often three-dimensional and involve all the stress components shown in Eq. (1), even simpler two-dimensional cases can attest to the complexity of the phenomena. Figure 4 compares the longitudinal stress component for an isolated transistor and a transistor with diffusion neighbors. The STI is 0.4μm thick and was simulated with a 950°C thermal cycle. Since the transistor with the diffusion neighbors has a reduced STI volume relative to the isolated case, it sees a three-fold reduction in the compressive stress.
|Figure 4. 2D TCAD simulation showing the effect of neighboring diffusions on channel stress. The stress with the neighboring diffusions (b) is reduced three-fold compared to the isolated device (a).|
Notwithstanding the effect of other stress components not included in this simple 2D simulation, the changes in the compressive stress would enhance the performance of a PMOS transistor and would degrade the performance of a NMOS transistor.
Despite its intended role as passive isolation, STI affects the mechanical state and electrical performance of neighboring transistors, motivating the need to analyze and model its impact during technology development and design. This article presented TCAD simulations of two such prominent cases: the narrow-width effect and stress proximity effects. In the narrow-width effect, STI contributes to variation of the channel doping and stress, with the combined result of a significant shift in the threshold voltage. Stress proximity effects are endemic to strained silicon technologies. The STI adds compressive stress to its adjacent silicon regions, and is summed with other stress sources to determine the overall stress state and electrical performance of individual transistors in the design.
The author would liked to acknowledge his colleague Xi-Wei Lin and the TCAD Application Development team for the helpful discussions.
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Ricardo Borges received his MSEE from Tufts U. and is senior manager, product marketing, Silicon Engineering Group, Synopsys Inc., 700 East Middlefield Road, Mountain View, CA 94043 USA; email@example.com