Life after the


Click to EnlargePete Singer

In 2005, SEMI commissioned a report that looked at the funding gap between what it would cost to achieve the goals defined by the industry in the International Technology Roadmap for Semiconductors (ITRS) and what equipment and materials suppliers were realistically capable of spending on R&D. The conclusion, at the time, was that by 2010 there would be a shortage of somewhere between $6-9 billion (the higher figure including the costs of transitioning to 450mm).

The recession is, by all measures, over for the semiconductor industry. This issue features rosy outlooks from forecasters and industry executives (and if they had written them even closer to press time, they'd be rosier still). After many devastating quarters, the capex faucet has been turned on, and equipment and material suppliers are enjoying "a very strong growth spurt," as Dean Freeman, research VP at Gartner, noted in mid-December. Foundries and a few memory companies started spending again in 2H09, and 1H10 will see an influx of technology upgrades. After a possible lull in 3Q10, look for capacity upgrades to ramp up into 2011, he says.

Back to business as usual? Hardly. Suppliers have had to hit the revenue "Reset" button, while R&D demands continue to grow. At the recent International Electron Devices Meeting, I had a chance to sit down with Dan Armbrust, the new president and CEO of SEMATECH. Dan, who was most recently the vice president of 300mm semiconductor operations at IBM in East Fishkill prior to SEMATECH, described the R&D funding situation as "under a lot of stress." He said equipment supplier shareholders "are going to be pressing to reset R&D (i.e., spend less) at the very same time that customers, the chipmakers, are saying you can't reset R&D. We need you to invest more. And, oh by the way, we'd like you to consider 450mm."

Armbrust believes the equipment industry may have to cooperate in a way similar to what that the chipmakers did 20 years ago. Saying EUV is a perfect example, where only one supplier is fielding a solution, Armbrust said "it's getting to the point where we're only going to have one supplier, and they can't even afford the development or won't take the risk of developing the tool that's needed without an expression financially of commitment of the ultimate beneficiaries, which would be the mask makers or the chip makers," he said. "You're just getting into a very different world where you don't have two or three or four suppliers, you've got one or two and they've got to get it right. It's really interesting to listen to how people are trying to work their way through this. We know how it worked, we know how we all got successful, but is that going to work for the next ten years? I don't think it will," Armburst said.

One solution is, of course, consortia such as SEMATECH and IMEC. Although they have very different models, both play a role in helping suppliers develop new technologies and determine their production worthiness. "When we get our hands on a piece of equipment, we can provide a dataset back, which is very useful to the supplier, and give them a pretty objective perspective on how the tool is proving out for manufacturability," said Armburst. "There's an ongoing set of interest in the supplier community, and I think we can do more."

It's unlikely that this will be enough, however, to offset the the R&D funding gap. If it was projected to be $6-9B five years ago, it can only have gotten bigger due to the deepest recession and most dramatic reduction in capex spending the industry has ever seen. Executives at equipment suppliers look down the road and see that new technologies, such as FinFETs and high mobility transistors with III-V channels, are probably feasible, but openly question whether it's possible given R&D spending constraints.

The conventional wisdom is that scaling will continue at the traditional pace defined by Moore's Law well into the future. Companies are just now ramping 32nm devices into volume production, and the industry is on track to move to the 22nm node in 2011. That will be followed by 15nm in the 2014-15 timeframe and the 11nm node in 2017-18. Further scaling to 8 and 5nm nodes will occur beyond 2020, perhaps enabled by silicon nanowires.

Such continued scaling is called More Moore (not to be confused with More than Moore, which constitutes the integrated of devices with diverse functionality, such as sensors, batteries, passive components, microprocessors and energy harvesting devices). The massive R&D spending gap, however, is making another scenario increasingly likely: No More Moore.

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