Improved tungsten deposition for 3Xnm logic, memory


Novellus Systems has developed a new tungsten deposition process that can reduce contact and line resistance at the 3Xnm node versus conventional tungsten CVD. Dubbed "LRWxT," the new approach, when used with the company's Altus Max system, results in highly conformal large grain size films with lower tungsten bulk resistivity.

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Kelvin contact resistance measurements obtained from 55nm N-type doped diffused contacts, showing reduced Rc with PNLxT, and additional Rc decrease with LRWxT. (Source: Novellus Systems; data courtesy of NEC Electronics)

At 32nm and beyond, thinner tungsten (W) films are required to fill smaller critical dimensions (CD), but their higher resistivity will keep scaling with each node progression. The new LRWxT tungsten deposition process involves three steps: a <20Å thick nucleation layer is deposited; a low-resistivity tungsten (LRWxT) treatment step is applied to promote growth of the low resistivity bulk film; and an optimized CVD-W film is deposited for the bulk fill of nanometer-sized structures. Filled features contain larger tungsten grains than either conventional silane-based nucleation or PNLxT process; the larger grain structure lowers the contact resistance of NiSi contacts by 20%-30%, the company claims.

The process has been tested on device features provided by NEC Electronics; results were presented at the Advanced Metallization Conference in October. — J.M.

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