The era of fully-depleted devices
Bich-Yen Nguyen, Carlos Mazur??, Soitec, Bernin, France
The technical superiority of fully-depleted transistors is well understood and has been largely discussed by high profile teams around the world from the IC industry and academia. Fully-depleted devices enable the IC industry to overcome the roadblocks that the conventional planar bulk technology faces in the scaling race. The fabrication of fully-depleted transistors can be achieved through two basic approaches: planar, or vertical fin fully-depleted transistors. The planar fully-depleted transistors are built on ultra-thin silicon-on-insulator (FDSOI) while the FinFETs are built on ultra-narrow fins, which are carved into the silicon using a bulk or SOI substrate as shown in Figs. 1a, 1b, and 1c, respectively.
|Figure 1. Device architecture options: a) planar FDSOI, b) FinFET SOI, and c) FinFET bulk.|
The IC industry is in front of a choice of CMOS architecture: continue with the evolutionary scaling path through adoption of the planar FDSOI, or introduce 3D transistors, known as FinFET or TriGate. Either choice comes with challenges of its own. This review will discuss the tradeoffs and challenges of FinFETs and planar FDSOI adoption.
Planar fully-depleted SOI devices
Ultra-thin body (UTB) SOI device architecture is extensively investigated to suppress the short channel effects (SCE) for scaling gate length beyond 30nm and to lower the sub-threshold leakage as projected by the International Technology Roadmap for Semiconductors. The combination of high mobility channels and UTB SOI devices is most appealing for high density, high performance and low power applications. The future nodes are driving numerous substrate solutions. Today's partially-depleted (PD) or bulk transistor architecture implemented for high performance processors and low power SOC may evolve into a fully-depleted (FD) approach with planar single gate transistors or with multiple gate structures as shown in Fig. 1 [1-3].
Planar FDSOI devices for electrostatic control. The thickness uniformity is the key parameter to control the Vt variation and SCE of the planar FDSOI device. Typical uniformity requirements include on-wafer uniformity and wafer-to-wafer uniformity. Both of them combined are classified as layer total thickness variation (LTTV) and define the overall manufacturing process window for thickness uniformity. LTTV has to be achieved at the nanometer or sub-nanometer range for the UTSOI layer for all wafers and all sites in order to meet the FD specifications. The SmartCut process optimization demonstrated an LTTV of +/0.5nm, fully compatible with the most demanding FD technologies (Fig. 2). At the same time, if a very thin BOX is required to extend the FD technology to further nodes, the BOX layer thickness can be decreased down to 10nm, and even below, with nanometer-range thickness uniformity and without degrading basic electrical properties of devices [4,5].
|Figure 2. Thickness uniformity of the SOI substrate with different BOX thickness.|
Even though planar single-gate FDSOI devices do not have as good a scalability as multi-gate devices, they offer the major advantage of full compatibility with existing manufacturing planar CMOS processing and the least disruption for design migration from the current bulk device architecture to planar FDSOI with the option to reuse the bulk-IPs for shortening the development time or time-to-market. Both FinFET and planar FDSOI feature an undoped channel to reduce random dopant fluctuation effects for improving Vt variation as shown in Fig. 3 . The FD devices with smaller Vt variation, steeper substhreshold slope and better short channel effect (SCE) enable the IC circuit functioning at lower operation voltage for reducing dynamic power consumption. The undoped channel devices also improve low-field mobility, thus the FD devices not only feature low power/leakage, but also high performance. The applicability of existing techniques for mobility enhancement used in planar bulk or PDSOI technologies can provide an additional boost in thin film devices [7,8]. Currently, most of these techniques are based on process-induced strain obtained from a contact etch stop layer, raised SiGe or SiC in the S/D regions . The thinner body channel reduces the external stress-induced effect, however, as the technology is scaled beyond 32/28nm, the impact of the induced-stress will be reduced with smaller gate pitch.
|Figure 3. Vt variability comparison: a) sigma delta Vt of FinFET Bulk vs. FinFET SOI, and b) published Pelgrom coefficient benchmarking for various device structures .|
Multi-gate devices for ultimate scalability and performance
There were several multi-gate device architectures investigated in the last decade to further improve the gate control of the channel for extending Moore's law to the end of the CMOS roadmap. Among these device architectures, the FinFET technique using either the SOI or bulk substrate as shown in Figs. 1b and 1c, respectively, has gained the most interest, because it features self-aligned gates and a self-aligned gate to source/drain. The FinFET is an ideal device architecture for improving electrostatic integrity and total inversion charge and it is possible, with volume inversion depending on the body dimension, these could result in a higher drive current, excellent SCE, near-ideal sub-threshold slope (SS~60mV/decade) and a very small drain-induced barrier lowering (DIBL) . Ernst et al. reported an outstanding transconductance increase by more than 200% for the double-gate transistor . Numerical simulation shows the feasibility of multi-gate transistors with a gate-length as short as 10nm; and the recommended fin width is roughly half of the gate length (Lg) for FinFET devices. A FinFET with conducting channels on three sides of the fin was named TriGate MOSFET by Intel  and the fin width of the TriGate could be the same dimension as Lg. The advantages of this structure include improving SCE, performance and topology. However, this device requires the gate dielectric to be uniform on all three sides of the fin body and at the corner in order to avoid multiple threshold and reliability issues.
The FinFET transistor performance and density are very promising with a high aspect ratio (AR) of fin height/fin width and a tight fin pitch. The real challenge of the FinFET structure is to precisely control the fin width and fin height dimensions and have the ability to scale the fin width down to the sub-20nm regime and precisely control these parameters during manufacture. Moreover, controlling the gate length dimension over a high AR fin body is critical. The tight process control is necessary to avoid the process-induced performance and leakage variation. The fin width is controlled by lithography or by using the spacer as hard masks, which could induce the fin line edge and line width roughness. The fin etch needs to be optimized to reduce surface damage to minimize the performance degradation for both FinFET-SOI and FinFET-Bulk. The fin height also plays an important role in controlling the performance and threshold voltage variation . In this case, the fin height of the FinFET-SOI can be precisely controlled by the SOI thickness as shown in Fig. 2, while the fin height of the FinFET-Bulk is defined by recessing of the oxide in the shallow trench isolation (STI) . The fin height variability is not only caused by the STI oxide recess, but also contributed by a few other process parameters such as hard mask, trench etch, channel stop process, loading effect, etc. Figure 3 compares transistor matching characteristics of different device architectures. Results indicated that planar FDSOI has achieved the smallest Vt variation or AVt (Pelgrom coefficient) among all the devices having the same gate dimension. The FinFET-SOI has a similar AVt value as planar FDSOI, but with a longer gate length. It was also demonstrated by imec (Fig. 3, inset) that FinFET-SOI with better fin height control and a purely undoped channel (without channel stopping implant) has a smaller Vt variation than FinFET-Bulk .
Multi-Vt solution for fully-depleted devices
There are a few solutions that can be used for tuning the threshold voltage (Vt) for fully-depleted devices to meet the performance and power requirements. The first solution is channel counter doping, but this has a variability compromise. The second solution is using the work function (WF) of the gate electrodes: top gate and bottom gate, or ground plane (GP). In FDSOI devices, in contrast to bulk, the WF of the top gate electrode is only about150mV from the midgap. Webber, et al., proposed the simple integration of two different metal gates, TiN and TaAlN, and the doping of two ground planes (GP) below the BOX in order to obtain the four Vts for both nMOS and pMOS without back bias as shown in Fig. 4a. The use of ultra-thin SOI and buried oxide (UTBB) substrate for planar FDSOI enables both multiple Vts and performance/power management techniques using forward and reserved back bias as demonstrated in Fig. 4b by Liu et al. .
|Figure 4. Multi-Vt option for planar FDSOI: a) four Vt values of FDSOI with two different near mid-gap metal gate electrodes and two ground-plane or back gate dopants, cb Vt tuning option for FDSOI on thin BOX with back bias (-2V-2V).|
In FinFETs, the multi-Vt tuning process can be more complex with large variations caused by the fin topology and tighter fin/gate pitch . The Vt tuning options for the FinFET are the WF of the gate electrode, channel doping, and sizing gate or fin. The separation of the gate is possible for independent gate bias features with an area penalty.
|Table 1. Assessment of various device architectures.|
Table 1 shows a summary of the trade-off between these device architectures (i.e., planar FDSOI, FinFET-SOI, and FinFET-bulk). All these devices feature the fully depleted advantages of improving SCE, steep SS and smaller DIBL. The main distinction of planar FDSOI is shorter time to market due to a simpler integration and compatible to existing CMOS processes. Planar FDSOI can exceed the AC performance as compared to 28nm and 20nm bulk at Vdd as low as 0.7V without using any performance boosters [15,16], yet some existing performance boosters can be implemented for further enhancement. Concerning SOI cost impact, a comprehensive cost analysis study by IC Knowledge concludes that FDSOI circuits offer the most cost effective solution due to process simplicity for the multi-Vt solution compared to the 22nm bulk . Moreover, with SOI's superior isolation there are opportunities to integrate power devices, RF and logic devices for increasing SOC performance and functionalities. For FinFET circuit, the impact of parasitic capacitance and its variation must be carefully studied, the penalty of achieving higher area efficiency and current with high AR may bring down the dynamic power benefits due to parasitic capacitance increase. Fundamentally, vertical device architecture introduces more edges and sides, inevitably exposing the device to more coupling and variation effects. This puts another level of demand on device design and maybe even new restrictions.
After more than 10 years of development, the era of fully-depleted devices has begun. Fully-depleted devices, both planar FDSOI and vertical multi-gate architecture feature an undoped channel to eliminate the RDF, and excellent gate control that has resulted in better SCE, steeper sub-threshold slope, small DIBL, greater low-field mobility, and low leakage. Published data have shown the planar FDSOI devices with thin BOX and GP improve SCE for scaling Lg down to the 11nm node and the silicon thickness requirement is >4nm (planar FDSOI with thin BOX is scalable down to the 11nm node and meets the DIBL of 100mV/V requirement). Excellent ultra-thin SOI and BOX thickness uniformity across wafer and wafer-to wafer have been demonstrated and are ready for high-volume manufacturing in early 2012. Record low Vt variation had been shown for planar FDSOI as compared to other device architectures with the same Lg at 22nm. The tight Vt variation and steep SS characteristic can enable the circuit to be operated at low Vdd for low power consumption. Another advantage of the planar FDSOI is multi-Vt solution and back-bias capability for performance and power management with much simpler integration as compared to the FinFET approach. In addition, the process integration of planar FDSOI is compatible with existing CMOS processing, thus enabling a shorter time-to-market and does not require excess capital investment for manufacturing. Such fully-depleted devices promise excellent performance ??? high circuit density at very low power consumption??? a critically important attribute for the rapidly growing realm of portable consumer electronics such as smart phones, tablets and mobile internet devices. The superior electrostatic characteristics of multi-gate devices such as FinFET enable ultimate scaling with good performance and low leakage. Producing and controlling fin and gate dimensions in high-volume manufacturing for the 22nm node has been announced, but extendibility to the end of the CMOS road map still needs to be proven.
We acknowledge helpful discussions and advice provided by many colleagues at Soitec, LETI, STMicroelectronics, IBM, IMEC and Global Froundries. SmartCut is a trademark of Soitec.
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Bich-Yen Nguyen received her BS in chemical engineering at the U. of Texas in Austin and is a senior fellow at Soitec, 1010 Land Creek Cove, Austin, Texas 78733; ph.: 1-979-997-0179; email: email@example.com. Carlos Mazur?? received his two doctorates in physics, one from the U. of Grenoble, France, and the other from the Technical U. of Munich, Germany, and is EVP and CTO at Soitec.
Solid State Technology | Volume 54 | Issue 10 | November 2011